Texas Instruments MSP430F663x User Manual

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PRODUCTPREVIEW

MSP430F663x

DRAFT ONLY

www.ti.com

FEATURES

• Low Supply-Voltage Range, 1.8 V to 3.6 V • Two Universal Serial Communication

• Ultralow Power Consumption – Active Mode (AM): TBD μA/MHz – Standby Mode (LPM3 WDT Mode): TBD μA – Off Mode (LPM4 RAM Retention): TBD μA – Shutdown Mode (LPM5 RTC Mode): TBD μA – Shutdown Mode (LPM5): TBD μA

• Wake-Up From Standby Mode in Less Than 5 μs

• 16-Bit RISC Architecture, Extended Memory, up to 20-MHz System Clock • Full-Speed Universal Serial Bus (USB)

• Flexible Power Management System – Integrated USB-PHY – Fully Integrated LDO With Programmable – Integrated 3.3-V/1.8-V USB Power System

Regulated Core Supply Voltage

– Supply Voltage Supervision, Monitoring,

and Brownout

• Unified Clock System – FLL Control Loop for Frequency and Autoscan Feature

Stabilization

– Low Power/Low Frequency Internal Clock With Synchronization

Source (VLO)

– Low Frequency Trimmed Internal Reference

Source (REFO) – 32-kHz Crystals (XT1) – High-Frequency Crystals Up to 32 MHz Operations

(XT2)

• 16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers

• 16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers

• 16-Bit Timer TA2, Timer_A With Three Capture/Compare Registers

• 16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers

MIXED SIGNAL MICROCONTROLLER

Interfaces – USCI_A0 and USCI_A1 Each Supporting

– Enhanced UART supporting

Auto-Baudrate Detection – IrDA Encoder and Decoder – Synchronous SPI

– USCI_B0 and USCI_B1 Each Supporting

– I2C – Synchronous SPI

– Integrated USB-PLL – Eight Input, Eight Output Endpoints

• 12-Bit Analog-to-Digital (A/D) Converter With Internal Shared Reference, Sample-and-Hold,

• Dual 12-Bit Digital-to-Analog (D/A) Converters

• Comparator

• Integrated LCD Driver With Contrast Control for up to 160 Segments

• Hardware Multiplier Supporting 32-Bit

• Flash Memory – Serial Onboard Programming, No External

Programming Voltage Needed

– Enhanced Data Integrity

• Six-Channel Internal DMA

• Real-Time Clock Module With Supply Voltage Backup Switch

• Family Members are Summarized in Table 1

• For Complete Module Descriptions, See the

MSP430x5xx/MSP430x6xx Family User's Guide

(SLAU208)

SLAS566 –OCTOBER 2009

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

PRODUCTPREVIEW

MSP430F663x

DRAFT ONLY

SLAS566 –OCTOBER 2009

DESCRIPTION

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 μs.

The MSP430F663x series are microcontroller configurations with four 16-bit timers, a high performance 12-bit analog-to-digital (A/D) converter, two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, comparator, USB 2.0, and up to 74 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, hand-held meters, etc.

Family members available are summarized in Table 1.

Device I/O

MSP430F6638 256 16 + 2 5, 3, 3 7 2 2 2 12 74

MSP430F6637

MSP430F6636

MSP430F6635

MSP430F6634

MSP430F6633

MSP430F6632

MSP430F6631

MSP430F6630

(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use. (2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4) Product Preview

Flash SRAM Timer_A Timer_B ADC12_A DAC12_A Comp_B Package

(KB) (KB)

(4)

192 16 + 2 5, 3, 3 7 2 2 2 12 74

(4)

128 16 + 2 5, 3, 3 7 2 2 2 12 74

(4)

256 16 + 2 5, 3, 3 7 2 2 - 12 74

(4)

192 16 + 2 5, 3, 3 7 2 2 - 12 74

(4)

128 16 + 2 5, 3, 3 7 2 2 - 12 74

(4)

256 16 + 2 5, 3, 3 7 2 2 - - 12 74

(4)

192 16 + 2 5, 3, 3 7 2 2 - - 12 74

(4)

128 16 + 2 5, 3, 3 7 2 2 - - 12 74

(1) (2) (3)

Table 1. Family Members

USCI

Channel A: Channel B: UART/IrDA/

SPI

SPI/I2C

www.ti.com

(Ch) (Ch) (Ch) Type

12 ext / 100 PZ,

4 int 113 ZQW

12 ext / 100 PZ,

4 int 113 ZQW

12 ext / 100 PZ,

4 int 113 ZQW

12 ext / 100 PZ,

4 int 113 ZQW

12 ext / 100 PZ,

4 int 113 ZQW

12 ext / 100 PZ,

4 int 113 ZQW

100 PZ,

113 ZQW

100 PZ,

113 ZQW

100 PZ,

113 ZQW

PRODUCTPREVIEW

MSP430F663x

DRAFT ONLY

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SLAS566 –OCTOBER 2009

Ordering Information

–40°C to 85°C MSP430F6634IPZ

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/package.

(3) Product preview.

PLASTIC 100-PIN TQFP (PZ) PLASTIC 113-BALL BGA (ZQW)

MSP430F6638IPZ MSP430F6638IZQW MSP430F6637IPZ MSP430F6636IPZ MSP430F6635IPZ

MSP430F6633IPZ MSP430F6632IPZ MSP430F6631IPZ MSP430F6630IPZ

PACKAGED DEVICES

(3) (3) (3) (3) (3) (3) (3) (3)

(1)

(2)

MSP430F6637IZQW MSP430F6636IZQW MSP430F6635IZQW MSP430F6634IZQW MSP430F6633IZQW MSP430F6632IZQW MSP430F6631IZQW MSP430F6630IZQW

(3) (3) (3) (3) (3) (3) (3) (3) (3)

PRODUCTPREVIEW

Unified

Clock

System

256KB 192KB 128KB

Flash

MCLK

ACLK

SMCLK

I/OPorts

P1/P2

2×8I/Os

Interrupt

Capability

1×16I/Os

CPUXV2

and

Working

Registers

EEM

(L:8+2)

XIN

XOUT

JTAG/

Interface/

PortPJ

SBW

PA PB PC PD

DMA

6Channel

XT2IN

XT OUT2

Power

Management

LDO SVM/ Brownout

SVS

SYS

Watchdog

P2Port

Mapping

Controller

I/OPorts

P3/P4

2×8I/Os

Interrupt

Capability

1×16I/Os

I/OPorts

P5/P6

2×8I/Os

1×16I/Os

I/OPorts

P7/P8

1×6I/Os

1×14I/Os

1×8I/Os

I/OPorts

1×8I/Os

MPY32

TA0

Timer_A

5CC

Registers

TA1and

TA2

2Timer_A

eachwith

3CC

Registers

TB0

Timer_B

7CC

Registers

RTC_B

Battery Backup System

CRC16

USCI0,1

Ax:UART,

IrDA,SPI

Bx:SPI,I2C

ADC12_A

200KSPS

16Channels (12ext/4int)

Autoscan

12Bit

DVCCDVSSAVCCAV

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V,2.0V,

2.5V

DAC12_A

12bit 2channels voltageout

LCD_B

160

Segments

USB

Full-speed

Comp_B

EDI

Enhanced

Data

Integrity

PJ.x

16KB RAM

+2KBRAM USBBuffer

+8BBackup

RAM

Unified

Clock

System

256KB 192KB 128KB

Flash

16KB RAM

+2KBRAM USBBuffer

+8BBackup

RAM

MCLK

ACLK

SMCLK

I/OPorts

P1/P2

2×8I/Os

Interrupt

Capability

1×16I/Os

CPUXV2

and

Working

Registers

EEM

(L:8+2)

XIN

XOUT

JTAG/

Interface/

PortPJ

SBW

PA PB PC PD

DMA

6Channel

XT2IN

XT OUT2

Power

Management

LDO SVM/ Brownout

SVS

SYS

Watchdog

P2Port

Mapping

Controller

I/OPorts

P3/P4

2×8I/Os

Interrupt

Capability

1×16I/Os

I/OPorts

P5/P6

2×8I/Os

1×16I/Os

I/OPorts

P7/P8

1×6I/Os

1×14I/Os

1×8I/Os

I/OPorts

1×8I/Os

MPY32

TA0

Timer_A

5CC

Registers

TA1and

TA2

2Timer_A

eachwith

3CC

Registers

TB0

Timer_B

7CC

Registers

CRC16

USCI0,1

Ax:UART,

IrDA,SPI

Bx:SPI,I2C

ADC12_A

200KSPS

16Channels (12ext/4int)

Autoscan

12Bit

DVCCDVSSAVCCAV

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V,2.0V,

2.5V

LCD_B

160

Segments

USB

Full-speed

Comp_B

EDI

Enhanced

Data

Integrity

PJ.x

RTC_B

Battery Backup System

MSP430F663x

DRAFT ONLY

SLAS566 –OCTOBER 2009

Functional Block Diagram, MSP430F6638, MSP430F6637, MSP430F6636

Functional Block Diagram, MSP430F6635, MSP430F6634, MSP430F6633

www.ti.com

PRODUCTPREVIEW

Unified

Clock

System

256KB 192KB 128KB

Flash

MCLK

ACLK

SMCLK

I/OPorts

P1/P2

2×8I/Os

Interrupt

Capability

1×16I/Os

CPUXV2

and

Working

Registers

EEM

(L:8+2)

XIN

XOUT

JTAG/

Interface/

PortPJ

SBW

PA PB PC PD

DMA

6Channel

XT2IN

XT OUT2

Power

Management

LDO SVM/ Brownout

SVS

SYS

Watchdog

P2Port

Mapping

Controller

I/OPorts

P3/P4

2×8I/Os

Interrupt

Capability

1×16I/Os

I/OPorts

P5/P6

2×8I/Os

1×16I/Os

I/OPorts

P7/P8

1×6I/Os

1×14I/Os

1×8I/Os

I/OPorts

1×8I/Os

MPY32

TA0

Timer_A

5CC

Registers

TA1and

TA2

2Timer_A

eachwith

3CC

Registers

TB0

Timer_B

7CC

Registers

CRC16

USCI0,1

Ax:UART,

IrDA,SPI

Bx:SPI,I2C

DVCCDVSSAVCCAV

P1.x P2.x

P3.x

P4.x

P5.x P6.x

P7.x

P8.x P9.x

RST/NMI

REF

Reference

1.5V,2.0V,

2.5V

LCD_B

160

Segments

USB

Full-speed

Comp_B

EDI

Enhanced

Data

Integrity

PJ.x

RTC_B

Battery Backup System

16KB RAM

+2KBRAM USBBuffer

+8BBackup

RAM

MSP430F663x

DRAFT ONLY

www.ti.com

Functional Block Diagram, MSP430F6632, MSP430F6631, MSP430F6630

SLAS566 –OCTOBER 2009

PRODUCTPREVIEW

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P6.4/CB4/A4

P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1

P7.4/CB8/A12

P7.5/CB9/A13 P7.6/CB10/A14/DAC0 P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+ P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2/R23

LCDCAP/R33

COM0

P5.3/COM1/S42

P9.7/S0 P9.6/S1 P9.5/S2 P9.4/S3 P9.3/S4 P9.2/S5 P9.1/S6 P9.0/S7 P8.7/S8 P8.6/UCB1SOMI/UCB1SCL/S9 P8.5/UCB1SIMO/UCB1SDA/S10 DVCC2 DVSS2

P2.0/P2MAP0

MSP430F6638 MSP430F6637 MSP430F6636

PZPACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2/S36

P1.4/TA0.3/S35

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4/COM2/S41

P5.5/COM3/S40

P1.0/TA0CLK/ACLK/S39

P3.0/TA1CLK/CBOUT/S31

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P1.6/TA0.1/S33

P1.7/TA0.2/S32

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.5/TA0.4/S34

P3.3/TA1.2/S28

P3.4/TA2CLK/SMCLK/S27

P3.5/TA2.0/S26

P3.6/TA2.1/S25

P3.7/TA2.2/S24

P4.0/TB0.0/S23

P4.2/TB0.2/S21 P4.1/TB0.1/S22

P4.4/TB0.4/S19 P4.3/TB0.3/S20

P4.6/TB0.6/S17 P4.5/TB0.5/S18

P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16

P8.4 /S11/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

MSP430F663x

DRAFT ONLY

SLAS566 –OCTOBER 2009

Pin Designation, MSP430F6638IPZ, MSP430F6637IPZ, MSP430F6636IPZ

www.ti.com

PRODUCTPREVIEW

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6

P6.7/CB7/A7 P7.4/CB8/A12 P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15 P5.0/VREF+/VeREF+ P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2/R23

LCDCAP/R33

COM0

P5.3/COM1/S42

P9.7/S0 P9.6/S1 P9.5/S2 P9.4/S3 P9.3/S4 P9.2/S5 P9.1/S6 P9.0/S7 P8.7/S8 P8.6/UCB1SOMI/UCB1SCL/S9 P8.5/UCB1SIMO/UCB1SDA/S10 DVCC2 DVSS2

P2.0/P2MAP0

MSP430F6635 MSP430F6634 MSP430F6633

PZPACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2/S36

P1.4/TA0.3/S35

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4/COM2/S41

P5.5/COM3/S40

P1.0/TA0CLK/ACLK/S39

P3.0/TA1CLK/CBOUT/S31

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P1.6/TA0.1/S33

P1.7/TA0.2/S32

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.5/TA0.4/S34

P3.3/TA1.2/S28

P3.4/TA2CLK/SMCLK/S27

P3.5/TA2.0/S26

P3.6/TA2.1/S25

P3.7/TA2.2/S24

P4.0/TB0.0/S23

P4.2/TB0.2/S21 P4.1/TB0.1/S22

P4.4/TB0.4/S19 P4.3/TB0.3/S20

P4.6/TB0.6/S17 P4.5/TB0.5/S18

P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16

P8.4 /S11/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

MSP430F663x

DRAFT ONLY

www.ti.com

Pin Designation, MSP430F6635IPZ, MSP430F6634IPZ, MSP430F6633IPZ

SLAS566 –OCTOBER 2009

PRODUCTPREVIEW

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

P6.4/CB4 P6.5/CB5 P6.6/CB6 P6.7/CB7 P7.4/CB8 P7.5/CB9

P7.6/CB10

P7.7/CB11 P5.0/VREF+/VeREF+ P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2/R23

LCDCAP/R33

COM0

P5.3/COM1/S42

P9.7/S0 P9.6/S1 P9.5/S2 P9.4/S3 P9.3/S4 P9.2/S5 P9.1/S6 P9.0/S7 P8.7/S8 P8.6/UCB1SOMI/UCB1SCL/S9 P8.5/UCB1SIMO/UCB1SDA/S10 DVCC2 DVSS2

P2.0/P2MAP0

MSP430F6632 MSP430F6631 MSP430F6630

PZPACKAGE

(TOP VIEW)

P6.3/CB3

P6.2/CB2

P6.1/CB1

P6.0/CB0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2/S36

P1.4/TA0.3/S35

AVSS2

P5.6/DMAE0

P5.4/COM2/S41

P5.5/COM3/S40

P1.0/TA0CLK/ACLK/S39

P3.0/TA1CLK/CBOUT/S31

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P1.6/TA0.1/S33

P1.7/TA0.2/S32

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.5/TA0.4/S34

P3.3/TA1.2/S28

P3.4/TA2CLK/SMCLK/S27

P3.5/TA2.0/S26

P3.6/TA2.1/S25

P3.7/TA2.2/S24

P4.0/TB0.0/S23

P4.2/TB0.2/S21 P4.1/TB0.1/S22

P4.4/TB0.4/S19 P4.3/TB0.3/S20

P4.6/TB0.6/S17 P4.5/TB0.5/S18

P8.0/TB0CLK/S15 P4.7/TB0OUTH/SVMOUT/S16

P8.4 /S11/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

MSP430F663x

DRAFT ONLY

SLAS566 –OCTOBER 2009

Pin Designation, MSP430F6632IPZ, MSP430F6631IPZ, MSP430F6630IPZ

www.ti.com

PRODUCTPREVIEW

A1 A2

A5 A6

A8 A9 A10

A11 A12

B1 B2

B5 B6

B8 B9 B10

B11 B12

C1 C2 C3 C11 C12

D1 D2 D4

D5 D6

D8 D9

D11 D12

E1 E2 E4

E5 E6

E8 E9

E11 E12

F1 F2 F4

F5 F8 F9

F11 F12

G1 G2 G4

G5 G8 G9

G11 G12

J1 J2 J4

J5 J6

J8 J9

J11 J12

H1 H2 H4

H5 H6

H8 H9

H11 H12

K1 K2 K11 K12

L1 L2

L5 L6

L8 L9 L10

L11 L12

M1 M2

M3 M5 M6

M8 M9 M10

M11 M12

ZQWPACKAGE

(TOP VIEW)

MSP430F663x

DRAFT ONLY

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SLAS566 –OCTOBER 2009

Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW, MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW, MSP430F6631IZQW, MSP430F6630IZQW

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TERMINAL

NAME

P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4

P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5

P6.6/CB6/A6/DAC0 3 B1 I/O

P6.7/CB7/A7/DAC1 4 C2 I/O

P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8

P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9

P7.6/CB10/A14/DAC0 7 D2 I/O

P7.7/CB11/A15/DAC1 8 D1 I/O

P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC

P5.1/VREF-/VeREF- 10 E4 I/O Negative terminal for the ADC's reference voltage for both sources, the internal

AVCC1 11 Analog power supply AVSS1 12 F2 Analog ground supply

XIN 13 F1 I Input terminal for crystal oscillator XT1 XOUT 14 G1 O Output terminal of crystal oscillator XT1 AVSS2 15 G2 Analog ground supply

P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC (not available on '6632, '6631, '6630 devices)

P2.0/P2MAP0 17 G4 I/O

P2.1/P2MAP1 18 H2 I/O

P2.2/P2MAP2 19 J1 I/O

P2.3/P2MAP3 20 H4 I/O

P2.4/P2MAP4 21 J2 I/O

P2.5/P2MAP5 22 K1 I/O

Terminal Functions

E1,

I/O

(1)

General-purpose digital I/O Analog input A4 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O Analog input A5 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O Comparator_B input CB6 Analog input A6 – ADC (not available on '6632, '6631, '6630 devices) DAC12.0 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O Comparator_B input CB7 Analog input A7 – ADC (not available on '6632, '6631, '6630 devices) DAC12.1 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O Analog input A12 –ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O Analog input A13 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O Comparator_B input CB10 Analog input A14 – ADC (not available on '6632, '6631, '6630 devices) DAC12.0 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O Comparator_B input CB11 Analog input A15 – ADC (not available on '6632, '6631, '6630 devices) DAC12.1 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O Input for an external reference voltage to the ADC

General-purpose digital I/O reference voltage, or an external applied reference voltage

General-purpose digital I/O DMA external trigger input

General-purpose digital I/O with port interrupt and map-able secondary function Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

General-purpose digital I/O with port interrupt and map-able secondary function Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data

General-purpose digital I/O with port interrupt and map-able secondary function Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock

General-purpose digital I/O with port interrupt and map-able secondary function Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

General-purpose digital I/O with port interrupt and map-able secondary function Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out

General-purpose digital I/O with port interrupt and map-able secondary function Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in

NO. DESCRIPTION

PZ ZQW

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TERMINAL

NAME

P2.6/P2MAP6/R03 23 K2 I/O Default mapping: no secondary function

P2.7/P2MAP7/LCDREF/R13 24 L2 I/O

DVCC1 25 L1 Digital power supply DVSS1 26 M1 Digital ground supply

(2)

VCORE P5.2/R23 28 L3 I/O LCDCAP/R33 29 M3 I/O Input/output port of most positive analog LCD voltage (V1)

COM0 30 J4 O LCD common output COM0 for LCD backplane

P5.3/COM1/S42 31 L4 I/O LCD common output COM1 for LCD backplane

P5.4/COM2/S41 32 M4 I/O LCD common output COM2 for LCD backplane

P5.5/COM3/S40 33 J5 I/O LCD common output COM3 for LCD backplane

P1.0/TA0CLK/ACLK/S39 34 L5 I/O

P1.1/TA0.0/S38 35 M5 I/O

P1.2/TA0.1/S37 36 J6 I/O

P1.3/TA0.2/S36 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

P1.4/TA0.3/S35 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

P1.5/TA0.4/S34 39 L6 I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output

P1.6/TA0.1/S33 40 J7 I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output

P1.7/TA0.2/S32 41 M7 I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output

P3.0/TA1CLK/CBOUT/S31 42 L7 I/O

SLAS566 –OCTOBER 2009

Terminal Functions (continued)

NO. DESCRIPTION

PZ ZQW

27 M2 Regulated core power supply (internal usage only, no external current loading)

I/O

(1)

General-purpose digital I/O with port interrupt and map-able secondary function Input/output port of lowest analog LCD voltage (V5)

General-purpose digital I/O with port interrupt and map-able secondary function Default mapping: no secondary function External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4)

General-purpose digital I/O Input/output port of second most positive analog LCD voltage (V2)

General-purpose digital I/O LCD segment output S42

General-purpose digital I/O LCD segment output S41

General-purpose digital I/O LCD segment output S40

General-purpose digital I/O with port interrupt Timer TA0 clock signal TACLK input ACLK output (divided by 1, 2, 4, or 8) LCD segment output S39

General-purpose digital I/O with port interrupt Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output LCD segment output S38

General-purpose digital I/O with port interrupt Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input LCD segment output S37

General-purpose digital I/O with port interrupt LCD segment output S36

General-purpose digital I/O with port interrupt LCD segment output S35

General-purpose digital I/O with port interrupt LCD segment output S34

General-purpose digital I/O with port interrupt LCD segment output S33

General-purpose digital I/O with port interrupt LCD segment output S32

General-purpose digital I/O with port interrupt Timer TA1 clock input Comparator_B output LCD segment output S31

(2) VCORE is for internal usage only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, C

VCORE

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TERMINAL

NAME

P3.1/TA1.0/S30 43 H7 I/O Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P3.2/TA1.1/S29 44 M8 I/O Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

P3.3/TA1.2/S28 45 L8 I/O Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

P3.4/TA2CLK/SMCLK/S27 46 J8 I/O

P3.5/TA2.0/S26 47 M9 I/O Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P3.6/TA2.1/S25 48 L9 I/O Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

P3.7/TA2.2/S24 49 M10 I/O Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

P4.0/TB0.0/S23 50 J9 I/O Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output

P4.1/TB0.1/S22 51 M11 I/O Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output

P4.2/TB0.2/S21 52 L10 I/O Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output

P4.3/TB0.3/S20 53 M12 I/O Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output

P4.4/TB0.4/S19 54 L12 I/O Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output

P4.5/TB0.5/S18 55 L11 I/O Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output

P4.6/TB0.6/S17 56 K11 I/O Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output

P4.7/TB0OUTH/SVMOUT/S16 57 K12 I/O

P8.0/TB0CLK/S15 58 J11 I/O Timer TB0 clock input

P8.1/UCB1STE/UCA1CLK/S14 59 J12 I/O USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output

P8.2/UCA1TXD/UCA1SIMO/S13 60 H11 I/O USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out

Terminal Functions (continued)

NO. DESCRIPTION

PZ ZQW

I/O

(1)

General-purpose digital I/O with port interrupt LCD segment output S30

General-purpose digital I/O with port interrupt LCD segment output S29

General-purpose digital I/O with port interrupt LCD segment output S28

General-purpose digital I/O with port interrupt Timer TA2 clock input SMCLK output LCD segment output S27

General-purpose digital I/O with port interrupt LCD segment output S26

General-purpose digital I/O with port interrupt LCD segment output S25

General-purpose digital I/O with port interrupt LCD segment output S24

General-purpose digital I/O with port interrupt LCD segment output S23

General-purpose digital I/O with port interrupt LCD segment output S22

General-purpose digital I/O with port interrupt LCD segment output S21

General-purpose digital I/O with port interrupt LCD segment output S20

General-purpose digital I/O with port interrupt LCD segment output S19

General-purpose digital I/O with port interrupt LCD segment output S18

General-purpose digital I/O with port interrupt LCD segment output S17

General-purpose digital I/O with port interrupt Timer TB0: Switch all PWM outputs high impedance SVM output LCD segment output S16

General-purpose digital I/O LCD segment output S15

General-purpose digital I/O LCD segment output S14

General-purpose digital I/O LCD segment output S13

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TERMINAL

NAME

P8.3/UCA1RXD/UCA1SOMI/S12 61 H12 I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in

P8.4/UCB1CLK/UCA1STE/S11 62 G11 I/O USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable

DVSS2 63 G12 Digital ground supply DVCC2 64 F12 Digital power supply

P8.5/UCB1SIMO/UCB1SDA/S10 65 F11 I/O USCI_B1 SPI slave in/master out; USCI_B1 I2C data

P8.6/UCB1SOMI/UCB1SCL/S9 66 G9 I/O USCI_B1 SPI slave out/master in; USCI_B1 I2C clock

P8.7/S8 67 E12 I/O

P9.0/S7 68 E11 I/O

P9.1/S6 69 F9 I/O

P9.2/S5 70 D12 I/O

P9.3/S4 71 D11 I/O

P9.4/S3 72 E9 I/O

P9.5/S2 73 C12 I/O

P9.6/S1 74 C11 I/O

P9.7/S0 75 D9 I/O

VSSU 76 and USB PHY ground supply

PU.0/DP 77 A12 I/O PUR 78 B10 I/O USB pull-up resistor pin (open drain) PU.1/DM 79 A11 I/O VBUS 80 A10 USB LDO input (connect to USB power source)

VUSB 81 A9 USB LDO output V18 82 B9 USB regulated power (internal usage only, no external current loading) AVSS3 83 A8 Analog ground supply

P7.2/XT2IN 84 B8 I/O

P7.3/XT2OUT 85 B7 I/O VBAK 86 A7 Chip internal backup subsystem

VBAT 87 D8 Backup supply voltage P5.7/RTCCLK 88 D7 I/O DVCC3 89 A6 Digital power supply

Terminal Functions (continued)

B11 B12

I/O

(1)

General-purpose digital I/O LCD segment output S12

General-purpose digital I/O LCD segment output S11

General-purpose digital I/O LCD segment output S10

General-purpose digital I/O LCD segment output S9

General-purpose digital I/O LCD segment output S8

General-purpose digital I/O LCD segment output S7

General-purpose digital I/O LCD segment output S6

General-purpose digital I/O LCD segment output S5

General-purpose digital I/O LCD segment output S4

General-purpose digital I/O LCD segment output S3

General-purpose digital I/O LCD segment output S2

General-purpose digital I/O LCD segment output S1

General-purpose digital I/O LCD segment output S0

General-purpose digital I/O - controlled by USB control register USB data terminal DP

General-purpose digital I/O - controlled by USB control register USB data terminal DM

General-purpose digital I/O Input terminal for crystal oscillator XT2

General-purpose digital I/O Output terminal of crystal oscillator XT2

General-purpose digital I/O RTCCLK output

NO. DESCRIPTION

PZ ZQW

SLAS566 –OCTOBER 2009

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SLAS566 –OCTOBER 2009

TERMINAL

NAME

DVSS3 90 A5 Digital ground supply TEST/SBWTCK 91 B6 I

PJ.0/TDO 92 B5 I/O

PJ.1/TDI/TCLK 93 A4 I/O

PJ.2/TMS 94 E7 I/O

PJ.3/TCK 95 D6 I/O

RST/NMI/SBWTDIO 96 A3 I/O Non-maskable interrupt input

P6.0/CB0/A0 97 B4 I/O Comparator_B input CB0

P6.1/CB1/A1 98 B3 I/O Comparator_B input CB1

P6.2/CB2/A2 99 A2 I/O Comparator_B input CB2

P6.3/CB3/A3 100 D5 I/O Comparator_B input CB3

Reserved N/A F8

Terminal Functions (continued)

E5 E6 E8 F4 F5

G5 G8 H5 H8 H9

I/O

(1)

Test mode pin – select digital I/O on JTAG pins Spy-bi-wire input clock

General-purpose digital I/O Test data output port

General-purpose digital I/O Test data input or test clock input

General-purpose digital I/O Test mode select

General-purpose digital I/O Test clock

Reset input active low Spy-bi-wire data input/output

General-purpose digital I/O Analog input A0 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O Analog input A1 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O Analog input A2 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O Analog input A3 – ADC (not available on '6632, '6631, '6630 devices)

Reserved BGA package balls. It is recommended to connect to ground (DVSS/AVSS).

NO. DESCRIPTION

PZ ZQW

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Program Counter

PC/R0

Stack Pointer SP/R1

Status Register

SR/CG1/R2

Constant Generator CG2/R3

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R15

General-Purpose Register

R14

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SHORT-FORM DESCRIPTION

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 2 shows examples of the three types of instruction formats; the address modes are listed in Table 3.

SLAS566 –OCTOBER 2009

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 → R5 Single operands, destination only e.g., CALL R8 PC → (TOS), R8 → PC Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

ADDRESS MODE S

Indexed + + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)

Symbolic (PC relative) + + MOV EDE,TONI M(EDE) → M(TONI)

Absolute + + MOV &MEM, &TCDAT M(MEM) → M(TCDAT)

Indirect + MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)

Indirect auto-increment + MOV @Rn+,Rm MOV @R10+,R11

Immediate + MOV #X,TONI MOV #45,TONI #45 → M(TONI)

(1) S = source, D = destination

Table 2. Instruction Word Formats

Table 3. Address Mode Descriptions

(1)

SYNTAX EXAMPLE OPERATION

M(R10) → R11

R10 + 2 → R10

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Operating Modes

The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following seven operating modes can be configured by software:

• Active mode (AM) – All clocks are active

• Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – FLL loop control remains active

• Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active, MCLK is disabled

• Low-power mode 2 (LPM2) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator remains enabled – ACLK remains active

• Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator is disabled – ACLK remains active

• Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator is disabled – Crystal oscillator is stopped – Complete data retention

• Low-power mode 5 (LPM5) – Internal regulator disabled – No data retention – optional RTC clocked by low-frequency oscillator – Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4

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Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 4. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

System Reset

Power-Up, External Reset

Watchdog Timeout, Key Violation WDTIFG, KEYV (SYSRSTIV)

Flash Memory Key Violation

EDI Parity Error

System NMI

Vacant Memory Access

Flash Memory Access Violation

Watchdog Interval Timer Mode WDTIFG Maskable 0FFF2h 57

USCI_A0 Receive/Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) USCI_B0 Receive/Transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV)

USCI_A1 Receive/Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) USCI_B1 Receive/Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)

PMM

JTAG Mailbox

User NMI

NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG

Oscillator Fault (SYSUNIV)

Comp_B Comparator B interrupt flags (CBIV)

Timer TB0 TB0CCR0 CCIFG0 Timer TB0 Maskable 0FFF4h 58

ADC12_A

Timer TA0 TA0CCR0 CCIFG0 Timer TA0 Maskable 0FFE8h 52 USB_UBM USB interrupts (USBIV)

Timer TA1 TA1CCR0 CCIFG0 Timer TA1 Maskable 0FFE0h 48

I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)

I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)

DAC12_A

Timer TA2 TA2CCR0 CCIFG2 Timer TA2 Maskable 0FFCEh 39

I/O Port P3 P3IFG.0 to P3IFG.7 (P3IV) I/O Port P4 P4IFG.0 to P4IFG.7 (P4IV)

(4)

DMA Maskable 0FFE4h 50

LCD_B LCD_B Interrupt Flags (LCDBIV)

RTC_B Maskable 0FFD4h 42

(5)

SLAS566 –OCTOBER 2009

SYSTEM WORD

INTERRUPT ADDRESS

(1) (2)

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62

JMBOUTIFG (SYSSNIV)

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TBIV)

ADC12IFG0 to ADC12IFG15 (ADC12IV)

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,

DMA4IFG, DMA5IFG (DMAIV)

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)

DAC12_0IFG, DAC12_1IFG

TA2CCR1 CCIFG1 to TA2CCR2,

TA2IFG (TA2IV)

(1)

(1) (2)

(1) (3)

(3)

(1) (3)

(3)

(1) (3)

(3)

(1) (3)

(1) (3) (1) (3)

(1) (3)

(1)

(1) (3)

(3)

(1) (3)

(1) (3) (1) (3)

Reset 0FFFEh 63, highest

(Non)maskable 0FFFAh 61

Maskable 0FFF8h 60 Maskable 0FFF6h 59

Maskable 0FFF0h 56 Maskable 0FFEEh 55 Maskable 0FFECh 54 Maskable 0FFEAh 53

Maskable 0FFE6h 51

Maskable 0FFE2h 49

Maskable 0FFDEh 47 Maskable 0FFDCh 46 Maskable 0FFDAh 45 Maskable 0FFD8h 44 Maskable 0FFD6h 43

Maskable 0FFD2h 41 Maskable 0FFD0h 40

Maskable 0FFCCh 38 Maskable 0FFCAh 37

(1) Multiple source flags (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (3) Interrupt flags are located in the module. (4) Only on devices with peripheral module ADC12_A, otherwise reserved. (5) Only on devices with peripheral module DAC12_A, otherwise reserved.

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Table 4. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations (continued)

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

Reserved Reserved

(6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatability with other devices, it is recommended to reserve these locations.

Memory Organization

Memory (flash) Total Size 128KB 192KB 256KB Main: interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h

Main: code memory

EDI support software Total Size 4KB 4KB 4KB (ROM) 007FFFh-007000h 007FFFh-007000h 007FFFh-007000h

Sector 3 4 KB 4 KB 4 KB

Sector 2 4 KB 4 KB 4 KB

RAM

USB RAM

Information memory (flash)

Bootstrap loader (BSL) memory (flash)

Peripherals

(1) N/A = Not available. (2) USB RAM can be used as general purpose RAM when not used for USB operation.

(2)

Sector 1 4 KB 4 KB 4 KB

Sector 0 4 KB 4 KB 4 KB

SYSTEM WORD

INTERRUPT ADDRESS

0FFC8h 36

(6)

Table 5. Memory Organization

MSP430F6636 MSP430F6637 MSP430F6638 MSP430F6633 MSP430F6634 MSP430F6635 MSP430F6630 MSP430F6631 MSP430F6632

Bank 3 N/A N/A 64 KB

Bank 2 N/A 64 KB 64 KB

Bank 1 64 KB 64 KB 64 KB

027FFF-018000h 027FFF-018000h 027FFF-018000h

Bank 0 64 KB 64 KB 64 KB

017FFF-008000h 017FFF-008000h 017FFF-008000h

0063FFh–005400h 0063FFh–005400h 0063FFh–005400h

0053FFh–004400h 0053FFh–004400h 0053FFh–004400h

0043FFh–003400h 0043FFh–003400h 0043FFh–003400h

0033FFh–002400h 0033FFh–002400h 0033FFh–002400h

Size 2KB 2KB 2KB

RAM 0023FFh-001C00h 0023FFh-001C00h 0023FFh-001C00h

Info A 128 B 128 B 128 B

0019FFh–001980h 0019FFh–001980h 0019FFh–001980h

Info B 128 B 128 B 128 B

00197Fh–001900h 00197Fh–001900h 00197Fh–001900h

Info C 128 B 128 B 128 B

0018FFh–001880h 0018FFh–001880h 0018FFh–001880h

Info D 128 B 128 B 128 B

00187Fh–001800h 00187Fh–001800h 00187Fh–001800h

BSL 3 512 B 512 B 512 B

0017FFh–001600h 0017FFh–001600h 0017FFh–001600h

BSL 2 512 B 512 B 512 B

0015FFh–001400h 0015FFh–001400h 0015FFh–001400h

BSL 1 512 B 512 B 512 B

0013FFh–001200h 0013FFh–001200h 0013FFh–001200h

BSL 0 512 B 512 B 512 B

0011FFh–001000h 0011FFh–001000h 0011FFh–001000h

Size 4KB 4KB 4KB

000FFFh–000000h 000FFFh–000000h 000FFFh–000000h

(1)

037FFF-028000h 037FFF-028000h

⋮ ⋮

0FF80h 0, lowest

047FFF-038000h

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Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the device memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Memory Programming User's Guide, TI literature number

SLAU265.

Table 6. BSL Functions

BSL FUNCTION DEVICE OUTPUT SIGNAL

Data transmit P1.1

Data receive P1.2

Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

• Segment A can be locked separately.

SLAS566 –OCTOBER 2009

Enhanced Data Integrity (EDI)

The EDI feature provides additional functionality over the regular MSP430 flash memory controller. The main purpose of the EDI function is gaining higher reliability of flash content and overall system integrity in harsh environments and application areas requiring this feature. The additional level of security is reached by caluclating more dimensional checksums.

The on-chip EDI support software allows easily to use the different EDI features. The implementation cover the following functionality:

• Level #0

– User-defined or auto configuration of memory – Error patching of up to four addresses (4 Error Cache entries) – Handling of detected errors in an error list stored in RAM or flash – Restart on error

• Level #1:

– All functionality of level #0 implemenation – Recover on error – User-defined error handling

For Complete EDI Description, See the MSP430 On-Chip EDI Support Software User's Guide (SLAUxxx)

RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage, however all data is lost. Features of the RAM memory include:

• RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.

• Each sector 0 to n can be complete disabled, however data retention is lost.

• Each sector 0 to n automatically enters low power retention mode when possible.

• For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

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Backup RAM Memory

The Backup RAM provides a limited number of bytes of RAM that are retained during LPM5 and during operation from a backup supply in case the Battery Backup System module is implemented.

There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.

Peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx/MSP430x6xx Family User's Guide, literature number SLAU 208.

Digital I/O

There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete and port PJ contains four individual I/O ports.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Programmable drive strength on all ports.

• Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.

• Read/write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD).

Port Mapping Controller

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2.

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

0 PM_NONE None DV

4 PM_TB0CCR0B Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0 5 PM_TB0CCR1B Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1 6 PM_TB0CCR2B Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2 7 PM_TB0CCR3B Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3 8 PM_TB0CCR4B Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4 9 PM_TB0CCR5B Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5

10 PM_TB0CCR6B Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6

PM_CBOUT - Comparator_B output

PM_TB0CLK Timer TB0 clock input -

PM_ADC12CLK - ADC12CLK

PM_DMAE0 DMAE0 Input -

PM_SVMOUT - SVM output

PM_TB0OUTH -

PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)

PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)

PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI) PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)

PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)

Table 7. Port Mapping, Mnemonics and Functions

Timer TB0 high impedance input

TB0OUTH

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Table 7. Port Mapping, Mnemonics and Functions (continued)

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

17 PM_MCLK - MCLK 18 PM_E0 EDI test pin (open drain and direction controlled by EDI) 19 PM_E1 EDI test pin (open drain and direction controlled by EDI)

20 - 30 Reserved None DV

31 (0FFh)

(1) The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are

P2.7/P2MAP7/LCDREF/R1

(1)

ignored resulting in a read out value of 31.

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION

P2.0/P2MAP0

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6/R03 PM_NONE - DV

PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)

PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI) PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

PM_ANALOG

PM_UCB0STE/PM_UCA0 USCI_B0 SPI slave transmit enable (direction controlled by USCI - input) /

PM_UCB0SIMO/PM_UCB USCI_B0 SPI slave in master out (direction controlled by USCI) / USCI_B0 I2C

0SDA data (open drain and direction controlled by USCI)

PM_UCB0SOMI/PM_UCB USCI_B0 SPI slave out master in (direction controlled by USCI) / USCI_B0 I2C

0SCL clock (open drain and direction controlled by USCI)

PM_UCB0CLK/PM_UCA0 USCI_B0 clock input/output (direction controlled by USCI) / USCI_A0 SPI slave

PM_UCA0TXD/PM_UCA0 USCI_A0 UART TXD (direction controlled by USCI - output) / USCI_A0 SPI slave

SIMO in master out (direction controlled by USCI)

PM_UCA0RXD/PM_UCA0 USCI_A0 UART RXD (direction controlled by USCI - input) / USCI_A0 SPI slave

SOMI out master in (direction controlled by USCI)

PM_NONE - DV

Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross

currents when applying analog signals.

Table 8. Default Mapping

CLK USCI_A0 clock input/output (direction controlled by USCI)

STE transmit enable (direction controlled by USCI - input)

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Oscillator and System Clock

The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS) module that includes support for a 32 kHz watch crystal oscillator (XT1 LF mode - XT1 HF mode not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low-power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 5 μs. The UCS module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the

internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-controlled oscillator DCO.

• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made

available to ACLK.

• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by

same sources made available to ACLK.

• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

Power Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains

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programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_B)

The RTC_B module can be configured for real-time clock (RTC) and calendar mode providing seconds, minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in LPM5 mode and operation from a backup supply.

Watchdog Timer (WDT_A)

The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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System Module (SYS)

The SYS module handles many of the system functions within the device. These include power on reset and power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

INTERRUPT VECTOR

SYSRSTIV , System Reset SVMH_OVP (POR) 019Eh 12h

Table 9. System Module Interrupt Vector Registers

INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY

No interrupt pending 00h

Brownout (BOR) 02h Highest RST/NMI (BOR) 04h

DoBOR (BOR) 06h

LPM5 wakeup (BOR) 08h

Security violation (BOR) 0Ah

SVSL (POR) 0Ch

SVSH (POR) 0Eh

SVML_OVP (POR) 10h

DoPOR (POR) 14h

WDT timeout (PUC) 16h

WDT key violation (PUC) 18h

KEYV flash key violation (PUC) 1Ah

FLL unlock (PUC) 1Ch

Peripheral area fetch (PUC) 1Eh

PMM key violation (PUC) 20h

EDI Parity Error (PUC) 22h

Reserved 24h to 3Eh Lowest

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Table 9. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR

SYSSNIV , System NMI VMAIFG 019Ch 0Ah

SYSUNIV, User NMI 019Ah

SYSBERRIV, Bus Error EDI Error Cache hit (XHIT) 0198h 04h

INTERRUPT EVENT WORD ADDRESS OFFSET PRIORITY

No interrupt pending 00h

SVMLIFG 02h Highest

SVMHIFG 04h

DLYLIFG 06h

DLYHIFG 08h

JMBINIFG 0Ch

JMBOUTIFG 0Eh

VLRLIFG 10h VLRHIFG 12h Reserved 14h to 1Eh Lowest

No interrupt pending 00h

NMIFG 02h Highest OFIFG 04h

ACCVIFG 06h

BUSIFG 08h

Reserved 0Ah to 1Eh Lowest

No interrupt pending 00h

USB wait state timeout 02h Highest

EDI Parity Error (PERR) 06h

Reserved 08h to 1Eh Lowest

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DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral.

The USB timestamp generator also utilizes the channel 0, 1, and 2 DMA trigger assignments described in

Table 10.

Trigger

0 DMAREQ 1 TA0CCR0 CCIFG 2 TA0CCR2 CCIFG 3 TA1CCR0 CCIFG 4 TA1CCR2 CCIFG 5 TA2CCR0 CCIFG 6 TA2CCR2 CCIFG 7 TBCCR0 CCIFG 8 TBCCR2 CCIFG

9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 UCA0RXIFG 17 UCA0TXIFG 18 UCB0RXIFG 19 UCB0TXIFG 20 UCA1RXIFG 21 UCA1TXIFG 22 UCB1RXIFG 23 UCB1TXIFG 24 ADC12IFGx 25 DAC12_0IFG 26 DAC12_1IFG 27 USB FNRXD 28 USB ready 29 MPY ready 30 DMA5IFG DMA0IFG DMA1IFG DMA2IFG DMA3IFG DMA4IFG 31 DMAE0

(1) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC. (2) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC.

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Table 10. DMA Trigger Assignments

Channel

0 1 2 3 4 5

(1)

(2) (2)

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Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B.

The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C. The MSP430F663x series includes two complete USCI modules (n = 0 to 1).

Timer TA0

Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

34-P1.0 L5-P1.0 TA0CLK TACLK

34-P1.0 L5-P1.0 TA0CLK TACLK 35-P1.1 M5-P1.1 TA0.0 CCI0A 35-P1.1 M5-P1.1

36-P1.2 J6-P1.2 TA0.1 CCI1A 36-P1.2 J6-P1.2 40-P1.6 J7-P1.6 TA0.1 CCI1B 40-P1.6 J7-P1.6

37-P1.3 H6-P1.3 TA0.2 CCI2A 37-P1.3 H6-P1.3 41-P1.7 M7-P1.7 TA0.2 CCI2B 41-P1.7 M7-P1.7

38-P1.4 M6-P1.4 TA0.3 CCI3A 38-P1.4 M6-P1.4

SIGNAL SIGNAL SIGNAL SIGNAL

SMCLK SMCLK

39-P1.5 L6-P1.5 TA0.4 CCI4A 39-P1.5 L6-P1.5

(1) Only on devices with peripheral module ADC12_A.

Table 11. Timer TA0 Signal Connections

INPUT INPUT OUTPUT OUTPUT

ACLK ACLK

DV DV DV

DV DV

DV DV DV

SS SS

CCI0B

GND

CCI3B

GND

CCI4B

GND

MODULE

BLOCK

Timer NA NA

CCR0 TA0 TA0.0

CCR1 TA1 TA0.1

CCR2 TA2 TA0.2

CCR3 TA3 TA0.3

CCR4 TA4 TA0.4

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ADC12_A (internal)

ADC12SHSx = {1}

(1)

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Timer TA1

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

42-P3.0 L7-P3.0 TA1CLK TACLK

42-P3.0 L7-P3.0 TA1CLK TACLK 43-P3.1 H7-P3.1 TA1.0 CCI0A 43-P3.1 H7-P3.1

44-P3.2 M8-P3.2 TA1.1 CCI1A 44-P3.2 M8-P3.2

45-P3.3 L8-P3.3 TA1.2 CCI2A 45-P3.3 L8-P3.3

(1) Only on devices with peripheral module DAC12_A.

Table 12. Timer TA1 Signal Connections

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

ACLK ACLK

SMCLK SMCLK

CBOUT

(internal)

ACLK

(internal)

CCI0B

GND

CCI1B

GND

CCI2B

GND

MODULE

BLOCK

Timer NA NA

CCR0 TA0 TA1.0

CCR1 TA1 TA1.1

CCR2 TA2 TA1.2

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DAC12_A

(1)

DAC12_0, DAC12_1

(internal)

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Timer TA2

Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 13. Timer TA2 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

46-P3.4 J8-P3.4 TA2CLK TACLK

46-P3.4 J8-P3.4 TA2CLK TACLK 47-P3.5 M9-P3.5 TA2.0 CCI0A 47-P3.5 M9-P3.5

48-P3.6 L9-P3.6 TA2.1 CCI1A 48-P3.6 L9-P3.6

49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

ACLK ACLK

SMCLK SMCLK

CBOUT

(internal)

ACLK

(internal)

CCI0B

GND

CCI1B

GND

CCI2B

GND

MODULE

BLOCK

Timer NA NA

CCR0 TA0 TA2.0

CCR1 TA1 TA2.1

CCR2 TA2 TA2.2

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Timer TB0

Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER

PZ ZQW PZ ZQW

58-P8.0 J11-P8.0

P2MAPx

(1) Timer functions selectable via the port mapping controller. (2) Only on devices with peripheral module ADC12_A. (3) Only on devices with peripheral module DAC12_A.

(1)

P2MAPx

58-P8.0 J11-P8.0

(1)

P2MAPx

50-P4.0 J9-P4.0 TB0.0 CCI0A 50-P4.0 J9-P4.0

(1)

P2MAPx

51-P4.1 M11-P4.1 TB0.1 CCI1A 51-P4.1 M11-P4.1

(1)

P2MAPx

52-P4.2 L10-P4.2 TB0.2 CCI2A 52-P4.2 L10-P4.2

(1)

P2MAPx

53-P4.3 M12-P4.3 TB0.3 CCI3A 53-P4.3 M12-P4.3

(1)

P2MAPx

54-P4.4 L12-P4.4 TB0.4 CCI4A 54-P4.4 L12-P4.4

(1)

P2MAPx

55-P4.5 L11-P4.5 TB0.5 CCI5A 55-P4.5 L11-P4.5

(1)

P2MAPx

56-P4.6 K11-P4.6 TB0.6 CCI6A 56-P4.6 K11-P4.6

(1)

P2MAPx

(1)

Table 14. Timer TB0 Signal Connections

INPUT INPUT OUTPUT OUTPUT

SIGNAL SIGNAL SIGNAL SIGNAL

TB0CLK TB0CLK

ACLK ACLK

SMCLK SMCLK

TB0CLK TB0CLK

TB0.0 CCI0B P2MAPx DV

TB0.1 CCI1B P2MAPx DV

TB0.2 CCI2B P2MAPx

TB0.3 CCI3B P2MAPx DV

TB0.4 CCI4B P2MAPx DV

TB0.5 CCI5B P2MAPx DV

TB0.6 CCI6B P2MAPx DV

GND

GND DAC12_0, DAC12_1

GND

MODULE

BLOCK

Timer NA NA

CCR0 TB0 TB0.0

CCR1 TB1 TB0.1

CCR2 TB2 TB0.2

CCR3 TB3 TB0.3

CCR4 TB4 TB0.4

CCR5 TB5 TB0.5

CCR6 TB6 TB0.6

ADC12 (internal)

ADC12SHSx = {2}

ADC12 (internal)

ADC12SHSx = {3}

(1)

DAC12_A

(internal)

(1)

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P2MAPx

(2)

P2MAPx

(2)

P2MAPx

(3)

P2MAPx

(1)

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Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals.

ADC12_A

The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device.

LCD_B

The LCD_B driver generates the segment and common signals required to drive a Liquid Crystal Display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The module also provides an automatic blinking capability for individual segments.

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USB Universal Serial Bus

The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO, PHY, and PLL. The PLL is highly-flexible and can support a wide range of input clock frequencies. USB RAM, when not used for USB communication, can be used by the system.

Embedded Emulation Module (EEM)

The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM implemented on all devices has the following features:

• Eight hardware triggers/breakpoints on memory access

• Two hardware triggers/breakpoints on CPU register write access

• Up to ten hardware triggers can be combined to form complex triggers/breakpoints

• Two cycle counters

• Sequencer

• State storage

• Clock control on module level

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Peripheral File Map

MODULE NAME BASE ADDRESS OFFSET ADDRESS RANGE

Special Functions (refer to Table 16) 0100h 000h - 01Fh

PMM (refer to Table 17) 0120h 000h - 00Fh

Flash Control (refer to Table 18) 0140h 000h - 00Fh

CRC16 (refer to Table 19) 0150h 000h - 007h

RAM Control (refer to Table 20) 0158h 000h - 001h

Watchdog (refer to Table 21) 015Ch 000h - 001h

UCS (refer to Table 22) 0160h 000h - 01Fh SYS (refer to Table 23) 0180h 000h - 01Fh

Shared Reference (refer to Table 24) 01B0h 000h - 001h Port Mapping Control (refer to Table 25) 01C0h 000h - 003h Port Mapping Port P2 (refer to Table 25) 01D0h 000h - 007h

Port P1/P2 (refer to Table 26) 0200h 000h - 01Fh Port P3/P4 (refer to Table 27) 0220h 000h - 01Fh Port P5/P6 (refer to Table 28) 0240h 000h - 00Bh Port P7/P8 (refer to Table 29) 0260h 000h - 00Bh

Port P9 (refer to Table 30) 0280h 000h - 00Bh

Port PJ (refer to Table 31) 0320h 000h - 01Fh Timer TA0 (refer to Table 32) 0340h 000h - 02Eh Timer TA1 (refer to Table 33) 0380h 000h - 02Eh

(1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's

Guide (SLAU208).

Timer TB0 (refer to Table 34) 03C0h 000h - 02Eh Timer TA2 (refer to Table 35) 0400h 000h - 02Eh

Battery Backup (refer to Table 36) 0480h 000h - 01Fh

RTC_B (refer to Table 37) 04A0h 000h - 01Fh

32-bit Hardware Multiplier (refer to Table 38) 04C0h 000h - 02Fh

DMA General Control (refer to Table 39) 0500h 000h - 00Fh

DMA Channel 0 (refer to Table 39) 0510h 000h - 00Ah DMA Channel 1 (refer to Table 39) 0520h 000h - 00Ah DMA Channel 2 (refer to Table 39) 0530h 000h - 00Ah DMA Channel 3 (refer to Table 39) 0540h 000h - 00Ah DMA Channel 4 (refer to Table 39) 0550h 000h - 00Ah DMA Channel 5 (refer to Table 39) 0560h 000h - 00Ah

USCI_A0 (refer to Table 40) 05C0h 000h - 01Fh USCI_B0 (refer to Table 41) 05E0h 000h - 01Fh USCI_A1 (refer to Table 42) 0600h 000h - 01Fh

USCI_B1 (refer to Table 43) 0620h 000h - 01Fh ADC12_A (refer to Table 44) 0700h 000h - 03Fh DAC12_A (refer to Table 45) 0780h 000h - 01Fh

Comparator_B (refer to Table 46) 08C0h 000h - 00Fh

USB configuration (refer to Table 47) 0900h 000h - 014h

USB control (refer to Table 48) 0920h 000h - 01Fh

LCD_B control (refer to Table 49) 0A00h 000h - 05Fh

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Table 15. Peripherals

(1)

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Table 16. Special Function Registers (Base Address: 0100h)

SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h

Table 17. PMM Registers (Base Address: 0120h)

PMM Control 0 PMMCTL0 00h PMM control 1 PMMCTL1 02h SVS high side control SVSMHCTL 04h SVS low side control SVSMLCTL 06h PMM interrupt flags PMMIFG 0Ch PMM interrupt enable PMMIE 0Eh

Table 18. Flash Control Registers (Base Address: 0140h)

Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h

SLAS566 –OCTOBER 2009

CRC data input CRC16DI 00h CRC result CRC16INIRES 04h

Table 20. RAM Control Registers (Base Address: 0158h)

RAM control 0 RCCTL0 00h

Table 21. Watchdog Registers (Base Address: 015Ch)

Watchdog timer control WDTCTL 00h

UCS control 0 UCSCTL0 00h UCS control 1 UCSCTL1 02h UCS control 2 UCSCTL2 04h UCS control 3 UCSCTL3 06h UCS control 4 UCSCTL4 08h UCS control 5 UCSCTL5 0Ah UCS control 6 UCSCTL6 0Ch UCS control 7 UCSCTL7 0Eh UCS control 8 UCSCTL8 10h

Table 19. CRC16 Registers (Base Address: 0150h)

Table 22. UCS Registers (Base Address: 0160h)

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System control SYSCTL 00h Bootstrap loader configuration area SYSBSLC 02h JTAG mailbox control SYSJMBC 06h JTAG mailbox input 0 SYSJMBI0 08h JTAG mailbox input 1 SYSJMBI1 0Ah JTAG mailbox output 0 SYSJMBO0 0Ch JTAG mailbox output 1 SYSJMBO1 0Eh Bus Error vector generator SYSBERRIV 18h User NMI vector generator SYSUNIV 1Ah System NMI vector generator SYSSNIV 1Ch Reset vector generator SYSRSTIV 1Eh

Table 24. Shared Reference Registers (Base Address: 01B0h)

Shared reference control REFCTL 00h

(Base Address of Port Mapping Control: 01C0h, Port P4: 01D0h)

Port mapping password register PMAPPWD 00h Port mapping control register PMAPCTL 02h Port P2.0 mapping register P2MAP0 00h Port P2.1 mapping register P2MAP1 01h Port P2.2 mapping register P2MAP2 02h Port P2.3 mapping register P2MAP3 03h Port P2.4 mapping register P2MAP4 04h Port P2.5 mapping register P2MAP5 05h Port P2.6 mapping register P2MAP6 06h Port P2.7 mapping register P2MAP7 07h

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Table 23. SYS Registers (Base Address: 0180h)

Table 25. Port Mapping Registers

Table 26. Port P1/P2 Registers (Base Address: 0200h)

Port P1 input P1IN 00h Port P1 output P1OUT 02h Port P1 direction P1DIR 04h Port P1 pullup/pulldown enable P1REN 06h Port P1 drive strength P1DS 08h Port P1 selection P1SEL 0Ah Port P1 interrupt vector word P1IV 0Eh Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h Port P2 pullup/pulldown enable P2REN 07h Port P2 drive strength P2DS 09h

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Table 26. Port P1/P2 Registers (Base Address: 0200h) (continued)

Port P2 selection P2SEL 0Bh Port P2 interrupt vector word P2IV 1Eh Port P2 interrupt edge select P2IES 19h Port P2 interrupt enable P2IE 1Bh Port P2 interrupt flag P2IFG 1Dh

Table 27. Port P3/P4 Registers (Base Address: 0220h)

Port P3 input P3IN 00h Port P3 output P3OUT 02h Port P3 direction P3DIR 04h Port P3 pullup/pulldown enable P3REN 06h Port P3 drive strength P3DS 08h Port P3 selection P3SEL 0Ah Port P3 interrupt vector word P3IV 0Eh Port P3 interrupt edge select P3IES 18h Port P3 interrupt enable P3IE 1Ah Port P3 interrupt flag P3IFG 1Ch Port P4 input P4IN 01h Port P4 output P4OUT 03h Port P4 direction P4DIR 05h Port P4 pullup/pulldown enable P4REN 07h Port P4 drive strength P4DS 09h Port P4 selection P4SEL 0Bh Port P4 interrupt vector word P4IV 1Eh Port P4 interrupt edge select P4IES 19h Port P4 interrupt enable P4IE 1Bh Port P4 interrupt flag P4IFG 1Dh

SLAS566 –OCTOBER 2009

Table 28. Port P5/P6 Registers (Base Address: 0240h)

Port P5 input P5IN 00h Port P5 output P5OUT 02h Port P5 direction P5DIR 04h Port P5 pullup/pulldown enable P5REN 06h Port P5 drive strength P5DS 08h Port P5 selection P5SEL 0Ah Port P6 input P6IN 01h Port P6 output P6OUT 03h Port P6 direction P6DIR 05h Port P6 pullup/pulldown enable P6REN 07h Port P6 drive strength P6DS 09h Port P6 selection P6SEL 0Bh

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Port P7 input P7IN 00h Port P7 output P7OUT 02h Port P7 direction P7DIR 04h Port P7 pullup/pulldown enable P7REN 06h Port P7 drive strength P7DS 08h Port P7 selection P7SEL 0Ah Port P8 input P8IN 01h Port P8 output P8OUT 03h Port P8 direction P8DIR 05h Port P8 pullup/pulldown enable P8REN 07h Port P8 drive strength P8DS 09h Port P8 selection P8SEL 0Bh

Port P9 input P9IN 00h Port P9 output P9OUT 02h Port P9 direction P9DIR 04h Port P9 pullup/pulldown enable P9REN 06h Port P9 drive strength P9DS 08h Port P9 selection P9SEL 0Ah

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Table 29. Port P7/P8 Registers (Base Address: 0260h)

Table 30. Port P9 Register (Base Address: 0280h)

Table 31. Port J Registers (Base Address: 0320h)

Port PJ input PJIN 00h Port PJ output PJOUT 02h Port PJ direction PJDIR 04h Port PJ pullup/pulldown enable PJREN 06h Port PJ drive strength PJDS 08h

Table 32. TA0 Registers (Base Address: 0340h)

TA0 control TA0CTL 00h Capture/compare control 0 TA0CCTL0 02h Capture/compare control 1 TA0CCTL1 04h Capture/compare control 2 TA0CCTL2 06h Capture/compare control 3 TA0CCTL3 08h Capture/compare control 4 TA0CCTL4 0Ah TA0 counter register TA0R 10h Capture/compare register 0 TA0CCR0 12h Capture/compare register 1 TA0CCR1 14h Capture/compare register 2 TA0CCR2 16h Capture/compare register 3 TA0CCR3 18h Capture/compare register 4 TA0CCR4 1Ah TA0 expansion register 0 TA0EX0 20h TA0 interrupt vector TA0IV 2Eh

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Table 33. TA1 Registers (Base Address: 0380h)

TA1 control TA1CTL 00h Capture/compare control 0 TA1CCTL0 02h Capture/compare control 1 TA1CCTL1 04h Capture/compare control 2 TA1CCTL2 06h TA1 counter register TA1R 10h Capture/compare register 0 TA1CCR0 12h Capture/compare register 1 TA1CCR1 14h Capture/compare register 2 TA1CCR2 16h TA1 expansion register 0 TA1EX0 20h TA1 interrupt vector TA1IV 2Eh

Table 34. TB0 Registers (Base Address: 03C0h)

TB0 control TB0CTL 00h Capture/compare control 0 TB0CCTL0 02h Capture/compare control 1 TB0CCTL1 04h Capture/compare control 2 TB0CCTL2 06h Capture/compare control 3 TB0CCTL3 08h Capture/compare control 4 TB0CCTL4 0Ah Capture/compare control 5 TB0CCTL5 0Ch Capture/compare control 6 TB0CCTL6 0Eh TB0 register TB0R 10h Capture/compare register 0 TB0CCR0 12h Capture/compare register 1 TB0CCR1 14h Capture/compare register 2 TB0CCR2 16h Capture/compare register 3 TB0CCR3 18h Capture/compare register 4 TB0CCR4 1Ah Capture/compare register 5 TB0CCR5 1Ch Capture/compare register 6 TB0CCR6 1Eh TB0 expansion register 0 TB0EX0 20h TB0 interrupt vector TB0IV 2Eh

SLAS566 –OCTOBER 2009

Table 35. TA2 Registers (Base Address: 0400h)

TA2 control TA2CTL 00h Capture/compare control 0 TA2CCTL0 02h Capture/compare control 1 TA2CCTL1 04h Capture/compare control 2 TA2CCTL2 06h TA2 counter register TA2R 10h Capture/compare register 0 TA2CCR0 12h Capture/compare register 1 TA2CCR1 14h Capture/compare register 2 TA2CCR2 16h TA2 expansion register 0 TA2EX0 20h TA2 interrupt vector TA2IV 2Eh

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Table 36. Battery Backup Registers (Base Address: 0480h)

Battery Backup Memory 0 BAKMEM0 00h Battery Backup Memory 1 BAKMEM1 02h Battery Backup Memory 2 BAKMEM2 04h Battery Backup Memory 3 BAKMEM3 06h Battery Backup Control BAKCTL 1Ch Battery Charger Control BAKCHCTL 1Eh

Table 37. Real Time Clock Registers (Base Address: 04A0h)

RTC control register 0 RTCCTL0 00h RTC control register 1 RTCCTL1 01h RTC control register 2 RTCCTL2 02h RTC control register 3 RTCCTL3 03h RTC prescaler 0 control register RTCPS0CTL 08h RTC prescaler 1 control register RTCPS1CTL 0Ah RTC prescaler 0 RTCPS0 0Ch RTC prescaler 1 RTCPS1 0Dh RTC interrupt vector word RTCIV 0Eh RTC seconds RTCSEC 10h RTC minutes RTCMIN 11h RTC hours RTCHOUR 12h RTC day of week RTCDOW 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC year low RTCYEARL 16h RTC year high RTCYEARH 17h RTC alarm minutes RTCAMIN 18h RTC alarm hours RTCAHOUR 19h RTC alarm day of week RTCADOW 1Ah RTC alarm days RTCADAY 1Bh Binary-to-BCD conversion register BIN2BCD 1Ch BCD-to-binary conversion register BCD2BIN 1Eh

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Table 38. 32-bit Hardware Multiplier Registers (Base Address: 04C0h)

16-bit operand 1 – multiply MPY 00h 16-bit operand 1 – signed multiply MPYS 02h 16-bit operand 1 – multiply accumulate MAC 04h 16-bit operand 1 – signed multiply accumulate MACS 06h 16-bit operand 2 OP2 08h 16 × 16 result low word RESLO 0Ah 16 × 16 result high word RESHI 0Ch 16 × 16 sum extension register SUMEXT 0Eh 32-bit operand 1 – multiply low word MPY32L 10h 32-bit operand 1 – multiply high word MPY32H 12h 32-bit operand 1 – signed multiply low word MPYS32L 14h 32-bit operand 1 – signed multiply high word MPYS32H 16h

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Table 38. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued)

32-bit operand 1 – multiply accumulate low word MAC32L 18h 32-bit operand 1 – multiply accumulate high word MAC32H 1Ah 32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch 32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh 32-bit operand 2 – low word OP2L 20h 32-bit operand 2 – high word OP2H 22h 32 × 32 result 0 – least significant word RES0 24h 32 × 32 result 1 RES1 26h 32 × 32 result 2 RES2 28h 32 × 32 result 3 – most significant word RES3 2Ah MPY32 control register 0 MPY32CTL0 2Ch

Table 39. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

DMA General Control: DMA module control 0 DMACTL0 00h DMA General Control: DMA module control 1 DMACTL1 02h DMA General Control: DMA module control 2 DMACTL2 04h DMA General Control: DMA module control 3 DMACTL3 06h DMA General Control: DMA module control 4 DMACTL4 08h DMA General Control: DMA interrupt vector DMAIV 0Ah DMA Channel 0 control DMA0CTL 00h DMA Channel 0 source address low DMA0SAL 02h DMA Channel 0 source address high DMA0SAH 04h DMA Channel 0 destination address low DMA0DAL 06h DMA Channel 0 destination address high DMA0DAH 08h DMA Channel 0 transfer size DMA0SZ 0Ah DMA Channel 1 control DMA1CTL 00h DMA Channel 1 source address low DMA1SAL 02h DMA Channel 1 source address high DMA1SAH 04h DMA Channel 1 destination address low DMA1DAL 06h DMA Channel 1 destination address high DMA1DAH 08h DMA Channel 1 transfer size DMA1SZ 0Ah DMA Channel 2 control DMA2CTL 00h DMA Channel 2 source address low DMA2SAL 02h DMA Channel 2 source address high DMA2SAH 04h DMA Channel 2 destination address low DMA2DAL 06h DMA Channel 2 destination address high DMA2DAH 08h DMA Channel 2 transfer size DMA2SZ 0Ah DMA Channel 3 control DMA3CTL 00h DMA Channel 3 source address low DMA3SAL 02h DMA Channel 3 source address high DMA3SAH 04h DMA Channel 3 destination address low DMA3DAL 06h DMA Channel 3 destination address high DMA3DAH 08h DMA Channel 3 transfer size DMA3SZ 0Ah DMA Channel 4 control DMA4CTL 00h

SLAS566 –OCTOBER 2009

Channel 4: 0550h, DMA Channel 5: 0560h)

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Table 39. DMA Registers (Base Address DMA General Control: 0500h,

DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA

DMA Channel 4 source address low DMA4SAL 02h DMA Channel 4 source address high DMA4SAH 04h DMA Channel 4 destination address low DMA4DAL 06h DMA Channel 4 destination address high DMA4DAH 08h DMA Channel 4 transfer size DMA4SZ 0Ah DMA Channel 5 control DMA5CTL 00h DMA Channel 5 source address low DMA5SAL 02h DMA Channel 5 source address high DMA5SAH 04h DMA Channel 5 destination address low DMA5DAL 06h DMA Channel 5 destination address high DMA5DAH 08h DMA Channel 5 transfer size DMA5SZ 0Ah

USCI control 0 UCA0CTL0 00h USCI control 1 UCA0CTL1 01h USCI baud rate 0 UCA0BR0 06h USCI baud rate 1 UCA0BR1 07h USCI modulation control UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receive buffer UCA0RXBUF 0Ch USCI transmit buffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDA transmit control UCA0IRTCTL 12h USCI IrDA receive control UCA0IRRCTL 13h USCI interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interrupt vector word UCA0IV 1Eh

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Channel 4: 0550h, DMA Channel 5: 0560h) (continued)

Table 40. USCI_A0 Registers (Base Address: 05C0h)

Table 41. USCI_B0 Registers (Base Address: 05E0h)

USCI synchronous control 0 UCB0CTL0 00h USCI synchronous control 1 UCB0CTL1 01h USCI synchronous bit rate 0 UCB0BR0 06h USCI synchronous bit rate 1 UCB0BR1 07h USCI I2C interrupt enable UCB0I2CIE 08h USCI synchronous status UCB0STAT 0Ah USCI synchronous receive buffer UCB0RXBUF 0Ch USCI synchronous transmit buffer UCB0TXBUF 0Eh USCI I2C own address UCB0I2COA 10h USCI I2C slave address UCB0I2CSA 12h USCI interrupt enable UCB0IE 1Ch USCI interrupt flags UCB0IFG 1Dh USCI interrupt vector word UCB0IV 1Eh

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Table 42. USCI_A1 Registers (Base Address: 0600h)

USCI control 0 UCA1CTL0 00h USCI control 1 UCA1CTL1 01h USCI baud rate 0 UCA1BR0 06h USCI baud rate 1 UCA1BR1 07h USCI modulation control UCA1MCTL 08h USCI status UCA1STAT 0Ah USCI receive buffer UCA1RXBUF 0Ch USCI transmit buffer UCA1TXBUF 0Eh USCI LIN control UCA1ABCTL 10h USCI IrDA transmit control UCA1IRTCTL 12h USCI IrDA receive control UCA1IRRCTL 13h USCI interrupt enable UCA1IE 1Ch USCI interrupt flags UCA1IFG 1Dh USCI interrupt vector word UCA1IV 1Eh

Table 43. USCI_B1 Registers (Base Address: 0620h)

USCI synchronous control 0 UCB1CTL0 00h USCI synchronous control 1 UCB1CTL1 01h USCI synchronous bit rate 0 UCB1BR0 06h USCI synchronous bit rate 1 UCB1BR1 07h USCI I2C interrupt enable UCB1I2CIE 08h USCI synchronous status UCB1STAT 0Ah USCI synchronous receive buffer UCB1RXBUF 0Ch USCI synchronous transmit buffer UCB1TXBUF 0Eh USCI I2C own address UCB1I2COA 10h USCI I2C slave address UCB1I2CSA 12h USCI interrupt enable UCB1IE 1Ch USCI interrupt flags UCB1IFG 1Dh USCI interrupt vector word UCB1IV 1Eh

SLAS566 –OCTOBER 2009

Table 44. ADC12_A Registers (Base Address: 0700h)

Control register 0 ADC12CTL0 00h Control register 1 ADC12CTL1 02h Control register 2 ADC12CTL2 04h Interrupt-flag register ADC12IFG 0Ah Interrupt-enable register ADC12IE 0Ch Interrupt-vector-word register ADC12IV 0Eh ADC memory-control register 0 ADC12MCTL0 10h ADC memory-control register 1 ADC12MCTL1 11h ADC memory-control register 2 ADC12MCTL2 12h ADC memory-control register 3 ADC12MCTL3 13h ADC memory-control register 4 ADC12MCTL4 14h ADC memory-control register 5 ADC12MCTL5 15h ADC memory-control register 6 ADC12MCTL6 16h ADC memory-control register 7 ADC12MCTL7 17h

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Table 44. ADC12_A Registers (Base Address: 0700h) (continued)

ADC memory-control register 8 ADC12MCTL8 18h ADC memory-control register 9 ADC12MCTL9 19h ADC memory-control register 10 ADC12MCTL10 1Ah ADC memory-control register 11 ADC12MCTL11 1Bh ADC memory-control register 12 ADC12MCTL12 1Ch ADC memory-control register 13 ADC12MCTL13 1Dh ADC memory-control register 14 ADC12MCTL14 1Eh ADC memory-control register 15 ADC12MCTL15 1Fh Conversion memory 0 ADC12MEM0 20h Conversion memory 1 ADC12MEM1 22h Conversion memory 2 ADC12MEM2 24h Conversion memory 3 ADC12MEM3 26h Conversion memory 4 ADC12MEM4 28h Conversion memory 5 ADC12MEM5 2Ah Conversion memory 6 ADC12MEM6 2Ch Conversion memory 7 ADC12MEM7 2Eh Conversion memory 8 ADC12MEM8 30h Conversion memory 9 ADC12MEM9 32h Conversion memory 10 ADC12MEM10 34h Conversion memory 11 ADC12MEM11 36h Conversion memory 12 ADC12MEM12 38h Conversion memory 13 ADC12MEM13 3Ah Conversion memory 14 ADC12MEM14 3Ch Conversion memory 15 ADC12MEM15 3Eh

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Table 45. DAC12_A Registers (Base Address: 0780h)

DAC12_A channel 0 control register 0 DAC12_0CTL0 00h DAC12_A channel 0 control register 1 DAC12_0CTL1 02h DAC12_A channel 0 data register DAC12_0DAT 04h DAC12_A channel 0 calibration control register DAC12_0CALCTL 06h DAC12_A channel 0 calibration data register DAC12_0CALDAT 08h DAC12_A channel 1 control register 0 DAC12_1CTL0 10h DAC12_A channel 1 control register 1 DAC12_1CTL1 12h DAC12_A channel 1 data register DAC12_1DAT 14h DAC12_A channel 1 calibration control register DAC12_1CALCTL 16h DAC12_A channel 1 calibration data register DAC12_1CALDAT 18h DAC12_A interrupt vector word DAC12IV 1Eh

Table 46. Comparator_B Registers (Base Address: 08C0h)

Comp_B control register 0 CBCTL0 00h Comp_B control register 1 CBCTL1 02h Comp_B control register 2 CBCTL2 04h Comp_B control register 3 CBCTL3 06h Comp_B interrupt register CBINT 0Ch Comp_B interrupt vector word CBIV 0Eh

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Table 47. USB Configuration Registers (Base Address: 0900h)

USB key/ID USBKEYID 00h USB module configuration USBCNF 02h USB PHY control USBPHYCTL 04h USB power control USBPWRCTL 08h USB power voltage setting USBPWRVSR 0Ah USB PLL control USBPLLCTL 10h USB PLL divider USBPLLDIV 12h USB PLL interrupts USBPLLIR 14h

Table 48. USB Control Registers (Base Address: 0920h)

Input endpoint#0 configuration IEPCNF_0 00h Input endpoint #0 byte count IEPCNT_0 01h Output endpoint#0 configuration OEPCNF_0 02h Output endpoint #0 byte count OEPCNT_0 03h Input endpoint interrupt enables IEPIE 0Eh Output endpoint interrupt enables OEPIE 0Fh Input endpoint interrupt flags IEPIFG 10h Output endpoint interrupt flags OEPIFG 11h USB interrupt vector USBIV 12h USB maintenance MAINT 16h Time stamp TSREG 18h USB frame number USBFN 1Ah USB control USBCTL 1Ch USB interrupt enables USBIE 1Dh USB interrupt flags USBIFG 1Eh Function address FUNADR 1Fh

SLAS566 –OCTOBER 2009

LCD_B control register 0 LCDBCTL0 000h LCD_B control register 1 LCDBCTL1 002h LCD_B blinking control register LCDBBLKCTL 004h LCD_B memory control register LCDBMEMCTL 006h LCD_B voltage control register LCDBVCTL 008h LCD_B port control register 0 LCDBPCTL0 00Ah LCD_B port control register 1 LCDBPCTL1 00Ch LCD_B port control register 2 LCDBPCTL2 00Eh LCD_B charge pump control register LCDBCTL0 012h LCD_B interrupt vector word LCDBIV 01Eh LCD_B memory 1 LCDM1 020h LCD_B memory 2 LCDM2 021h ... LCD_B memory 22 LCDM22 035h LCD_B blinking memory 1 LCDBM1 040h LCD_B blinking memory 2 LCDBM2 041h ...

Table 49. LCD_B Registers (Base Address: 0A00h)

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Table 49. LCD_B Registers (Base Address: 0A00h) (continued)

LCD_B blinking memory 22 LCDBM22 055h

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Specifications and Main Features

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