Texas Instruments MSP430FG4618, MSP430FG4617, MSP430FG4619, MSP430CG4618, MSP430FG4616 User Manual

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MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

• Low Supply-Voltage Range: 1.8 V to 3.6 V • Universal Serial Communication Interface

• Ultra-Low Power Consumption – Enhanced UART Supports Automatic Baud– Active Mode: 400 µA at 1 MHz, 2.2 V – Standby Mode: 1.3 µA – Off Mode (RAM Retention): 0.22 µA

• Five Power-Saving Modes

• Wakeup From Standby Mode in Less Than 6 µs

• 16-Bit RISC Architecture, Extended Memory, 125‑ns Instruction Cycle Time

• Three-Channel Internal DMA

• 12-Bit Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold and Autoscan Feature • Section 3 Summarizes the Available Family

• Three Configurable Operational Amplifiers

• Dual 12-Bit Digital-to-Analog Converters (DACs) With Synchronization

• 16-Bit Timer_A With Three Capture/Compare Registers

• 16-Bit Timer_B With Seven Capture/CompareWith-Shadow Registers

• On-Chip Comparator

• Supply Voltage Supervisor and Monitor With Programmable Level Detection

• Serial Communication Interface (USART1), Select Asynchronous UART or Synchronous SPI by Software

Rate Detection – IrDA Encoder and Decoder – Synchronous SPI – I2C

• Serial Onboard Programming, Programmable Code Protection by Security Fuse

• Brownout Detector

• Basic Timer With Real-Time Clock (RTC) Feature

• Integrated LCD Driver up to 160 Segments With Regulated Charge Pump

Members – MSP430FG4616, MSP430FG4616

92KB+256B of Flash or ROM 4KB of RAM

– MSP430FG4617, MSP430CG4617

92KB+256B of Flash or ROM 8KB of RAM

– MSP430FG4618, MSP430CG4618

116KB+256B of Flash or ROM 8KB of RAM

– MSP430FG4619, MSP430CG4619

120KB+256B of Flash or ROM 4KB of RAM

• For Complete Module Descriptions, see the MSP430x4xx Family User’s Guide (SLAU056)

1.2 Applications

• Portable Medical Applications • E-Meter Applications

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in less than 6 µs.

The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal serial communication interface (USCI), one universal synchronous/asynchronous communication interface (USART), DMA, 80 I/O pins, and a segment liquid crystal display (LCD) driver with regulated charge pump.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Oscillators

FLL+

RAM

4KB 8KB 8KB 4KB

Brownout

Protection

SVS/SVM

RST/NMI

DVCC 1/2 DVSS1 /2

MCLK

Watchdog

WDT+

15/16- Bit

Timer_ A3

3 CC

Registers

8MHz

CPUX

incl. 16

Registers

XOUT/ XT2 OUT

OA0, OA 1,

OA2

3 Op Amps

Basic Timer

and

Real-Time

Clock

JTAG

Interface

LCD_A

160

Segments

1,2,3 ,4 Mux

Ports

P1/P2

2x8 I/O

Interrupt

capability

USCI_A 0:

UART,

IrDA, SPI

USCI_B 0:

SPI, I2 C

Comparator

Flash (FG) ROM (CG)

120KB 116KB

92KB 92KB

Hardware

Multiplier

MPY,

MPYS,

MAC,

MACS

Timer_B 7

7 CC

Registers,

Shadow

Reg

ADC12

12-Bit

Channels

DAC12

12-Bit

2 Channels Voltage out

USART 1

UART , SPI

DMA

Controller

3 Channels

Ports P3/P4 P5/P6

4x8 I/O

Ports

P7/P8

P9/P10

4x8, 2x16 I/O

AVCC AVSS P1.x/P2 .x

2x 8

P3.x/P4 .x P5.x/P6 .x

4x 8

P7.x/P8. x

P9.x/P10.x

4x 8/2x16

XIN /

XT2 IN

SMCLK

ACLK

MDB

MAB

Enhanced

Emulation

(FG only)

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

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PART NUMBER PACKAGE BODY SIZE

MSP430FG4619IPZ LQFP (100) 14 mm × 14 mm MSP430FG4619IZQW MicroStar Junior™ BGA (113) 7 mm × 7 mm

(1) For the most current part, package, and ordering information for all available devices, see the Package

Option Addendum in Section 8, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 8.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

Device Information

(1)

(2)

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Figure 1-1. Functional Block Diagram

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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table of Contents

1 Device Overview ......................................... 1 5.30 12-Bit ADC, Timing Parameters .................... 37

1.1 Features .............................................. 1 5.31 12-Bit ADC, Linearity Parameters................... 37

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram............................ 2

2 Revision History ......................................... 4

3 Device Comparison ..................................... 5

4 Terminal Configuration and Functions.............. 6

4.1 Pin Diagrams ......................................... 6

4.2 Signal Descriptions................................... 8

5 Specifications........................................... 14

5.1 Absolute Maximum Ratings ........................ 14

5.2 ESD Ratings ........................................ 14

5.3 Recommended Operating Conditions............... 14

5.4 Supply Current Into AVCC+ DVCCExcluding

External Current .................................... 16

5.5 Thermal Characteristics............................. 17

5.6 Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI,

JTAG (TCK, TMS, TDI/TCLK,TDO/TDI) ............ 18

5.7 Inputs Px.x, TAx, TBX............................... 18

5.8 Leakage Current – Ports P1 to P10 ................ 18

5.9 Outputs – Ports P1 to P10 .......................... 18

5.10 Output Frequency................................... 19

5.11 Typical Characteristics – Outputs................... 20

5.12 Wake-up Timing From LPM3 ....................... 21

5.13 RAM................................................. 21

5.14 LCD_A............................................... 21

5.15 Comparator_A ...................................... 22

5.16 Typical Characteristics – Comparator_A............ 23

5.17 POR, BOR .......................................... 24

5.18 SVS (Supply Voltage Supervisor and Monitor) ..... 25

5.19 DCO................................................. 27

5.20 Crystal Oscillator, LFXT1 Oscillator ................ 29

5.21 Crystal Oscillator, XT2 Oscillator ................... 29

5.22 USCI (UART Mode)................................. 29

5.23 USCI (SPI Master Mode)............................ 30

5.24 USCI (SPI Slave Mode)............................. 30

5.25 USCI (I

5.26 USART1............................................. 33

5.27 12-Bit ADC, Power Supply and Input Range

5.28 12-Bit ADC, External Reference ................... 34

5.29 12-Bit ADC, Built-In Reference...................... 35

C Mode).................................... 33

Conditions .......................................... 34

5.32 12-Bit ADC, Temperature Sensor and Built-In V

MID

...................................................... 38

5.33 12-Bit DAC, Supply Specifications.................. 38

5.34 12-Bit DAC, Linearity Specifications ................ 39

5.35 12-Bit DAC, Output Specifications .................. 41

5.36 12-Bit DAC, Reference Input Specifications........ 41

5.37 12-Bit DAC, Dynamic Specifications................ 42

5.38 12-Bit DAC, Dynamic Specifications Continued .... 43

5.39 Operational Amplifier OA, Supply Specifications ... 44

5.40 Operational Amplifier OA, Input/Output

Specifications........................................ 44

5.41 Operational Amplifier OA, Dynamic Specifications . 45

5.42 Operational Amplifier OA, Typical Characteristics.. 45

5.43 Operational Amplifier OA Feedback Network,

Noninverting Amplifier Mode (OAFCx = 4).......... 46

5.44 Operational Amplifier OA Feedback Network,

Inverting Amplifier Mode (OAFCx = 6).............. 46

5.45 Flash Memory (FG461x Devices Only) ............. 47

5.46 JTAG Interface...................................... 47

5.47 JTAG Fuse ......................................... 47

6 Detailed Description................................... 48

6.1 CPU ................................................. 48

6.2 Instruction Set....................................... 49

6.3 Operating Modes.................................... 50

6.4 Interrupt Vector Addresses.......................... 51

6.5 Special Function Registers (SFRs) ................. 52

6.6 Memory Organization ............................... 54

6.7 Bootstrap Loader (BSL)............................. 55

6.8 Flash Memory....................................... 55

6.9 Peripherals .......................................... 55

6.10 Input/Output Schematics ............................ 65

7 Device and Documentation Support.............. 100

7.1 Device Support..................................... 100

7.2 Documentation Support............................ 103

7.3 Related Links ...................................... 103

7.4 Community Resources............................. 104

7.5 Trademarks ........................................ 104

7.6 Electrostatic Discharge Caution ................... 104

7.7 Export Control Notice.............................. 104

7.8 Glossary............................................ 104

8 Mechanical, Packaging, and Orderable

Information............................................. 105

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SLAS508J –APRIL 2006–REVISED JUNE 2015

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from March 2, 2011 to June 19, 2015 Page

• Document format and organization changes throughout, including the addition of section numbering ................... 1

• Added Device Information table .................................................................................................... 2

• Moved functional block diagram to Section 1.4................................................................................... 2

• Added Section 3, Device Comparison............................................................................................. 5

• Added signal names to ZQW pinout figure........................................................................................ 7

• Changed table note that starts "Segments S0 through S3 are disabled when..."............................................ 8

• Added row for unassigned ball locations on ZQW package................................................................... 13

• Added Section 5 and moved all electrical specifications to it ................................................................. 14

• Added Section 5.2, ESD Ratings.................................................................................................. 14

• In Recommended Operating Conditions, added test conditions for TYP values ........................................... 14

• Added Section 5.5, Thermal Characteristics .................................................................................... 17

• Changed table note that starts "Segments S0 through S3 are disabled when..." .......................................... 21

• Changed the value of DAC12_xDAT from 7F7h to F7Fh in Figure 5-33 .................................................... 43

• Added Table 6-19 and moved P4.6 and P4.7 from Table 6-18 to insert correct LCDS32 control bit name ............ 75

• Added Table 6-29 and moved P7.2 and P7.3 from Table 6-28 to insert correct LCDS28 control bit name ............ 88

• Added Table 6-31 and moved P7.6 and P7.7 from Table 6-30 to insert correct LCDS24 control bit name ............ 89

• Added Table 6-33 and moved P8.2 to P8.5 from Table 6-32 to insert correct LCDS20 control bit name............... 90

• Added Table 6-36 and moved P9.2 to P9.5 from Table 6-35 to insert correct LCDS12 control bit name............... 92

• Corrected LCD segment numbers in PIN NAME column of Table 6-36..................................................... 92

• Added Table 6-37 and moved P9.6 and P9.7 from Table 6-35 to insert correct LCDS8 control bit name.............. 93

• Corrected LCD segment numbers in PIN NAME column of Table 6-37..................................................... 93

• Corrected LCD segment numbers in PIN NAME and FUNCTION columns of Table 6-38................................ 94

• Added Table 6-39 and moved P10.2 to P10.5 from Table 6-38 to insert correct LCDS4 control bit name ............. 94

• Added Section 7 and moved Trademarks and ESD Caution sections to it ................................................ 100

• Added Section 8 ................................................................................................................... 105

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SLAS508J –APRIL 2006–REVISED JUNE 2015

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1. Device Comparison

(1)(2)

FLASH ROM RAM ADC12 DAC12 COMP_A

DEVICE EEM Timer_A Timer_B OP AMP USART USCI I/O PACKAGE

(KB) (KB) (KB) (Channels) (Channels) (Channels)

PZ 100

MSP430FG4619 120 – 4 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430FG4618 116 – 8 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430FG4617 92 – 8 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430FG4616 92 – 4 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4619 – 120 4 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4618 – 116 8 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4617 – 92 8 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4616 – 92 4 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

(1) For the most currentdevice, package,and ordering information for all available devices, see thePackage Option Addendum in Section 8, orsee theTI website at www.ti.com. (2) Package drawings, thermal data,and symbolizationare available at www.ti.com/packaging.

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MSP430CG4618 MSP430CG4617 MSP430CG4616

10 0

P1 .7 /C A1

P6 .1 /A 1/ OA 0 O

P6 .0 /A 0/ OA 0 I0

RS T /N M I

XT 2 IN

XT 2 OU T

P1 .3 /T BO U T H/ SV S O UT

P1 .4 /T BC L K/SMC L K

P1 .5 /TA CLK /A CLK

P1 .6 /C A0

P2 .3 /T B2

P9 ,2 /S 15

P9 .1 /S 16

P9 .0 /S 17

P8 .5 /S 20

P8 .0 /S 25

P7 .7 /S 26

P7 .6 /S 27

P7 .5 /S 28

P7 .4 /S 29

P4 .7 /U C A0 R XD /S3 4

P7 .3 /U C A0 C LK /S 3 0

P1 .0 /TA 0

TD I/ TC L K

TD O /T DI

P8 .4 /S 21

SS 1

P6 .2 /A 2/ OA 0 I1

P1 .2 /TA 1

P8 .1 /S 24

P4 .6 /U C A0 TXD /S 3 5

DVCC1

P6.3/A3/OA1O

P6.4/A4/OA1I0

P6.5/A5/OA2O

P6.6/A6/DAC0/OA2I0

P6.7/A7/DAC1/SVSIN

VREF+

XIN

XOUT

VeREF+/DAC0

VREF-/VeREF-

P5.1/S0/A12/DAC1

P5.0/S1/A13/OA1I1

P10.7/S2/A14/OA2I1

P10.6/S3/A15

P10.5/S4

P10.4/S5

P10.3/S6

P10.2/S7

P10.1/S8

P10.0/S9

P9.7/S10

P9.6/S11

P9.5/S12

P9.4/S13

P2.4/UCA0TXD

P2.5/UCA0RXD

P2.6/CAOUT

P2.7/ADC12CLK/DMAE0

P3.0/UCB0STE

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK

P3.4/TB3

P3.5/TB4

P3.6/TB5

P3.7/TB6

P4.0/UTXD1

P4.1/URXD1

DVSS2

DVCC2

LCDCAP/R33

P5.7/R23

P5.6/LCDREF/R13

P5.5/R03

P5.4/COM3

P5.3/COM2

P5.2/COM1

COM0

P4.2/STE1/S39

P8 .6 /S 19

P8 .3 /S 22

P8 .2 /S 23

P7 .0 /U C A0 S TE /S 3 3

P4 .5 /U C LK 1/S36

P4 .4 /S OMI 1/S3 7

P4 .3 /S IM O 1/S3 8

CCAVSS

TC K

TM S

P1 .1 /TA 0/MC L K

P2 .0 /TA 2

P2 .1 /T B0

P2 .2 /T B1

P9.3/S14

P8.7/S18

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 100-pin PZ package.

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Figure 4-1. 100-Pin PZ Package (Top View)

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1 2 3 4 5 6 7 8 9 10 11 12

CC1

P6.3

P6.6

XIN

XOUT

P5.1

P10.6

P10.3

P10.0

P9.5

P9.4

N/A

P6.4

P6.5

REF+

P5.0

P10.5

P10.2

P9.7

P9.2

N/A

P9.3

SS1

P6.7

P9.1

P9.0

P6.0

P6.2

N/A

REF–

P10.4

P9.6

P8.7

N/A

P8.6

P8.5

TCK

RST

P6.1

P10.7

P10.1

P8.4

P8.1

P8.0

P8.3

P8.2

TDO

XT2IN

TDI

TMS

P7.3

P7.5

P7.6

P7.7

P1.0

XT2OUT

P1.2

P1.1

P4.4

P4.7

P7.2

P7.4

P1.3

P1.4

P2.1

P2.2

N/A

P5.3

P7.0

P7.1

P1.6

P1.5

N/A

P2.7

P3.2

P3.5

P4.0

N/A

P4.5

P4.6

P2.0

P1.7

COM0

P4.3

P2.3

N/A

P2.5

P3.0

P3.3

P3.6

P4.1

LCDCAP

P5.7

P5.5

N/A

P4.2

N/A

P2.4

P2.6

P3.1

P3.4

P3.7

SS2

CC2

P5.6

P5.4

P5.2

N/A

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Figure 4-2 shows the pinout for the 113-pin ZQW package. This figure shows only the default pin

assignments; for all pin assignments, see Table 4-1.

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

supply. The shortest ground return path to the device should be established to ball location B3, DV

N/A = Not Assigned. All unassigned ball locations on the ZQW package should be electrically tied to the ground

Figure 4-2. 113-Pin ZQW Package (Top View)

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SS1

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SLAS508J –APRIL 2006–REVISED JUNE 2015

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1. Signal Descriptions

SIGNAL NAME I/O DESCRIPTION

CC1

P6.3 General-purpose digital I/O A3 2 B1 I/O Analog input A3 for 12-bit ADC OA1O OA1 output P6.4 General-purpose digital I/O A4 3 B2 I/O Analog input A4 for 12-bit ADC OA1I0 OA1 input multiplexer on + terminal and – terminal P6.5 General-purpose digital I/O A5 4 C2 I/O Analog input A5 for 12-bit ADC OA2O OA2 output P6.6 General-purpose digital I/O A6 Analog input A6 for 12-bit ADC DAC0 DAC12.0 output OA2I0 OA2 input multiplexer on + terminal and – terminal P6.7 General-purpose digital I/O A7 Analog input A7 for 12-bit ADC DAC1 DAC12.1 output SVSIN Analog input to brownout, supply voltage supervisor V

REF+

XIN 8 D1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 E1 O Output terminal of crystal oscillator XT1 Ve

REF+

DAC0 DAC12.0 output V

REF

REF–

P5.1 General-purpose digital I/O

(1)

S0 A12 Analog input A12 for 12-bit ADC DAC1 DAC12.1 output P5.0 General-purpose digital I/O

(1)

S1 A13 Analog input A13 for 12-bit ADC OA1I1 OA1 input multiplexer on + terminal and – terminal P10.7 General-purpose digital I/O

(1)

S2 A14 Analog input A14 for 12-bit ADC OA2I1 OA2 input multiplexer on + terminal and – terminal P10.6 General-purpose digital I/O

(1)

S3 A15 Analog input A15 to 12-bit ADC

PIN NO.

PZ ZQW

1 A1 Digital supply voltage, positive terminal

5 C1 I/O

6 C3 I/O

7 D2 O Output of positive terminal of the reference voltage in the ADC

10 E2 I/O

11 E4 I

12 F1 I/O

13 F2 I/O

14 E5 I/O

Input for an external reference voltage to the ADC

Internal reference voltage, negative terminal for the ADC reference voltage External applied reference voltage, negative terminal for the ADC reference voltage

LCD segment output 0

LCD segment output 1

LCD segment output 2

15 G1 I/O LCD segment output 3

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(1) Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and, therefore, cannot be used

together with the LCD charge pump. On the MSP430xG461x devices only, S0 through S3 are also disabled if VLCDEXT = 1. This setting is typically used to apply an external LCD voltage supply to the LCDCAP terminal. For these devices, set LCDCPEN = 0, VLCDEXT = 0, and VLCDx > 0 to enable an external LCD voltage supply to be applied to the LCDCAP terminal.

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Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P10.5 General-purpose digital I/O S4 LCD segment output 4 P10.4 General-purpose digital I/O S5 LCD segment output 5 P10.3 General-purpose digital I/O S6 LCD segment output 6 P10.2 General-purpose digital I/O S7 LCD segment output 7 P10.1 General-purpose digital I/O S8 LCD segment output 8 P10.0 General-purpose digital I/O S9 LCD segment output 9 P9.7 General-purpose digital I/O S10 LCD segment output 10 P9.6 General-purpose digital I/O S11 LCD segment output 11 P9.5 General-purpose digital I/O S12 LCD segment output 12 P9.4 General-purpose digital I/O S13 LCD segment output 13 P9.3 General-purpose digital I/O S14 LCD segment output 14 P9.2 General-purpose digital I/O S15 LCD segment output 15 P9.1 General-purpose digital I/O S16 LCD segment output 16 P9.0 General-purpose digital I/O S17 LCD segment output 17 P8.7 General-purpose digital I/O S18 LCD segment output 18 P8.6 General-purpose digital I/O S19 LCD segment output 19 P8.5 General-purpose digital I/O S20 LCD segment output 20 P8.4 General-purpose digital I/O S21 LCD segment output 21 P8.3 General-purpose digital I/O S22 LCD segment output 22 P8.2 General-purpose digital I/O S23 LCD segment output 23 P8.1 General-purpose digital I/O S24 LCD segment output 24 P8.0 General-purpose digital I/O S25 LCD segment output 25 P7.7 General-purpose digital I/O S26 LCD segment output 26

PIN NO.

PZ ZQW

16 G2 I/O

17 F4 I/O

18 H1 I/O

19 H2 I/O

20 F5 I/O

21 J1 I/O

22 J2 I/O

23 G4 I/O

24 K1 I/O

25 L1 I/O

26 M2 I/O

27 K2 I/O

28 L3 I/O

29 M3 I/O

30 H4 I/O

31 L4 I/O

32 M4 I/O

33 G5 I/O

34 L5 I/O

35 M5 I/O

36 H5 I/O

37 J5 I/O

38 M6 I/O

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Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P7.6 General-purpose digital I/O S27 LCD segment output 27 P7.5 General-purpose digital I/O S28 LCD segment output 28 P7.4 General-purpose digital I/O S29 LCD segment output 29 P7.3 General-purpose digital I/O UCA0CLK External clock input – USCI_A0 in UART or SPI mode,

S30 LCD segment 30 P7.2 General-purpose digital I/O UCA0SOMI 43 L7 I/O Slave out/master in of USCI_A0 in SPI mode S31 LCD segment output 31 P7.1 General-purpose digital I/O UCA0SIMO 44 M8 I/O Slave in/master out of USCI_A0 in SPI mode S32 LCD segment output 32 P7.0 General-purpose digital I/O UCA0STE 45 L8 I/O Slave transmit enable – USCI_A0 in SPI mode S33 LCD segment output 33 P4.7 General-purpose digital I/O UCA0RXD 46 J7 I/O Receive data in – USCI_A0 in UART or IrDA mode S34 LCD segment output 34 P4.6 General-purpose digital I/O UCA0TXD 47 M9 I/O Transmit data out – USCI_A0 in UART or IrDA mode S35 LCD segment output 35 P4.5 General-purpose digital I/O UCLK1 External clock input – USART1 in UART or SPI mode,

S36 LCD segment output 36 P4.4 General-purpose digital I/O SOMI1 49 H7 I/O Slave out/master in of USART1 in SPI mode S37 LCD segment output 37 P4.3 General-purpose digital I/O SIMO1 50 M10 I/O Slave in/master out of USART1 in SPI mode S38 LCD segment output 38 P4.2 General-purpose digital I/O STE1 51 M11 I/O Slave transmit enable – USART1 in SPI mode S39 LCD segment output 39 COM0 52 L10 O Common output, COM0 for LCD backplanes P5.2 General-purpose digital I/O COM1 Common output, COM1 for LCD backplanes P5.3 General-purpose digital I/O COM2 Common output, COM2 for LCD backplanes P5.4 General-purpose digital I/O COM3 Common output, COM3 for LCD backplanes P5.5 General-purpose digital I/O R03 Input port of lowest analog LCD level (V5)

PIN NO.

PZ ZQW

39 L6 I/O

40 J6 I/O

41 M7 I/O

42 H6 I/O

48 L9 I/O

53 L12 I/O

54 J8 I/O

55 K12 I/O

56 K11 I/O

Clock output – USCI_A0 in SPI mode

Clock output – USART1 in SPI MODE

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P5.6 General-purpose digital I/O LCDREF 57 J12 I/O External reference voltage input for regulated LCD voltage R13 Input port of third most positive analog LCD level (V4 or V3) P5.7 General-purpose digital I/O R23 Input port of second most positive analog LCD level (V2) LCDCAP LCD capacitor connection R33 Input/output port of most positive analog LCD level (V1) DV

CC2

SS2

P4.1 General-purpose digital I/O URXD1 Receive data in – USART1 in UART mode P4.0 General-purpose digital I/O UTXD1 Transmit data out – USART1 in UART mode P3.7 General-purpose digital I/O TB6 Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6 output P3.6 General-purpose digital I/O TB5 Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5 output P3.5 General-purpose digital I/O TB4 Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4 output P3.4 General-purpose digital I/O TB3 Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output P3.3 General-purpose digital I/O UCB0CLK External clock input – USCI_B0 in UART or SPI mode,

P3.2 General-purpose digital I/O UCB0SOMI 69 F9 I/O Slave out/master in of USCI_B0 in SPI mode UCB0SCL I2C clock – USCI_B0 in I2C mode P3.1 General-purpose digital I/O UCB0SIMO 70 D12 I/O Slave in/master out of USCI_B0 in SPI mode UCB0SDA I2C data – USCI_B0 in I2C mode P3.0 General-purpose digital I/O UCB0STE Slave transmit enable – USCI_B0 in SPI mode P2.7 General-purpose digital I/O ADC12CLK 72 E9 I/O Conversion clock for 12-bit ADC DMAE0 DMA channel 0 external trigger P2.6 General-purpose digital I/O CAOUT Comparator_A output P2.5 General-purpose digital I/O UCA0RXD Receive data in – USCI_A0 in UART or IrDA mode P2.4 General-purpose digital I/O UCA0TXD Transmit data out – USCI_A0 in UART or IrDA mode P2.3 General-purpose digital I/O TB2 Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2 General-purpose digital I/O TB1 Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output P2.1 General-purpose digital I/O TB0 Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output

PIN NO.

PZ ZQW

58 J11 I/O

59 H11 I

60 H12 Digital supply voltage, positive terminal 61 G12 Digital supply voltage, negative terminal

62 G11 I/O

63 H9 I/O

64 F12 I/O

65 F11 I/O

66 G9 I/O

67 E12 I/O

68 E11 I/O

Clock output – USCI_B0 in SPI mode

71 D11 I/O

73 C12 I/O

74 C11 I/O

75 B12 I/O

76 A11 I/O

77 E8 I/O

78 D8 I/O

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Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P2.0 General-purpose digital I/O TA2 Timer_A Capture: CCI2A input, compare: Out2 output P1.7 General-purpose digital I/O CA1 Comparator_A input P1.6 General-purpose digital I/O CA0 Comparator_A input P1.5 General-purpose digital I/O TACLK 82 B9 I/O Timer_A, clock signal TACLK input ACLK ACLK output (divided by 1, 2, 4, or 8) P1.4 General-purpose digital I/O TBCLK 83 B8 I/O Input clock TBCLK – Timer_B7 SMCLK Submain system clock SMCLK output P1.3 General-purpose digital I/O TBOUTH 84 A8 I/O Switch all PWM digital output ports to high impedance – Timer_B7 TB0 to TB6 SVSOUT SVS: output of SVS comparator P1.2 General-purpose digital I/O TA1 Timer_A, Capture: CCI1A input, compare: Out1 output P1.1 General-purpose digital I/O TA0 86 E7 I/O Timer_A. Capture: CCI0B input. Note: TA0 is only an input on this pin. BSL receive. MCLK MCLK output P1.0 General-purpose digital I/O TA0 Timer_A. Capture: CCI0A input, compare: Out0 output. BSL transmit. XT2OUT 88 B7 O Output terminal of crystal oscillator XT2 XT2IN 89 B6 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO Test data output port. TDO/TDI data output. TDI Programming data input terminal TDI Test data input TCLK Test clock input. The device protection fuse is connected to TDI/TCLK. TMS 92 E6 I Test mode select. TMS is used as an input port for device programming and test. TCK 93 A5 I Test clock. TCK is the clock input port for device programming and test. RST Reset input NMI Nonmaskable interrupt input port P6.0 General-purpose digital I/O A0 95 A4 I/O Analog input A0 for 12-bit ADC OA0I0 OA0 input multiplexer on + terminal and – terminal P6.1 General-purpose digital I/O A1 96 D5 I/O Analog input A1 for 12-bit ADC OA0O OA0 output P6.2 General-purpose digital I/O A2 97 B4 I/O Analog input A2 for 12-bit ADC OA0I1 OA0 input multiplexer on + terminal and – terminal

AVSS 98 A3 DV

SS1

PIN NO.

PZ ZQW

79 A10 I/O

80 B10 I/O

81 A9 I/O

85 D7 I/O

87 A7 I/O

90 A6 I/O

91 D6 I

94 B5 I

Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, Comparator_A, port 1

99 B3 Digital supply voltage, negative terminal

100 A2

Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, Comparator_A, port 1. Do not power up before powering DV

CC1

and DV

CC2

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

Not Assigned – G8, H8, – supply. The shortest ground return path to the device should be established to ball location

PIN NO.

PZ ZQW

A12,

B11, D4,

D9, F8, All unassigned ball locations on the ZQW package should be electrically tied to the ground

J4, J9, B3, DV

L2, L11,

M1, M12

SS1

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5 Specifications

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5.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at VCCto V Voltage applied to any pin

(2)

–0.3 4.1 V –0.3 VCC+ 0.3 V

Diode current at any device terminal ±2 mA

Storage temperature, T

stg

Unprogrammed device –55 105 Programmed device –40 85

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are referenced to VSS.The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TDI/TCLK pin when blowing the JTAG fuse.

5.2 ESD Ratings

VALUE UNIT

Electrostatic discharge V

(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1)

(2)

±1000

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)

MIN NOM MAX UNIT

During program execution (AVCC= DV

Supply voltage 2.7 3.6 V

During flash memory programming (FG461x) (AVCC= DV

CC1/2

= VCC)

During program execution, SVS enabled and PORON = 1 (AVCC= DV

Supply voltage (AVSS= DV

= VSS) 0 0 V

SS1/2

Operating free-air temperature range –40 85 °C

CC1/2

= VCC)

LF selected, XTS_FLL = 0

(LFXT1)

Crystal frequency

(3)

XT1 selected, XTS_FLL = 1 Ceramic resonator 450 8000 kHz XT1 selected, XTS_FLL = 1 Crystal 1000 8000

(XT2)

(System)

Crystal frequency kHz

Processor frequency (signal MCLK) VCC= 2.0 V DC 4.6 MHz

(1) TI recommends powering AVCCand DVCCfrom the same source. A maximum difference of 0.3 V between AVCCand DVCCcan be

tolerated during power up and operation.

(2) The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply

voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry.

(3) In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

(1)

(2)

(3)

Watch crystal 32.768

(1)

1.8 3.6

2 3.6

Ceramic resonator 450 8000 Crystal 1000 8000 VCC= 1.8 V DC 3

VCC= 3.6 V DC 8

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1.8 3.62.7 3

3.0 MHz

8.0 MHz

Supply Voltage (V)

Supply voltage range, MSP430FG461x, during flash memory programming

Supply voltage range, MSP430xG461x, during program execution

2.0

4.6 MHz

f (MHz)

System

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Figure 5-1. Frequency vs Supply Voltage

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5.4 Supply Current Into AVCC+ DVCCExcluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

(1) (2)

= f

= 32768 Hz, µA

(SMCLK)

= 1 MHz,

CG461x TA= –40°C to 85°C

FG461x TA= –40°C to 85°C

(1) (2)

TA= –40°C to 85°C µA

(AM)

(LPM0)

Active mode f

(MCLK)

(ACLK)

XTS = 0, SELM = (0, 1), (FG461x: program executes from flash)

Low power mode (LPM0)

Low-power mode (LPM2), VCC= 2.2 V 11 20

(LPM2)f(MCLK)

= f

(ACLK)

(SMCLK)

= 32768 Hz, SCG0 = 0

= 0 MHz, TA= –40°C to 85°C µA

(3) (2)

TA= –40°C 1.3 4.0 TA= 25°C 1.3 4.0

(LPM3)

Low-power mode (LPM3), f

= f

(MCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled, ACLK selected, LCD_A enabled, LCDCPEN = 0, (static mode, f

(SMCLK)

= 0 MHz,

LCD

= f

(ACLK)

/32)

(3) (4) (2)

TA= 60°C 2.22 6.5 TA= 85°C 6.5 15.0 TA= –40°C 1.9 5.0 TA= 25°C 1.9 5.0 TA= 60°C 2.5 7.5 TA= 85°C 7.5 18.0 TA= –40°C 1.5 5.5 TA= 25°C 1.5 5.5

(LPM3)

Low-power mode (LPM3), f

= f

(MCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled, ACLK selected, LCD_A enabled, LCDCPEN = 0, (4-mux mode; f

(SMCLK)

= 0 MHz,

= f

LCD

(ACLK)

/32)

(3) (4) (2)

TA= 60°C 2.8 7.0 TA= 85°C 7.2 17.0 TA= –40°C 2.5 6.5 TA= 25°C 2.5 6.5 TA= 60°C 3.2 8.0 TA= 85°C 8.5 20.0 TA= –40°C 0.13 1.0 TA= 25°C 0.22 1.0 TA= 60°C 0.9 2.5

Low-power mode (LPM4),

(LPM4)f(MCLK)

(ACLK)

= 0 MHz, f

= 0 Hz, SCG0 = 1

(SMCLK)

= 0 MHz, µA

(3) (2)

TA= 85°C 4.3 12.5 TA= –40°C 0.13 1.6 TA= 25°C 0.3 1.6 TA= 60°C 1.1 3.0 TA= 85°C 5.0 15.0

(1) Timer_B is clocked by f (2) Current for brownout included.

(DCOCLK)

= f

= 1 MHz. Allinputs aretied to 0 V or to VCC. Outputs do notsource orsink any current.

(DCO)

(3) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (4) The LPM3 currents are characterized with a Micro Crystal CC4V-T1A (9 pF) crystal and OSCCAPx = 1h.

VCC= 2.2 V 280 370 VCC= 3 V 470 580 VCC= 2.2 V 400 480 VCC= 3 V 600 740 VCC= 2.2 V 45 70 VCC= 3 V 75 110

VCC= 3 V 17 24

VCC= 2.2 V

VCC= 3 V

VCC= 2.2 V

VCC= 3 V

VCC= 2.2 V

VCC= 3 V

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µA

Current consumption of active mode versus system frequency, FG version: I

(AM)

= I

(AM) [1 MHz]

× f

(System)

[MHz] Current consumption of active mode versus supply voltage, FG version: I

= I

(AM)

(AM) [3 V]

+ 200 µA/V × (VCC– 3 V)

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.5 Thermal Characteristics

PARAMETER PACKAGE VALUE UNIT

JC,TOP

Junction-to-ambient thermal resistance, still air Junction-to-case (top) thermal resistance Junction-to-board thermal resistance

(3)

Junction-to-board thermal characterization parameter 12 °C/W Junction-to-top thermal characterization parameter 0.3 °C/W Junction-to-ambient thermal resistance, still air Junction-to-case (top) thermal resistance Junction-to-board thermal resistance

(3)

Junction-to-board thermal characterization parameter 21.2 °C/W Junction-to-top thermal characterization parameter 0.2 °C/W

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(1)

(2)

42 °C/W 10 °C/W

ZQW (S-PBGA-N113) 12 °C/W

(1)

(2)

43.5 °C/W

6.2 °C/W

PZ (S-PQFP-G100) 21.8 °C/W

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5.6 Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

IT+

IT–

hys

Positive-going input threshold voltage V

Negative-going input threshold voltage V

Input voltage hysteresis (V

IT+

– V

) V

IT–

VCC= 2.2 V 1.1 1.55 VCC= 3 V 1.5 1.98 VCC= 2.2 V 0.4 0.9 VCC= 3 V 0.9 1.3 VCC= 2.2 V 0.3 1.1 VCC= 3 V 0.5 1

5.7 Inputs Px.x, TAx, TBX

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

(int)

(cap)

(TAext)

(TBext)

(TAint)

(TBint)

External interrupt timing ns

Timer_A, Timer_B capture timing ns

Timer_A or Timer_B clock frequency TACLK, TBCLK externally applied to pin INCLK t

Timer A or Timer B clock frequency SMCLK or ACLK signal selected MHz

Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag

TA0, TA1, TA2 TB0, TB1, TB2, TB3, TB4, TB5, TB6

= t

(H)

(L)

(1) The external signal sets the interrupt flag every time the minimum t

shorter than t

5.8 Leakage Current – Ports P1 to P10

(int)

(1)

parameters are met. It may be set even with trigger signals

(int)

2.2 V 62 3 V 50

2.2 V 8 3 V 10

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

(2)

lkg(Px.y)

Leakage current, Port Px VCC= 2.2 V, 3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pins, unless otherwise noted. (2) The port pin must be selected as input.

V(Px.y) (1 ≤ × ≤ 10, 0 ≤ y ≤ 7)

MIN MAX UNIT

MHz

5.9 Outputs – Ports P1 to P10

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

(1) The maximum total current, I (2) The maximum total current, I

High-level output voltage V

Low-level output voltage V

and I

voltage drop. voltage drop.

OH(max)

and I

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= –1.5 mA, VCC= 2.2 V

OH(max)

= –6 mA, VCC= 2.2 V

OH(max)

= –1.5 mA, VCC= 3 V

OH(max)

= –6 mA, VCC= 3 V

OH(max)

= 1.5 mA, VCC= 2.2 V

OL(max)

= 6 mA, VCC= 2.2 V

OL(max)

= 1.5 mA, VCC= 3 V

OL(max)

= 6 mA, VCC= 3 V

OL(max)

, for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified

OL(max)

, for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified

OL(max)

(1) (2) (1)

(2)

(1) (2) (1)

(2)

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VCC– 0.25 V

VCC– 0.6 V

VCC– 0.25 V

VCC– 0.6 V

VSS+ 0.25

V V V

SS SS SS

VSS+ 0.6

VSS+ 0.25

VSS+ 0.6

CC CC CC CC

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5.10 Output Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(Px.y)

(MCLK)

(SMCLK)

(ACLK)

(Xdc)

(1 ≤ × ≤ 10, 0 ≤ y ≤ 7) CL= 20 F, IL= ±1.5 mA MHz

P1.1/TA0/MCLK P1.4/TBCLK/SMCLK

CL= 20 pF MHz

P1.5/TACLK/ACLK VCC= 3 V DC 12

P1.5/TACLK/ACLK, CL= 20 pF, VCC= 2.2 V, 3 V

Duty cycle of output frequency

P1.1/TA0/MCLK, CL= 20 pF, VCC= 2.2 V, 3 V

P1.4/TBCLK/SMCLK, CL= 20 pF, VCC= 2.2 V, 3 V

VCC= 2.2 V DC 10 VCC= 3 V DC 12

VCC= 2.2 V 10

(ACLK)

(MCLK)

(SMCLK)

= f = f = f

= f = f

(LFXT1) (LFXT1) (LFXT1)

(XT1)

(DCOCLK)

= f

(XT2)

= f

(DCOCLK)

= f = f

(XT1)

(LF)

40% 60% 30% 70%

50%

40% 60%

50% – 50%+

15 ns 15 ns

50%

40% 60%

50% – 50% +

15 ns 15 ns

50%

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0.0

-5.0

-10.0

-15.0

-20.0

-25.0

0.0 0.5 1.0 1.5 2.0 2.5

T =25 CA°

T =85 CA°

V =2.2V P2.0

V High-LevelOutputVoltage V

- -

I -typicalHigh-LevelOutputCurrent-mA

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

I TypicalHigh-LevelOutputCurren mA

- -

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

V High-LevelOutputVoltage V

- -

T =25 CA°

T =85 CA°

V =3V P2.0

25.0

20.0

15.0

10.0

5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5

V Low-LevelOutputVoltage V

– –

V =2.2V P2.0

T =25 CA°

T =85 CA°

I -TypicalLow-LevelOutputCurrent-mA

50.0

40.0

30.0

20.0

10.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

V Low-LevelOutputVoltage V

- -

I TypicalLow-LevelOutputCurrent mA

- -

V =3V P2.0

T =25 CA°

T =85 CA°

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.11 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

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Figure 5-2. Typical Low-Level Output Current vs Typical Low- Figure 5-3. Typical Low-Level Output Current vs Typical Low-

Figure 5-4. Typical High-Level Output Current vs Typical High- Figure 5-5. Typical High-Level Output Current vs Typical High-

Level Output Current Level Output Current

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.12 Wake-up Timing From LPM3

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f = 1 MHz 6

d(LPM3)

Delay time f = 2 MHz VCC= 2.2 V, 3 V 6 µs

f = 3 MHz 6

5.13 RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

VRAMh CPU halted

(1) This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution

should take place during this supply voltage condition.

(1)

1.6 V

5.14 LCD_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC(LCD)

LCD

PARAMETER TEST CONDITIONS V

Supply voltage

Supply current

(1)

Capacitor on LCDCAP

(3) (4)

Charge pump enabled (LCDCPEN = 1, VLCDx > 0000)

V VLCDx= 1000, all segments on, f no LCD connected

= 3 V, LCDCPEN = 1,

LCD(typ)

(2)

, TA= 25°C

Charge pump enabled (LCDCPEN = 1, VLCDx > 0000)

LCD

= f

/32, 2.2 V 3 µA

ACLK

LCD frequency 1.1 kHz

VLCDx = 0000 V VLCDx = 0001 2.60 VLCDx = 0010 2.66 VLCDx = 0011 2.72 VLCDx = 0100 2.78 VLCDx = 0101 2.84 VLCDx = 0110 2.90

LCD

LCD voltage

(4)

VLCDx = 0111 2.96 VLCDx = 1000 3.02 VLCDx = 1001 3.08 VLCDx = 1010 3.14 VLCDx = 1011 3.20 VLCDx = 1100 3.26 VLCDx = 1101 3.32 VLCDx = 1110 3.38 VLCDx = 1111 3.44 3.60

LCD

LCD driver output impedance 2.2 V 10 kΩ

(1) Refer to the supply current specifications I (2) Connecting an actual display increases the current consumption depending on the size of the LCD.

= 3 V, CPEN = 1,

LCD

VLCDx = 1000, I

for additional current specifications with the LCD_A module active.

(LPM3)

LOAD

= ±10 µΑ

(3) Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device. (4) Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and, therefore, cannot be used

MIN TYP MAX UNIT

2.2 3.6 V

4.7 µF

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Voltage@0.5V node

Voltage@0.25V node

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5.15 Comparator_A

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

(CC)

(Refladder/RefDiode)

(Ref025)

(Ref050)

CAON = 1, CARSEL = 0, CAREF = 0 µA

CAON = 1, CARSEL = 0, CAREF = (1, 2, 3), No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1

2.2 V 25 40 3 V 45 60

2.2 V 30 50 3 V 45 71

2.2 V, 3 V 0.23 0.24 0.25

2.2 V, 3 V 0.47 0.48 0.5

PCA0 = 1, CARSEL = 1, CAREF = 3, 2.2 V 390 480 540

(RefVT)

Vp– V V

hys

(response LH)

(response HL)

Common-mode input voltage range

Offset voltage

(2)

Input hysteresis CAON = 1 2.2 V, 3 V 0 0.7 1.4 mV

(1) The leakage current for the Comparator_A terminals is identical to I (2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The

No load at P1.6/CA0 and P1.7/CA1, mV TA= 85°C

3 V 400 490 550

CAON = 1 2.2 V, 3 V 0 VCC– 1 V

2.2 V, 3 V –30 30 mV

TA= 25°C, Overdrive 10 mV, without filter: CAF = 0

TA= 25°C, Overdrive 10 mV, without filter: CAF = 1

TA= 25°C, Overdrive 10 mV, without filter: CAF = 0

TA= 25°C, Overdrive 10 mV, without filter: CAF = 1

lkg(Px.x)

specification.

2.2 V 160 210 300 3 V 80 150 240

2.2 V 1.4 1.9 3.4 3 V 0.9 1.5 2.6

2.2 V 130 210 300 3 V 80 150 240

2.2 V 1.4 1.9 3.4 3 V 0.9 1.5 2.6

two successive measurements are then summed together.

MIN TYP MAX UNIT

µA

µs

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Overdrive

VCAOUT

t(response)

V+

V-

400mV

CAON

V+

CAF

Low-PassFilter

t »2µ

ToInternal Modules

SetCAIFG Flag

CAOUT

V-

VCC

0V

650

600

550

500

450

400

-45 -25

-5

15 35

55 75

T Free-AirTemperature C

- - °

V ReferenceVoltage mV

REF

- -

V =3V

Typical

650

600

550

500

450

400

-45 -25

-5

15 35

55 75

T Free-AirTemperature C

- - °

V ReferenceVoltage mV

REF

- -

V =2.2V

Typical

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5.16 Typical Characteristics – Comparator_A

SLAS508J –APRIL 2006–REVISED JUNE 2015

Figure 5-6. Reference Voltage vs Free-Air Temperature Figure 5-7. Reference Voltage vs Free-Air Temperature

Figure 5-8. Block Diagram of Comparator_A Module

Figure 5-9. Overdrive Definition

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CC(drop)

3V

0.5

1.5

0.001 1 1000

TypicalConditions

1ns 1ns

t -PulseWidth-

s t -PulseWidth-

V =3V

V -V

CC(drop)

d(BOR)

(B_IT-)

hys(B_IT-)

CC(start)

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.17 POR, BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(BOR)

CC(start)

(B_IT–)

hys(B_IT–)

(reset)

Brownout

(2) (3)

(1) The current consumption of the brownout module is already included in the ICCcurrent consumption data. (2) The voltage level V (3) During power up, the CPU begins code execution following a period of t

(B_IT–)

+ V

hys(B_IT–)

must not be changed until VCC≥ V MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout and SVS circuit.

dVCC/dt ≤ 3 V/s (see Figure 5-10) V

(B_IT– )

dVCC/dt ≤ 3 V/s (see Figure 5-10 through Figure 5-

12)

dVCC/dt ≤ 3 V/s (see Figure 5-10) 70 130 210 mV Pulse duration needed at RST/NMI pin to accepted

reset internally, VCC= 2.2 V, 3 V

2 µs

≤ 1.89 V.

CC(min)

, where V

after VCC= V

is the minimum supply voltage for the desired operating frequency. See the

CC(min)

d(BOR)

(B_IT–)

+ V

. The default FLL+settings

hys(B_IT–)

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(1)

2000 µs

0.7 ×

1.79 V

Figure 5-11. V

CC(drop)

Level with a Square Voltage Drop to Generate a POR or BOR Signal

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Figure 5-10. POR, BOR vs Supply Voltage

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0.5

1.5

CC(drop)

tpw-PulseWidth-ms

CC(d ro p )

- V

3V

0.001 1 1000

tpw-PulseWidth-ms

t =t

f r

TypicalConditions

V =3V

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Figure 5-12. V

CC(drop)

Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

5.18 SVS (Supply Voltage Supervisor and Monitor)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(SVSR)

d(SVSon)

settle

(SVSstart)

hys(SVS_IT–)

(SVS_IT–)

(3)

CC(SVS)

(1) t (2) The recommended operating voltage range is limited to 3.6 V.

(3) The current consumption of the SVS module is not included in the ICCcurrent consumption data.

is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD

settle

value from 2 to 15. The overdrive is assumed to be > 50 mV.

dVCC/dt > 30 V/ms (see Figure 5-13) 5 150 dVCC/dt ≤ 30 V/ms 2000 SVS on, switch from VLD = 0 to VLD ≠ 0, VCC= 3 V 150 300 µs

(1)

VLD ≠ 0 VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-13) 1.55 1.7 V

VCC/dt ≤ 3 V/s (see Figure 5-13)

VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage applied on A7

VCC/dt ≤ 3 V/s (see Figure 5-13)

VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage applied on A7

VLD ≠ 0, VCC= 2.2 V, 3 V 10 15 µA

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VLD = 1 70 120 155 mV VLD = 2 to 14

VLD = 15 4.4 20 mV VLD = 1 1.8 1.9 2.05

VLD = 2 1.94 2.1 2.23 VLD = 3 2.05 2.2 2.35 VLD = 4 2.14 2.3 2.46 VLD = 5 2.24 2.4 2.58 VLD = 6 2.33 2.5 2.69 VLD = 7 2.46 2.65 2.84 VLD = 8 2.58 2.8 2.97 VLD = 9 2.69 2.9 3.10 VLD = 10 2.83 3.05 3.26 VLD = 11 2.94 3.2 3.39 VLD = 12 3.11 3.35 3.58 VLD = 13 3.24 3.5 3.73 VLD = 14 3.43 3.7

VLD = 15 1.1 1.2 1.3

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(SVS_IT–)

× 0.001 × 0.016

(SVS_IT–)

(2)

3.96

µs

12 µs

(2) (2) (2)

0.5

1.5

1ns 1ns

tpw-PulseWidth-ms

3V

1 10 1000

t-PulseWidth-ms

100

3V

t =t

f r

RectangularDrop

TriangularDrop

CC(drop)

CC(d ro p )

- V

CC(drop)

CC(start)

(B_IT-)

Brownout

Region

(SVSstart)

(SVS_IT-)

SoftwareSetsVLD>0:

SVSis Active

d(SVSR)

undefined

hys(SVS_IT-)

d(BOR)

Brownout

d(SVSon)

d(BOR)

SetPOR

Brown

Out

Region

SVSCircuitis ActiveFromVLD>toVCC<V(B_IT-)

SVSOut

Vhys(B_IT-)

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Figure 5-13. SVS Reset (SVSR) vs Supply Voltage

Figure 5-14. V

CC(drop)

with a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal

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T -

CV -V

1.8 3.0

2.4 3.6

1.0

20 6040 85

1.0

0-20-400

(DCO)

(DCO3V)

(DCO)

(DCO20 C)°

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.19 DCO

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

= 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,

(DCOCLK)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO)

DCOPLUS = 0

2.2 V, 3 V 1 MHz

FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 MHz

FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 MHz

FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 MHz

FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 MHz

FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1 MHz

Step size between adjacent DCO taps: Sn= f

DCO(Tap n+1)/fDCO(Tap n)

Temperature drift, N FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0

Drift with VCCvariation, N FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0

(see Figure 5-16 for taps 21 to 27)

= 01Eh,

(DCO)

= 01Eh,

(DCO)

1 < TAP ≤ 20 1.06 1.11

2.2 V 0.3 0.65 1.25

3 V 0.3 0.7 1.3

2.2 V 2.5 5.6 10.5

3 V 2.7 6.1 11.3

2.2 V 0.7 1.3 2.3

3 V 0.8 1.5 2.5

2.2 V 5.7 10.8 18

3 V 6.5 12.1 20

2.2 V 1.2 2 3

3 V 1.3 2.2 3.5

2.2 V 9 15.5 25

3 V 10.3 17.9 28.5

2.2 V 1.8 2.8 4.2

3 V 2.1 3.4 5.2

2.2 V 13.5 21.5 33

3 V 16 26.6 41

2.2 V 2.8 4.2 6.2

3 V 4.2 6.3 9.2

2.2 V 21 32 46

3 V 30 46 70

TAP = 27 1.07 1.17

2.2 V –0.2 –0.3 –0.4

3 V –0.2 –0.3 –0.4

MIN TYP MAX UNIT

0 5 15 %/V

%/°C

Figure 5-15. DCO Frequency vs Supply Voltage VCCand vs Ambient Temperature

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DCOFrequency AdjustedbyBits 2 to2 inSCFI1{N }

9 5

{DCO}

FN_2=0 FN_3=0 FN_4=0 FN_8=0

FN_2=1 FN_3=0 FN_4=0 FN_8=0

FN_2=x FN_3=1 FN_4=0 FN_8=0

FN_2=x FN_3=x FN_4=1 FN_8=0

FN_2=x FN_3=x FN_4=x

FN_8=1

Legend

ToleranceatTap27

ToleranceatTap2

OverlappingDCORanges: UninterruptedFrequencyRange

(DCO)

1 2720

1.11

1.17

DCOTap

Sn - S te p s iz e Ratio b et w een D C O Ta p s

Min

Max

1.07

1.06

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Figure 5-16. DCO Tap Step Size

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Figure 5-17. Five Overlapping DCO Ranges Controlled by FN_x Bits

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.20 Crystal Oscillator, LFXT1 Oscillator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OSCCAPx = 0h, VCC= 2.2 V, 3 V 0

V V

XIN

XOUT

IL IH

Integrated input capacitance

Integrated output capacitance

Low-level input voltage at XIN VCC= 2.2 V, 3 V High-level input voltage at XIN VCC= 2.2 V, 3 V

(3)

(1) The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is

× C

) / (C

+ C

XIN

(2) To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.

XOUT

XIN

). This is independent of XTS_FLL.

XOUT

• Keep the trace between the MCU and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

(3) TI recommends external capacitance for precision real-time clock applications; OSCCAPx = 0h. (4) Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.

OSCCAPx = 1h, VCC= 2.2 V, 3 V 10 OSCCAPx = 2h, VCC= 2.2 V, 3 V 14 OSCCAPx = 3h, VCC= 2.2 V, 3 V 18 OSCCAPx = 0h, VCC= 2.2 V, 3 V 0 OSCCAPx = 1h, VCC= 2.2 V, 3 V 10 OSCCAPx = 2h, VCC= 2.2 V, 3 V 14 OSCCAPx = 3h, VCC= 2.2 V, 3 V 18

(4) (4)

0.8 × V

SS CC

(1) (2)

0.2 × V

V V

5.21 Crystal Oscillator, XT2 Oscillator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

XT2IN

XT2OUT

(1) The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. (2) Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

Integrated input capacitance VCC= 2.2 V, 3 V 2 pF Integrated output capacitance VCC= 2.2 V, 3 V 2 pF

Input levels at XT2IN

VCC= 2.2 V, 3 V

(2)

0.8 × V

(1)

0.2 × V

5.22 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI

BITCLK

USCI input clock frequency External: UCLK f

Duty cycle = 50% ±10%

BITCLK clock frequency (equals baud rate in MBaud)

UART receive deglitch time UART

(1)

2.2 V, 3 V 1 MHz

2.2 V 50 150 600 3 V 50 100 600

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

MIN TYP MAX UNIT

SYSTEM

V V

MHz

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5.23 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18 and Figure 5-19)

USCI

SU,MI

HD,MI

VALID,MO

PARAMETER TEST CONDITIONS V

USCI input clock frequency f

SMCLK, ACLK Duty cycle = 50% ±10%

SOMI input data setup time ns

iSOMI input data hold time ns

SIMO output data valid time UCLK edge to SIMO valid, CL= 20 pF ns

2.2 V 110 3 V 75

2.2 V 0 3 V 0

2.2 V 30 3 V 20

MIN MAX UNIT

SYSTEM

5.24 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-20 and Figure 5-21)

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

SU,SI

HD,SI

VALID,SO

PARAMETER TEST CONDITIONS V

STE lead time STE low to clock

STE lag time Last clock to STE high

STE access time STE low to SOMI data out

STE disable time STE high to SOMI high impedance

SIMO input data setup time ns

SIMO input data hold time ns

SOMI output data valid time UCLK edge to SOMI valid, CL= 20 pF ns

2.2 V, 3 V 50 ns

2.2 V, 3 V 10 ns

2.2 V, 3 V 50 ns

2.2 V 20 3 V 15

2.2 V 10 3 V 10

2.2 V 75 110 3 V 50 75

MIN TYP MAX UNIT

MHz

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UCLK

CKPL = 0

CKPL = 1

SIMO

1/f

UC xCLK

LOW /HIGHtLOW /HIGH

SOMI

SU ,MI

HD ,MI

VALID , MO

UCLK

CKPL = 0

CKPL = 1

SIMO

1/f

UCx CLK

LOW /HIGHtLOW /HIGH

SOMI

SU ,MI

HD ,MI

VALID , MO

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Figure 5-18. SPI Master Mode, CKPH = 0

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Figure 5-19. SPI Master Mode, CKPH = 1

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STE

UCLK

CKPL =0

CKPL =1

STE ,LEAD

STE ,LAG

ACC

DIS

LOW /HIGHtLOW /HIGH

SU ,SI

HD ,SI

VALID , SO

SO MI

SI MO

1/f

UCx CLK

STE

UCLK

CKPL = 0

CKPL = 1

SOMI

ACC

DIS

1/f

UCx CLK

LOW /HIGHtLOW /HIGH

SIMO

SU ,SIMO

HD ,SIMO

VALID , SOMI

STE ,LEAD

STE ,LAG

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Figure 5-20. SPI Slave Mode, CKPH = 0

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Figure 5-21. SPI Slave Mode, CKPH = 1

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SDA

SCL

LOW

HD ,DAT

SU , DAT

HD ,STA

SU ,STAtHD ,STA

HIGH

SU ,STO

BUF

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5.25 USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-22)

USCI

SCL

HD,STA

SU,STA

HD,DAT

SU,DAT

SU,STO

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI input clock frequency External: UCLK f

Duty Cycle = 50% ±10%

SCL clock frequency 2.2 V, 3 V 0 400 kHz

≤ 100 kHz 2.2 V, 3 V 4

Hold time (repeated) START µs

Setup time for a repeated START µs

SCL

> 100 kHz 2.2 V, 3 V 0.6

SCL

≤ 100 kHz 2.2 V, 3 V 4.7

SCL

> 100 kHz 2.2 V, 3 V 0.6

SCL

Data hold time 2.2 V, 3 V 0 ns Data setup time 2.2 V, 3 V 250 ns Setup time for STOP 2.2 V, 3 V 4 µs

Pulse duration of spikes suppressed by input filter

2.2 V 50 150 600 3 V 50 100 600

MIN TYP MAX UNIT

SYSTEM

MHz

Figure 5-22. I2C Mode Timing

5.26 USART1

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

USART1 deglitch time ns

(τ)

(1) The signal applied to the USART1 receive signal (terminal) (URXD1) must meet the timing requirements of t

flip-flop is set. The URXS flip-flop is set with negative pulses that meet the minimum-timing condition of t set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD1 line.

VCC= 2.2 V, SYNC = 0, UART mode 200 430 800 VCC= 3 V, SYNC = 0, UART mode 150 280 500

to ensure that the URXS

(τ)

. The operating conditions to

(τ)

(1)

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5.27 12-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(P6.x/Ax)

ADC12

REF+

Analog supply voltage AVSSand DVSSare connected together, 2.2 3.6 V

Analog input voltage range

Operating supply current into AVCCterminal

(3)

(4)

Input capacitance VCC= 2.2 V 40 pF Input MUX ON resistance 0 V ≤ VAx≤ V

(1) The leakage current is defined in the leakage current table with Ax parameter. (2) The analog input voltage range must be within the selected reference voltage range VR+to VR–for valid conversion results. (3) The internal reference supply current is not included in current consumption parameter I (4) The internal reference current is supplied from terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.

AVCCand DVCCare connected together, V

= V

(AVSS)

All external Ax terminals, Analog inputs selected in

(2)

ADC12MCTLx register, P6Sel.x = 1, 0 V V

≤ VAx≤ V

(AVSS)

ADC12CLK

ADC12ON = 1, REFON = 0, mA SHT0 = 0, SHT1 = 0, ADC12DIV = 0

ADC12CLK

ADC12ON = 0, REFON = 1, REF2_5V = 1 f

ADC12CLK

ADC12ON = 0, REFON = 1, REF2_5V = 0

= 0 V

(DVSS)

(AVCC)

= 5.0 MHz, VCC= 2.2 V 0.65 1.3

VCC= 3 V 0.8 1.6

= 5.0 MHz,

VCC= 3 V 0.5 0.8 VCC= 2.2 V 0.5 0.8

VCC= 3 V 0.5 0.8

Only one terminal can be selected at one time, Ax

AVCC

VCC= 3 V 2000 Ω

ADC12

(1)

AVCC

5.28 12-Bit ADC, External Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REF+

/Ve

REF–

(Ve

– Differential external reference

REF+

/Ve

REF–

VeREF+

VREF–/VeREF–

Positive external reference voltage input

Negative external reference voltage input

) voltage input

Input leakage current 0 V ≤ Ve Input leakage current 0 V ≤ Ve

REF+

> V

REF+ REF–

REF–

/Ve

≤ V ≤ V

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

REF–

AVCC AVCC

(2)

(3)

(4)

VCC= 2.2 V, 3 V ±1 µA VCC= 2.2 V, 3 V ±1 µA

(1)

1.4 V

AVCC

0 1.2 V

1.4 V

AVCC

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VREF+

1mF

1ms

10ms

100ms t

REFON

.66xC [ms]withC in

VREF+ VREF+

100mF

10mF

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5.29 12-Bit ADC, Built-In Reference

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REF2_5V = 1 for 2.5 V,

REF+

CC(min)

VREF+

L(VREF+)

Positive built in reference voltage output

AVCCminimum voltage, Positive built in reference active

Load current out of V terminal

Load-current regulation, V terminal

REF+

max ≤ I

VREF+

REF2_5V = 0 for 1.5 V, I

max ≤ I

VREF+

REF2_5V = 0, I REF2_5V = 1, I REF2_5V = 1, I

= 500 µA ±100 µA, VCC= 2.2 V ±2

VREF+

Analog input voltage ≈ 0.75 V, REF2_5V = 0

= 500 µA ±100 µA,

VREF+

Analog input voltage ≈ 1.25 V, VCC= 3 V ±2

VREF+

VREF+ VREF+ VREF+

≤ I

VREF+

≤ I

VREF+

max ≤ I min ≥ I min ≥ I

min

VREF+ VREF+

REF2_5V = 1 I

= 100 µA → 900 µA,

DL(VREF+)

VREF+

REF+

REFON

Load current regulation, VREF+ terminal

Capacitance at pin V

REF+

(1)

Temperature coefficient of built- I in reference 0 mA ≤ I

Settling time of internal reference I voltage (see Figure 5-23 )

(2)

VREF+

= 5 µF, Ax ≈ 0.5 × V

VREF+

Error of conversion result ≤ 1 LSB

REF+

REFON = 1, 0 mA ≤ I

VREF+

REF+

≤ I

VREF+

max

is a constant in the range of

≤ 1 mA

VREF+

= 0.5 mA, C

= 1.5 V, V

AVCC

VREF+

= 2.2 V

= 10 µF,

(1) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two

capacitors between pins V

(2) The condition is that the error in a conversion started after t

capacitive load.

and AVSSand V

REF+

REF-–

/Ve

and AVSS: 10-µF tantalum and 100-nF ceramic.

REF–

is less than ±0.5 LSB. The settling time depends on the external

REFON

VCC= 3 V 2.4 2.5 2.6

VCC= 2.2 V, 3 V 1.44 1.5 1.56

≤ I

VREF+

min 2.2

VREF+

≥ –0.5 mA 2.8 V ≥ – 1 mA 2.9

VCC= 2.2 V 0.01 –0.5 VCC= 3 V 0.01 –1

VCC= 3 V ±2

, VCC= 3 V 20 ns

VCC= 2.2 V, 3 V 5 10 µF

VCC= 2.2 V, 3 V ±100 ppm/°C

LSB

17 ms

Figure 5-23. Typical Settling Time of Internal Reference t

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vs External Capacitor on V

REFON

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REF+

10 m F 100 nF

MSP430FG461x

10 m F 100 nF

SS1/2

CC1/2

From Power Supply

ApplyExternalReference[V ]

eREF+

orUseInternalReference[V ]

REF+

V orV

REF+ eREF+

V /V

REF- eREF-

ReferenceIsInternally Switchedto AV

10 m F 100 nF

MSP430FG461x

10 m F 100 nF

SS1/2

CC1/2

From

Power

Supply

Apply

External

Reference

ApplyExternalReference[V ]

eREF+

orUseInternalReference[V ]

REF+

V orV

REF+ eREF+

V /V

REF- eREF-

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Figure 5-24. Supply Voltage and Reference Voltage Design V

Figure 5-25. Supply Voltage and Reference Voltage Design V

REF–

/Ve

REF–

/Ve

External Supply

REF–

= AVSS, Internally Connected

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5.30 12-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

ADC12CLK

ADC12OSC

CONVERT

Internal ADC12 ADC12DIV = 0, oscillator f

Conversion time µs

For specified performance of ADC12 linearity parameters

ADC12CLK

C f

ADC12OSC

External f SMCLK,

= f

ADC12OSC

≥ 5 µF, Internal oscillator,

VREF+

= 3.7 MHz to 6.3 MHz

ADC12CLK

from ACLK, MCLK, or

ADC12SSEL ≠ 0

ADC12ON

Sample

Turnon settling time of the ADC

Sampling time ns

(1) The condition is that the error in a conversion started after t

settled.

(2) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:

Sample

n+1

= ln(2

) × (RS+ RI) x CI+ 800 ns where n = ADC resolution = 12, RS= external source resistance.

(1)

RS= 400 Ω,RI= 1000 Ω, CI= 30pF, τ = [RS +RI] × C

(2)

ADC12ON

is less than ±0.5 LSB. The reference and input signal are already

2.2 V, 3 V 0.45 5 6.3 MHz

2.2 V, 3 V 3.7 5 6.3 MHz

2.2 V, 3 V 2.06 3.51

3 V 1220

2.2 V 1400

MIN TYP MAX UNIT

13 × ADC12DIV

× 1/f

ADC12CLK

5.31 12-Bit ADC, Linearity Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Integral linearity

error Differential linearity (Ve

error C

Offset error Internal impedance of source RS < 100 Ω, 2.2 V, 3 V ±2 ±4 LSB

Gain error 2.2 V, 3 V ±1.1 ±2 LSB

Total unadjusted (Ve

error CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)

1.4 V ≤ (Ve

1.6 V < (Ve

REF+

= 10 µF (tantalum) and 100 nF (ceramic)

VREF+

(Ve

REF+

= 10 µF (tantalum) and 100 nF (ceramic)

VREF+

(Ve

REF+

= 10 µF (tantalum) and 100 nF (ceramic)

VREF+

REF+

– V

-– V

REF+ REF+

REF–

– V – V

/Ve

REF–

/Ve

REF–

) min ≤ (Ve

REF–

) min ≤ (Ve

REF–

)min ≤ (Ve

REF–

) min ≤ 1.6 V ±2

REF–

) min ≤ [V

REF–

)min ≤ (Ve

REF+

REF+–VREF–

] ±1.7

AVCC

– V

/Ve

REF–

– V

REF–

/Ve

2.2 V, 3 V LSB

2.2 V, 3 V ±1 LSB

2.2 V, 3 V ±2 ±5 LSB

MIN TYP MAX UNIT

100 ns

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5.32 12-Bit ADC, Temperature Sensor and Built-In V

MID

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

SENSOR

SENSOR(sample)

VMID

MID

VMID(sample)

(1) The sensor current I

high). When REFON = 1, I

(2) The temperature sensor offset can be as much as ±20°C. TI recommends a single-point calibration to minimize the offset error of the

Operating supply current REFON = 0, INCH = 0Ah, into AVCCterminal

(2)

(1)

ADC12ON = N/A, TA= 25°C ADC12ON = 1, INCH = 0Ah,

TA= 0°C ADC12ON = 1, INCH = 0Ah 2.2 V, 3 V 3.55 ±3% mV/°C

Sample time required if ADC12ON = 1, INCH = 0Ah, channel 10 is selected

Current into divider at channel 11

(4)

AVCCdivider at channel 11 V

Sample time required if ADC12ON = 1, INCH = 0Bh, channel 11 is selected

is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is

SENSOR

(3)

Error of conversion result ≤ 1 LSB

ADC12ON = 1, INCH = 0Bh µA

ADC12ON = 1, INCH = 0Bh, V

≈ 0.5 × V

MID

(5)

Error of conversion result ≤ 1 LSB

is already included in I

AVCC

REF+

2.2 V 40 120 3 V 60 160

2.2 V, 3 V 986 mV

2.2 V 30 3 V 30

2.2 V N/A 3 V N/A

2.2 V 1.1 1.1 ±0.04 3 V 1.5 1.50 ±0.04

2.2 V 1400 3 V 1220

built-in temperature sensor. (3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t (4) No additional current is needed. The V (5) The on-time t

is included in the sampling time t

VMID(on)

is used during sampling.

MID

VMID(sample)

; no additional on time is needed.

MIN TYP MAX UNIT

µA

µs

(4) (4)

SENSOR(on)

5.33 12-Bit DAC, Supply Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Analog supply voltage AVCC= DVCC, AVSS= DVSS= 0 V 2.20 3.60 V

DAC12AMPx = 2, DAC12IR = 0, DAC12_xDAT = 0800h

DAC12AMPx = 2, DAC12IR = 1, DAC12_xDAT = 0800h, 50 110 Ve

= V

REF+

= AV

2.2 V, 3 V µA

Supply current, single DAC

(1) (2)

channel

REF+

DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0800h, 200 440 Ve

REF+

DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0800h, 700 1500 Ve

= V

REF+

DAC12_xDAT = 800h, V

PSRR 70 dB

Power-supply rejection

(3)(4)

ratio

ΔAVCC= 100 mV DAC12_×DAT = 800h, V

ΔAVCC= 100 mV

REF+

= AV

REF

= 1.5 V,

= 1.5 V or 2.5 V,

2.2 V

3 V

(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly. (2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. (3) PSRR = 20× log{ΔAVCC/ΔV (4) V

is applied externally. The internal reference is not used.

REF

DAC12_xOUT

MIN TYP MAX UNIT

50 110

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Positive

Negative

R+

GainError

OffsetError

DACCode

DACV

OUT

Idealtransfer function

Load

=100pF

DACOutput

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5.34 12-Bit DAC, Linearity Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-26)

PARAMETER TEST CONDITIONS V

Resolution 12-bit monotonic 12 bits

= 1.5 V,

INL Integral nonlinearity

(1)

DNL Differential nonlinearity

Offset voltage without calibration

Offset voltage with calibration

E(O)/dT

E(G)/dT

Offset error temperature coefficient

Gain error

(1)

Gain temperature coefficient

ref

DAC12AMPx = 7, DAC12IR = 1 V

= 2.5 V,

ref

DAC12AMPx = 7, DAC12IR = 1 V

= 1.5 V,

ref

(1)

(1) (2)

(1)

DAC12AMPx = 7, DAC12IR = 1 V

= 2.5 V,

ref

DAC12AMPx = 7, DAC12IR = 1 V

= 1.5 V,

ref

DAC12AMPx = 7, DAC12IR = 1

(1) (2)

= 2.5 V,

ref

DAC12AMPx = 7, DAC12IR = 1 V

= 1.5 V,

ref

DAC12AMPx = 7, DAC12IR = 1 V

= 2.5 V,

ref

DAC12AMPx = 7, DAC12IR = 1

(1)

= 1.5 V 2.2 V

REF

= 2.5 V 3 V

REF

2.2 V

3 V

2.2 V

3 V

2.2 V

3 V

2.2 V

3 V

2.2 V, 3 V ±30 µV/°C

2.2 V, 3 V 10

DAC12AMPx = 2 100

Offset_Cal

Time for offset calibration

(3)

DAC12AMPx = 3, 5 2.2 V, 3 V 32 ms DAC12AMPx = 4, 6, 7 6

(1) Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and “b” of

the first order equation: y = a + b × x. V (2) The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting bit DAC12CALON.

DAC12_xOUT

= EO+ (1 + EG) × (Ve

/4095) × DAC12_xDAT, DAC12IR = 1.

REF+

(3) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =

{0, 1}. TI recommends that the DAC12 module be configured before initiating calibration. Port activity during calibration may effect

accuracy and is not recommended.

MIN TYP MAX UNIT

±2.0 ±8.0 LSB

±0.4 ±1.0 LSB

±21

±2.5

±3.5 %FSR

ppm of

FSR/°C

Figure 5-26. Linearity Test Load Conditions and Gain and Offset Definition

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DAC12_xDAT-DigitalCode

DNL -DifferentialNonlinearityError-LSB

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0 0 512 1024 1536

2048

2560 3072

3584 4095

V =2.2V,V =1/.5V DAC12AMPx=7

DAC12IR=1

CC REF

V = 2.2 V, V = 1.5 V DAC12AMPx = 7

DAC12IR = 1

CC REF

-1

-2

-3

-4 0 512 1024 1536

2048

2560 3072

3584 4095

DAC12_xDAT – Digital Code

INL – Integral Nonlinearity Error – LSB

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Figure 5-27. Typical INL Error vs Digital Input Data

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Figure 5-28. Typical DNL Error vs Digital Input Data

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O/P(DAC12_x)

Max

0.3

AVCC-0.3V

OUT

Min

Load

=100pF

Load

DAC12

O/P(DAC12_x)

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.35 12-Bit DAC, Output Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

No load, Ve DAC12_xDAT = 0h, DAC12IR = 1, 0 0.005

REF+

= AVCC,

DAC12AMPx = 7 No load, Ve

DAC12_xDAT = 0FFFh, DAC12IR = 1, AV

Output voltage range (see

Figure 5-29)

(1)

DAC12AMPx = 7 R

= 3 kΩ, Ve

Load

DAC12_xDAT = 0h, DAC12IR = 1, 0 0.1

REF+

= AVCC,

REF+

DAC12AMPx = 7 R

= 3 kΩ, Ve

Load

DAC12_xDAT = 0FFFh, DAC12IR = 1, AV

REF+

DAC12AMPx = 7

L(DAC12)

O/P(DAC12)

Max DAC12 load capacitance

Max DAC12 load current mA

= 3 kΩ, V

Output resistance (see

Figure 5-29)

Load

DAC12AMPx = 2, DAC12_xDAT = 0h R

= 3 kΩ,

Load

O/P(DAC12)

DAC12_xDAT = 0FFFh R

= 3 kΩ,

Load

0.3 V ≤ V

O/P(DAC12)

> AVCC– 0.3 V, 2.2 V, 3 V 150 250 Ω

O/P(DAC12)

(1) Data is valid after the offset calibration of the output amplifier.

= AVCC,

< 0.3 V,

≤ AVCC– 0.3 V

2.2 V, 3 V V

2.2 V, 3 V 100 pF

2.2 V –0.5 +0.5 3 V –1.0 +1.0

MIN TYP MAX UNIT

AVCC–

0.05

AVCC–

0.13

150 250

1 4

Figure 5-29. DAC12_x Output Resistance Tests

5.36 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

REF+

(VREF+)

(Ri

(VeREF+)

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). (2) The maximum voltage applied at reference input voltage terminal Ve (3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). (4) The maximum voltage applied at reference input voltage terminal Ve (5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel

reducing the reference input resistance.

Reference input voltage range

Reference input resistance 2.2 V, 3 V

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MIN TYP MAX UNIT

AVCC/3 AVCC+ 0.2

AVCCAVCC+ 0.2

DAC12IR = 0 DAC12IR = 1

(1) (2) (3) (4)

2.2 V, 3 V V

DAC12_0 IR = DAC12_1 IR = 0 20 MΩ DAC12_0 IR = 1, DAC12_1 IR = 0 DAC12_0 IR = 0, DAC12_1 IR = 1 DAC12_0 IR = DAC12_1 IR = 1,

DAC12_0 SREFx = DAC12_1 20 24 28

(5)

SREFx

= [AVCC– V

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REF+

= [AVCC– V

REF+

E(O)

40 48 56

] / [3 × (1 + EG)]. ] / (1 + EG).

kΩ

Conversion1 Conversion2

OUT

Conversion3

10%

SRLH

SRHL

90%

10%

90%

Load

=100pF

DACOutput

O/P(DAC12.x)

Load

Conversion1 Conversion2

OUT

Conversion3

Glitch

Energy

+/-1/2LSB

settleLH

settleHL

=3k

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5.37 12-Bit DAC, Dynamic Specifications

= VCC, DAC12IR = 1, over recommended ranges of supply voltage and operating free-air temperature (unless otherwise

ref

noted) (see Figure 5-30 and Figure 5-31)

PARAMETER TEST CONDITIONS V

DAC12 on time Error

(see Figure 5-30)

< ±0.5 LSB

V(O)

DAC12_xDAT = 800h,

DAC12AMPx = 0 → {2, 3, 4} 60 120

(1)

DAC12AMPx = 0 → {5, 6} 2.2 V, 3 V 15 30 µs DAC12AMPx = 0 → 7 6 12

DAC12AMPx = 2 100 200

S(FS)

Settling time, full scale DAC12AMPx = 3,5 2.2 V, 3 V 40 80 µs

DAC12_xDAT = 80h→F7Fh→80h

DAC12AMPx = 4, 6, 7 15 30 DAC12AMPx = 2 5

DAC12AMPx = 4, 6, 7 1

S(C–C)

Settling time, code to code 3F8h→408h→3F8h DAC12AMPx = 3,5 2.2 V, 3 V 2 µs

DAC12_xDAT = BF8h→C08h→BF8h

DAC12AMPx = 2 0.05 0.12

SR Slew rate DAC12AMPx = 3,5 2.2 V, 3 V 0.35 0.7 V/µs

DAC12_xDAT = 80h→F7Fh→80h

(2)

DAC12AMPx = 4, 6, 7 1.5 2.7 DAC12AMPx = 2 600

Glitch energy, full-scale DAC12AMPx = 3,5 2.2 V, 3 V 150 nV-s

DAC12_xDAT = 80h→F7Fh→80h

DAC12AMPx = 4, 6, 7 30

(1) R (2) Slew rate applies to output voltage steps ≥ 200 mV.

Load

and C

connected to AVSS(not AVCC/2) in Figure 5-30.

Load

MIN TYP MAX UNIT

Figure 5-30. Settling Time and Glitch Energy Testing

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Figure 5-31. Slew Rate Testing

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DAC12_xDAT 080h

OUT

1/f

Toggle

F7Fh

DAC12_yOUT

080h F7Fh 080h

DAC12_xOUT

REF+

Load

= 100 pF

Load

DAC12_1

Load

= 100 pF

Load

DAC12_0

DAC0

DAC1

REF+

Load

=100pF

Load

DAC12_x

DACx

=3k

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5.38 12-Bit DAC, Dynamic Specifications Continued

TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS V

DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h

DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h

DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h

DAC12_0DAT = 800h, No Load, DAC12_1DAT = 80h↔F7Fh, R f

DAC12_1OUT

= 10 kHz at 50/50 duty cycle

DAC12_0DAT = 80h↔F7Fh, R DAC12_1DAT = 800h, No Load, –80 f

DAC12_0OUT

= 10 kHz at 50/50 duty cycle

Load

(1) R

–3dB

3-dB bandwidth, VDC= 1.5 V, VAC= 0.1 VPP 2.2 V, 3 V 180 kHz (see Figure 5-32)

Channel-to-channel crosstalk 2.2 V, 3 V dB (see Figure 5-33)

= 3 kΩ, C

LOAD

(1)

= 100 pF

SLAS508J –APRIL 2006–REVISED JUNE 2015

MIN TYP MAX UNIT

550

= 3 kΩ –80

= 3 kΩ,

Figure 5-32. Test Conditions for 3-dB Bandwidth Specification

Figure 5-33. Crosstalk Test Conditions

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5.39 Operational Amplifier OA, Supply Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Supply voltage 2.2 3.6 V

Fast Mode, OARRIP = 1 (rail-to-rail mode off) 180 290 Medium Mode, OARRIP = 1 (rail-to-rail mode off) 110 190

Supply current

(1)

Slow Mode, OARRIP = 1 (rail-to-rail mode off) 50 80 Fast Mode, OARRIP = 0 (rail-to-rail mode on) 300 490

2.2 V, 3 V µA

Medium Mode, OARRIP = 0 (rail-to-rail mode on) 190 350 Slow Mode, OARRIP = 0 (rail-to-rail mode on) 90 190

PSRR Power supply rejection ratio Noninverting 2.2 V, 3 V 70 dB

(1) P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.

MIN TYP MAX UNIT

5.40 Operational Amplifier OA, Input/Output Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

I/P

Ikg

Voltage supply, I/P V

Input leakage current, I/P

OARRIP = 1 (rail-to-rail mode off) –0.1 VCC– 1.2 OARRIP = 0 (rail-to-rail mode on) –0.1 VCC+ 0.1 TA= –40 to +55°C –5 ±0.5 5

(1) (2)

TA= +55 to +85°C –20 ±5 20

Fast Mode 50 Medium Mode f

Voltage noise density, I/P nV/√HZ

Slow Mode Fast Mode 30 Medium Mode f

= 1 kHz

V(I/P)

= 10 kHz 50

V(I/P)

Slow Mode 65

O/P (OAx)

Offset voltage, I/P 2.2 V, 3 V ±10 mV Offset temperature drift, I/P Offset voltage drift with supply, 0.3 V ≤ VIN≤ VCC– 0.3 V

I/P ΔVCC≤ ±10%, TA= 25°C

High-level output voltage, O/P V

Low-level output voltage, O/P V

Output resistance (see

Figure 5-34)

(4)

(3)

2.2 V, 3 V ±10 µV/°C

2.2 V, 3 V ±1.5 mV/V

Fast Mode, I Slow Mode, I Fast Mode, I Slow Mode, I R

= 3 kΩ, C

Load

OARRIP = 0 (rail-to-rail mode on), 150 250 V

R OARRIP = 0 (rail-to-rail mode on), 2.2 V, 3 V Ω V

R OARRIP = 0 (rail-to-rail mode on),

0.2 V ≤ V

O/P(OAx)

= 3 kΩ, C

Load

O/P(OAx)

= 3 kΩ, C

Load

< 0.2 V

> AVCC– 0.2 V

O/P(OAx)

≤ –500 µA 2.2 V VCC– 0.2 V

SOURCE

≤ –150 µA 3 V VCC– 0.1 V

SOURCE

≤ +500 µA 2.2 V V

SOURCE

≤ +150 µA 3 V V

SOURCE

= 50 pF,

Load

= 50 pF,

Load

= 50 pF,

Load

≤ AVCC– 0.2 V

CMRR Common-mode rejection ratio Noninverting 2.2 V, 3 V 70 dB

(1) ESD damage can degrade input current leakage. (2) The input bias current is overridden by the input leakage current. (3) Calculated using the box method. (4) Specification valid for voltage-follower OAx configuration.

MIN TYP MAX UNIT

140

CC SS SS

0.2

0.1

150 250

0.1 4

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10 100 1000 10000

-50

-100

-150

-200

-250

InputFrequency-kHz

Phase-degrees

FastMode

MediumMode

SlowMode

140

120

100

-20

-40

-60

-80

0.001 0.01 0.1

10 100 1000 10000

InputFrequency-kHz

Gain=dB

FastMode

MediumMode

SlowMode

O/P(OAx)

Max

0.2V AV

AVCC-0.2V

OUT

Min

Load

OAx

O/P(OAx)

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Figure 5-34. OAx Output Resistance Tests

5.41 Operational Amplifier OA, Dynamic Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Fast Mode 1.2

SR Slew rate Medium Mode 0.8 V/µs

Slow Mode 0.3

Open-loop voltage gain 100 dB

φm Phase margin CL= 50 pF 60 deg

Gain margin CL= 50 pF 20 dB

GBW (see Figure 5-35 and 2.2 V, 3 V MHz

Gain-bandwidth product

Figure 5-36)

t t

Enable time on ton, Noninverting, Gain = 1 2.2 V, 3 V 10 20 µs

en(on)

Enable time off 2.2 V, 3 V 1 µs

en(off)

Noninverting, Fast Mode, RL= 47 kΩ, CL= 50 pF Noninverting, Medium Mode, RL= 300 kΩ, CL= 50 pF

Noninverting, Slow Mode, RL= 300 kΩ, CL= 50 pF

MIN TYP MAX UNIT

2.2

1.4

0.5

5.42 Operational Amplifier OA, Typical Characteristics

Figure 5-35. Typical Open-Loop Gain vs Frequency

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Figure 5-36. Typical Phase vs Frequency

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5.43 Operational Amplifier OA Feedback Network, Noninverting Amplifier Mode (OAFCx = 4)

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

OAFBRx = 0 0.996 1.00 1.002 OAFBRx = 1 1.329 1.334 1.340 OAFBRx = 2 1.987 2.001 2.016

G Gain 2.2 V, 3 V

OAFBRx = 3 2.64 2.667 2.70 OAFBRx = 4 3.93 4.00 4.06 OAFBRx = 5 5.22 5.33 5.43 OAFBRx = 6 7.76 7.97 8.18 OAFBRx = 7 15.0 15.8 16.6

THD Total harmonic distortion and nonlinearity All gains dB

Settle

Settling time

(1)

All power modes 2.2 V, 3 V 7 12 µs

2.2 V –60 3 V –70

(1) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The

settling time of the amplifier itself might be faster.

MIN TYP MAX UNIT

5.44 Operational Amplifier OA Feedback Network, Inverting Amplifier Mode (OAFCx = 6)

(1)

over recommended operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

OAFBRx = 1 –0.371 –0.335 –0.298 OAFBRx = 2 –1.031 –1.002 –0.972 OAFBRx = 3 –1.727 –1.668 –1.609

G Gain OAFBRx = 4 2.2 V, 3 V –3.142 –3.00 –2.856

OAFBRx = 5 –4.581 –4.33 –4.073 OAFBRx = 6 –7.529 –6.97 –6.379 OAFBRx = 7 –17.040 –14.8 –12.279

THD Total harmonic distortion and nonlinearity All gains dB

Settle

Settling time

(2)

All power modes 2.2 V, 3 V 7 12 µs

2.2 V –60 3 V –70

(1) This includes the two OA configuration "inverting amplifier with input buffer". Both OAs need to be set to the same power mode, OAPMx. (2) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The

settling time of the amplifier itself might be faster.

MIN TYP MAX UNIT

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5.45 Flash Memory (FG461x Devices Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER V

CC(PGM/ERASE)

FTG

PGM

ERASE

GMERASE

CPT

CMErase

Program and erase supply voltage 2.7 3.6 V Flash timing generator frequency 257 476 kHz Supply current from DVCC during program 2.7 V, 3.6 V 3 5 mA Supply current from DVCC during erase Supply current from DVCC during global mass erase Cumulative program time Cumulative mass erase time 2.7 V, 3.6 V 20 ms Program and erase endurance 10

Retention

Word

Block, 0

Block, 1-63

Block, End

Mass Erase

Global Mass Erase

Seg Erase

Data retention duration TJ= 25°C 100 years Word or byte program time 30 Block program time for 1st byte or word 25 Block program time for each additional byte or word 18 Block program end-sequence wait time Mass erase time 10593 Global mass erase time 10593 Segment erase time 4819

(1) Lower 64KB or upper 64KB flash memory erased. (2) All flash memory erased. (3) The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write

feature is used.

(4) These values are hardwired into the flash controller state machine (t

TEST

CONDITIONS

(1) (2) (3)

(4)

= 1/f

FTG

MIN TYP MAX UNIT

2.7 V, 3.6 V 3 7 mA

2.7 V, 3.6 V 6 14 mA

2.7 V, 3.6 V 10 ms

cycles

6 t

FTG

5.46 JTAG Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

TCK

Internal

(1) f (2) TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.

5.47 JTAG Fuse

TCK input frequency

Internal pullup resistance on TMS, TCK, TDI/TCLK

may be restricted to meet the timing requirements of the module selected.

TCK

(1)

(2)

2.2 V 0 5 3 V 0 10

2.2 V, 3 V 25 60 90 kΩ

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

CC(FB)

(1) After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to

bypass mode.

Supply voltage during fuse-blow condition TA= 25°C 2.5 V Voltage level on TDI/TCLK for fuse-blow (FG461x) 6 7 V Supply current into TDI/TCLK during fuse blow 100 mA Time to blow fuse 1 ms

MIN TYP MAX UNIT

MHz

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General-PurposeRegister

ProgramCounter

StackPointer

StatusRegister

ConstantGenerator

General-PurposeRegister

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-PurposeRegister

R10

R11

General-PurposeRegister

R14

R15

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6 Detailed Description

6.1 CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

The MSP430xG461x device family uses the MSP430X CPU and is completely backwards compatible with the MSP430 CPU. For a complete description of the MSP430X CPU, refer to the MSP430x4xx Family User’s Guide (SLAU056).

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6.2 Instruction Set

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 6-1 shows examples of the three types of instruction formats; the address modes are listed in Table 6-2.

Table 6-1. Instruction Word Formats

FORMAT EXAMPLE OPERATION

Dual operands, source-destination ADD R4,R5 R4 + R5 → R5 Single operands, destination only CALL R8 PC→ (TOS), R8 → PC Relative jump, un/conditional JNE Jump-on-equal bit = 0

Table 6-2. Address Mode Descriptions

ADDRESS MODE S

Indexed • • MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)→ M(6+R6)

Symbolic (PC relative) • • MOV EDE,TONI M(EDE) → M(TONI)

Absolute • • MOV & MEM, & TCDAT M(MEM) → M(TCDAT)

Indirect • MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)

Indirect autoincrement • MOV @Rn+,Rm MOV @R10+,R11

Immediate • MOV #X,TONI MOV #45,TONI #45 → M(TONI)

(1) NOTE: S = source D = destination

(1)

SYNTAX EXAMPLE OPERATION

M(R10) → R11 R10 + 2→ R10

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6.3 Operating Modes

These devices have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM) – All clocks are active

• Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active. MCLK is disabled – FLL+ loop control remains active

• Low-power mode 1 (LPM1) – CPU is disabled – FLL+ loop control is disabled – ACLK and SMCLK remain active. MCLK is disabled

• Low-power mode 2 (LPM2) – CPU is disabled – MCLK, FLL+ loop control and DCOCLK are disabled – DCO DC generator remains enabled – ACLK remains active

• Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL+ loop control, and DCOCLK are disabled – DCO DC generator is disabled – ACLK remains active

• Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL+ loop control, and DCOCLK are disabled – DCO DC generator is disabled – Crystal oscillator is stopped

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6.4 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6-3. Interrupt Sources, Flags, and Vectors

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

SYSTEM WORD

INTERRUPT ADDRESS

Power-Up

External Reset WDTIFG

Watchdog KEYV

(1) (2)

Reset 0FFFEh 31, highest

Flash Memory

TBIFG

(1) (3)

(1) (4)(2)

(1)(4)

(Non)maskable (Non)maskable 0FFFCh 30 (Non)maskable

(4)

Maskable 0FFFAh 29

NMI NMIIFG

Oscillator Fault OFIFG

Flash Memory Access Violation ACCVIFG

Timer_B7 TBCCR0 CCIFG0 Timer_B7 Maskable 0FFF8h 28

TBCCR1 CCIFG1 to TBCCR6 CCIFG6,

Comparator_A CAIFG Maskable 0FFF6h 27

Watchdog Timer+ WDTIFG Maskable 0FFF4h 26

(4)

(1) (4)

(1) (1)

Maskable 0FFF2h 25 Maskable 0FFF0h 24 Maskable 0FFEEh 23 Maskable 0FFECh 22

Maskable 0FFE8h 20

USCI_A0, USCI_B0 Receive UCA0RXIFG, UCB0RXIFG

USCI_A0, USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG

ADC12 ADC12IFG

(1) (4)

Timer_A3 TACCR0 CCIFG0 Timer_A3 Maskable 0FFEAh 21

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG

(1) (4)

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7

USART1 Receive URXIFG1 Maskable 0FFE6h 19 USART1 Transmit UTXIFG1 Maskable 0FFE4h 18

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7

(1) (4)

Maskable 0FFE2h 17

Basic Timer 1, RTC BTIFG Maskable 0FFE0h 16

(1) (4)

Maskable 0FFDEh 15 Maskable 0FFDCh 14

DMA DMA0IFG, DMA1IFG, DMA2IFG

DAC12 DAC12.0IFG, DAC12.1IFG

0FFDAh 13

Reserved Reserved

(5)

⋮ ⋮

0FFC0h 0, lowest

(1) Multiple source flags (2) Access and key violations, KEYV and ACCVIFG, only applicable to FG devices. (3) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (4) Interrupt flags are located in the module. (5) The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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7 6 5 4 03 2 1

Address

01h

rw*0

BTIE UTXIE1 URXIE1

rw*0 rw*0

UCA0TXIE UCA0RXIE

rw*0 rw*0

UCB0TXIE UCB0RXIE

rw*0 rw*0

7 6 5 4 0

OFIE WDTIE

3 2 1

rw*0 rw*0 rw*0

Address

0h ACCVIE NMIIE

rw*0

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6.5 Special Function Registers (SFRs)

The MSP430 SFRs are in the lowest address space and are organized as byte mode registers. SFRs should be accessed with byte instructions.

Legend

rw Bit can be read and written. rw-0, rw-1 Bit can be read and written. It is Reset or Set by PUC. rw-(0), rw-(1) Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device

6.5.1 Interrupt Enable 1 and 2

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected.

Active if watchdog timer is configured as a general-purpose timer. OFIE Oscillator fault-interrupt enable NMIIE Nonmaskable interrupt enable ACCVIE Flash access violation interrupt enable

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UCA0RXIE USCI_A0 receive-interrupt enable UCA0TXIE USCI_A0 transmit-interrupt enable UCB0RXIE USCI_B0 receive-interrupt enable UCB0TXIE USCI_B0 transmit-interrupt enable URXIE1 USART1 UART and SPI receive-interrupt enable UTXIE1 USART1 UART and SPI transmit-interrupt enable BTIE Basic timer interrupt enable

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7 6 5 4 0

UTXE1

3 2 1

rw*0 rw*0

Address

05h

URXE1

USPIE1

7 6 5 4 03 2 1

Address

04h

7 6 5 4 03 2 1

Address

03h

BTIFG

rw*0

UTXIFG1 URXIFG1

rw*1 rw*0

UCA0TXIFG UCA0RXIFG

rw*0 rw*0

UCB0TXIFG UCB0RXIFG

rw*0 rw*0

7 6 5 4 0

OFIFG WDTIFG

3 2 1

rw*0 rw*1 rw*(0)

Address

02h NMIIFG

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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6.5.2 Interrupt Flag Register 1 and 2

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation

Reset on VCCpower-on or a reset condition at the RST/NMI pin in reset mode OFIFG Flag set on oscillator fault NMIIFG Set by the RST/NMI pin

UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag URXIFG0 USART1: UART and SPI receive flag UTXIFG0 USART1: UART and SPI transmit flag BTIFG Basic timer flag

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6.5.3 Module Enable Registers 1 and 2

URXE1 USART1: UART mode receive enable UTXE1 USART1: UART mode transmit enable USPIE1 USART1: SPI mode transmit and receive enable

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6.6 Memory Organization

Table 6-4 summarizes the memory organization for the FG461x devices, and Table 6-5 summarizes the

memory organization for the CG461x devices.

Table 6-4. MSP430FG461x Memory Organization

MSP430FG4616 MSP430FG4617 MSP430FG4618 MSP430FG4619

Memory Size 92KB 92KB 116KB 120KB Main: interrupt vector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main: code memory Flash 018FFFh-002100h 019FFFh-003100h 01FFFFh-003100h 01FFFFh-002100h

RAM Total Size 4KB 8KB 8KB 4KB

Extended Size 2KB 6KB 6KB 2KB

Mirrored Size 2KB 2KB 2KB 2KB

Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte

Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h 010FFh-01000h

Boot memory Size 1KB 1KB 1KB 1KB

ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h

RAM Size 2KB 2KB 2KB 2KB (Mirrored at 018FFh- 09FFh-0200h 09FFh-0200h 09FFh-0200h 09FFh-0200h 01100h)

Peripherals 16 bit 01FFh-0100h 01FFh-0100h 01FFh-0100h 01FFh-0100h

8 bit 0FFh-010h 0FFh-010h 0FFh-010h 0FFh-010h

8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h 0Fh-00h

020FFh-01100h 030FFh-01100h 030FFh-01100h 020FFh-01100h

020FFh-01900h 030FFh-01900h 030FFh-01900h 020FFh-01900h

018FFh-01100h 018FFh-01100h 018FFh-01100h 018FFh-01100h

Table 6-5. MSP430CG461x Memory Organization

MSP430CG4616 MSP430CG4617 MSP430CG4618 MSP430CG4619

Memory Size 92KB 92KB 116KB 120KB Main: interrupt vector ROM 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main: code memory ROM 018FFFh-002100h 019FFFh-003100h 01FFFFh-003100h 01FFFFh-002100h

RAM Total Size 4KB 8KB 8KB 4KB

Extended Size 2KB 6KB 6KB 2KB

Mirrored Size 2KB 2KB 2KB 2KB

Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte

ROM 010FFh-01000h 010FFh-01000h 010FFh-01000h 010FFh-01000h

Boot memory Size 1KB 1KB 1KB 1KB (Optional on CG) ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h

RAM Size 2KB 2KB 2KB 2KB (Mirrored at 018FFh- 09FFh-0200h 09FFh-0200h 09FFh-0200h 09FFh-0200h 01100h)

Peripherals 16 bit 01FFh-0100h 01FFh-0100h 01FFh-0100h 01FFh-0100h

8 bit 0FFh-010h 0FFh-010h 0FFh-010h 0FFh-010h

8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h 0Fh-00h

020FFh-01100h 030FFh-01100h 030FFh-01100h 020FFh-01100h

020FFh-01900h 030FFh-01900h 030FFh-01900h 020FFh-01900h

018FFh-01100h 018FFh-01100h 018FFh-01100h 018FFh-01100h

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6.7 Bootstrap Loader (BSL)

The BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MCU memory through the BSL is protected by user-defined password. A bootstrap loader security key is provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader (SLAA089).

any other value BSL enabled

BSL FUNCTION PZ/ZQW PACKAGE PINS

Data Transmit 87/A7 – P1.0 Data Receiver 86/E7 – P1.1

6.8 Flash Memory

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

BSLKEY DESCRIPTION

00000h

0AA55h BSL disabled

Erasure of flash disabled if an invalid password is supplied

SLAS508J –APRIL 2006–REVISED JUNE 2015

The flash memory can be programmed by the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A and B can be erased individually, or as a group with segments 0-n. Segments A and B are also called information memory.

• New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory before the first use.

6.9 Peripherals

Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide.

6.9.1 DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.

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6.9.2 Oscillator and System Clock

The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal

• Main clock (MCLK), the system clock used by the CPU

• Submain clock (SMCLK), the subsystem clock used by the peripheral modules

• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

6.9.3 Brownout, Supply Voltage Supervisor (SVS)

The brownout circuit provides the proper internal reset signal to the device during power-on and power-off. The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset).

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The CPU begins code execution after the brownout circuit releases the device reset. However, VCCmay not have ramped to V

CC(min)

changed until VCCreaches V reaches V

CC(min)

at that time. The user must make sure the default FLL+ settings are not

. If desired, the SVS circuit can be used to determine when V

CC(min)

6.9.4 Digital I/O

There are ten 8-bit I/O ports implemented—ports P1 through P10:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.

• Read and write access to port-control registers is supported by all instructions

• Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB, respectively.

6.9.5 Basic Timer1 and Real-Time Clock

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated realtime clock (RTC). An internal calendar compensates for months with less than 31 days and includes leapyear correction.

6.9.6 LCD_A Drive With Regulated Charge Pump

The LCD_A driver generates the segment and common signals required to drive a segment LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.

6.9.7 Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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6.9.8 Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols like UART, enhanced UART with automatic baudrate detection, and IrDA.

The USCI_A0 module provides support for SPI (3-pin or 4-pin), UART, enhanced UART and IrDA. The USCI_B0 module provides support for SPI (3-pin or 4-pin) and I2C.

6.9.9 USART1

The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for serial data communication. The USART supports synchronous SPI (3-pin or 4-pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.

6.9.10 Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16, 16×8, 8×16, and 8×8 bit operations. The module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.

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6.9.11 Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-6. Timer_A3 Signal Connections

INPUT PIN NUMBER

PZ/ZQW PZ/ZQW

82/B9 - P1.5 TACLK TACLK

82/B9 - P1.5 TACLK INCLK 87/A7 - P1.0 TA0 CCI0A 87/A7 - P1.0 86/E7 - P1.1 TA0 CCI0B

85/D7 - P1.2 TA1 CCI1A 85/D7 - P1.2

79/A10 - P2.0 TA2 CCI2A 79/A10 - P2.0

DEVICE INPUT MODULE INPUT MODULE OUT

SIGNAL NAME SIGNAL

ACLK ACLK

SMCLK SMCLK

CAOUT (internal) CCI1B ADC12 (internal)

ACLK (internal) CCI2B

GND

MODULE BLOCK

Timer NA

CCR0 TA0

CCR1 TA1

CCR2 TA2

OUTPUT PIN

NUMBER

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6.9.12 Timer_B7

Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 6-7. Timer_B7 Signal Connections

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INPUT PIN NUMBER

PZ/ZQW PZ/ZQW

DEVICE INPUT MODULE INPUT MODULE OUT

SIGNAL NAME SIGNAL

MODULE BLOCK

OUTPUT PIN

NUMBER

83/B8 - P1.4 TBCLK TBCLK

ACLK ACLK

SMCLK SMCLK

Timer NA

83/B8 - P1.4 TBCLK INCLK 78/D8 - P2.1 TB0 CCI0A 78/D8 - P2.1 78/D8 - P2.1 TB0 CCI0B ADC12 (internal)

DV DV

GND

CCR0CCR0 TB0TB0

77/E8 - P2.2 TB1 CCI1A 77/E8 - P2.2 77/E8 - P2.2 TB1 CCI1B ADC12 (internal)

DV DV

GND

CCR1 TB1

76/A11 - P2.3 TB2 CCI2A 76/A11 - P2.3 76/A11 - P2.3 TB2 CCI2B

DV DV

GND

CCR2 TB2

67/E12 - P3.4 TB3 CCI3A 67/E12 - P3.4 67/E12 - P3.4 TB3 CCI3B

DV DV

GND

CCR3 TB3

66/G9 - P3.5 TB4 CCI4A 66/G9 - P3.5 66/G9 - P3.5 TB4 CCI4B

DV DV

GND

CCR4 TB4

65/F11 - P3.6 TB5 CCI5A 65/F11 - P3.6 65/F11 - P3.6 TB5 CCI5B

DV DV

GND

CCR5 TB5

64/F12 - P3.7 TB6 CCI6A 64/F12 - P3.7

ACLK (internal) CCI6B

DV DV

GND

CCR6 TB6

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6.9.13 Comparator_A

The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

6.9.14 ADC12

The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

6.9.15 DAC12

The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 can be used in 8-bit or 12-bit mode and can be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.

6.9.16 OA

The MSP430xG461x has three configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning before analog-todigital conversion.

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Table 6-8. OA Signal Connections

INPUT PIN OUTPUT PIN

NUMBER NUMBER

PZ PZ

95 - P6.0 OA0I0 OA0I0 OA0O 96 - P6.1 97 - P6.2 OA0I1 OA0I1 OA0O ADC12 (internal)

3- P6.4 OA1I0 OA1I0 OA1O 2- P6.3

13 - P5.0 OA1I1 OA1I1 OA1O 13- P5.0

5- P6.6 OA2I0 OA2I0 OA2O 4- P6.5

14 - P10.7 OA2I1 OA2I1 OA2O 14 - P10.7

DEVICE INPUT MODULE INPUT MODULE DEVICE OUTPUT

SIGNAL NAME OUTPUT SIGNAL SIGNAL

DAC12_0OUT

(internal)

DAC12_1OUT

(internal)

DAC12_0OUT

(internal)

DAC12_1OUT

(internal)

DAC12_0OUT

(internal)

DAC12_1OUT

(internal)

DAC12_0OUT

DAC12_1OUT

DAC12_0OUT OA1O ADC12 (internal)

DAC12_1OUT

DAC12_0OUT OA2O ADC12 (internal)

DAC12_1OUT

MODULE BLOCK

OA0 OA0OUT

OA1 OA1OUT

OA2 OA2OUT

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6.9.17 Peripheral File Map

Table 6-9 lists the registers and addresses for peripherals with word access. Table 6-10 lists the registers

and addresses for peripherals with byte access.

Table 6-9. Peripherals With Word Access

MODULE REGISTER NAME ACRONYM ADDRESS Watchdog+ Watchdog timer control WDTCTL 0120h Timer_B7 Capture/compare register 6 TBCCR6 019Eh

Capture/compare register 5 TBCCR5 019Ch Capture/compare register 4 TBCCR4 019Ah Capture/compare register 3 TBCCR3 0198h Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control 6 TBCCTL6 018Eh Capture/compare control 5 TBCCTL5 018Ch Capture/compare control 4 TBCCTL4 018Ah Capture/compare control 3 TBCCTL3 0188h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh

Timer_A3 Capture/compare register 2 TACCR2 0176h

Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh

Hardware Multiplier Sum extend SUMEXT 013Eh

Result high word RESHI 013Ch Result low word RESLO 013Ah Second operand OP2 0138h Multiply signed + accumulate/operand1 MACS 0136h Multiply + accumulate/operand1 MAC 0134h Multiply signed/operand1 MPYS 0132h Multiply unsigned/operand1 MPY 0130h

Flash Flash control 3 FCTL3 012Ch (FG devices only) Flash control 2 FCTL2 012Ah

Flash control 1 FCTL1 0128h

DMA DMA module control 0 DMACTL0 0122h

DMA module control 1 DMACTL1 0124h DMA interrupt vector DMAIV 0126h

DMA Channel 0 DMA channel 0 control DMA0CTL 01D0h

DMA channel 0 source address DMA0SA 01D2h DMA channel 0 destination address DMA0DA 01D6h DMA channel 0 transfer size DMA0SZ 01DAh

DMA Channel 1 DMA channel 1 control DMA1CTL 01DCh

DMA channel 1 source address DMA1SA 01DEh DMA channel 1 destination address DMA1DA 01E2h DMA channel 1 transfer size DMA1SZ 01E6h

DMA Channel 2 DMA channel 2 control DMA2CTL 01E8h

DMA channel 2 source address DMA2SA 01EAh DMA channel 2 destination address DMA2DA 01EEh DMA channel 2 transfer size DMA2SZ 01F2h

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MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-9. Peripherals With Word Access (continued)

MODULE REGISTER NAME ACRONYM ADDRESS ADC12 Conversion memory 15 ADC12MEM15 015Eh

See also Table 6-10 Conversion memory 14 ADC12MEM14 015Ch

DAC12 DAC12_1 data DAC12_1DAT 01CAh

Port PA Port PA selection PASEL 03Eh

Port PB Port PB selection PBSEL 00Eh

Conversion memory 13 ADC12MEM13 015Ah Conversion memory 12 ADC12MEM12 0158h Conversion memory 11 ADC12MEM11 0156h Conversion memory 10 ADC12MEM10 0154h Conversion memory 9 ADC12MEM9 0152h Conversion memory 8 ADC12MEM8 0150h Conversion memory 7 ADC12MEM7 014Eh Conversion memory 6 ADC12MEM6 014Ch Conversion memory 5 ADC12MEM5 014Ah Conversion memory 4 ADC12MEM4 0148h Conversion memory 3 ADC12MEM3 0146h Conversion memory 2 ADC12MEM2 0144h Conversion memory 1 ADC12MEM1 0142h Conversion memory 0 ADC12MEM0 0140h Interrupt-vector-word register ADC12IV 01A8h Inerrupt-enable register ADC12IE 01A6h Inerrupt-flag register ADC12IFG 01A4h Control register 1 ADC12CTL1 01A2h Control register 0 ADC12CTL0 01A0h

DAC12_1 control DAC12_1CTL 01C2h DAC12_0 data DAC12_0DAT 01C8h DAC12_0 control DAC12_0CTL 01C0h

Port PA direction PADIR 03Ch Port PA output PAOUT 03Ah Port PA input PAIN 038h

Port PB direction PBDIR 00Ch Port PB output PBOUT 00Ah Port PB input PBIN 008h

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MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-10. Peripherals With Byte Access

MODULE REGISTER NAME ACRONYM ADDRESS OA2 Operational Amplifier 2 control register 1 OA2CTL1 0C5h

Operational Amplifier 2 control register 0 OA2CTL0 0C4h

OA1 Operational Amplifier 1 control register 1 OA1CTL1 0C3h

Operational Amplifier 1 control register 0 OA1CTL0 0C2h

OA0 Operational Amplifier 0 control register 1 OA0CTL1 0C1h

Operational Amplifier 0 control register 0 OA0CTL0 0C0h

LCD_A LCD Voltage Control 1 LCDAVCTL1 0AFh

LCD Voltage Control 0 LCDAVCTL0 0AEh LCD Voltage Port Control 1 LCDAPCTL1 0ADh LCD Voltage Port Control 0 LCDAPCTL0 0ACh LCD memory 20 LCDM20 0A4h : : : LCD memory 16 LCDM16 0A0h LCD memory 15 LCDM15 09Fh : : : LCD memory 1 LCDM1 091h LCD control and mode LCDCTL 090h

ADC12 ADC memory-control register 15 ADC12MCTL15 08Fh (Memory control registers ADC memory-control register 14 ADC12MCTL14 08Eh require byte access) ADC memory-control register 13 ADC12MCTL13 08Dh

ADC memory-control register 12 ADC12MCTL12 08Ch ADC memory-control register 11 ADC12MCTL11 08Bh ADC memory-control register 10 ADC12MCTL10 08Ah ADC memory-control register 9 ADC12MCTL9 089h ADC memory-control register 8 ADC12MCTL8 088h ADC memory-control register 7 ADC12MCTL7 087h ADC memory-control register 6 ADC12MCTL6 086h ADC memory-control register 5 ADC12MCTL5 085h ADC memory-control register 4 ADC12MCTL4 084h ADC memory-control register 3 ADC12MCTL3 083h ADC memory-control register 2 ADC12MCTL2 082h ADC memory-control register 1 ADC12MCTL1 081h ADC memory-control register 0 ADC12MCTL0 080h

USART1 Transmit buffer U1TXBUF 07Fh

Receive buffer U1RXBUF 07Eh Baud rate U1BR1 07Dh Baud rate U1BR0 07Ch Modulation control U1MCTL 07Bh Receive control U1RCTL 07Ah Transmit control U1TCTL 079h USART control U1CTL 078h

USCI USCI I2C Slave Address UCBI2CSA 011Ah

USCI I2C Own Address UCBI2COA 0118h USCI Synchronous Transmit Buffer UCBTXBUF 06Fh USCI Synchronous Receive Buffer UCBRXBUF 06Eh USCI Synchronous Status UCBSTAT 06Dh USCI I2C Interrupt Enable UCBI2CIE 06Ch USCI Synchronous Bit Rate 1 UCBBR1 06Bh USCI Synchronous Bit Rate 0 UCBBR0 06Ah USCI Synchronous Control 1 UCBCTL1 069h USCI Synchronous Control 0 UCBCTL0 068h USCI Transmit Buffer UCATXBUF 067h USCI Receive Buffer UCARXBUF 066h USCI Status UCASTAT 065h USCI Modulation Control UCAMCTL 064h USCI Baud Rate 1 UCABR1 063h USCI Baud Rate 0 UCABR0 062h USCI Control 1 UCACTL1 061h USCI Control 0 UCACTL0 060h USCI IrDA Receive Control UCAIRRCTL 05Fh USCI IrDA Transmit Control UCAIRTCTL 05Eh USCI LIN Control UCAABCTL 05Dh

Comparator_A Comparator_A port disable CAPD 05Bh

Comparator_A control 2 CACTL2 05Ah Comparator_A control 1 CACTL1 059h

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MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-10. Peripherals With Byte Access (continued)

MODULE REGISTER NAME ACRONYM ADDRESS BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h FLL+Clock FLL+ Control 1 FLL_CTL1 054h

RTC Real Time Clock Year High Byte RTCYEARH 04Fh (Basic Timer 1) Real Time Clock Year Low Byte RTCYEARL 04Eh

Port P10 Port P10 selection P10SEL 00Fh

Port P9 Port P9 selection P9SEL 00Eh

Port P8 Port P8 selection P8SEL 03Fh

Port P7 Port P7 selection P7SEL 03Eh

Port P6 Port P6 selection P6SEL 037h

Port P5 Port P5 selection P5SEL 033h

Port P4 Port P4 selection P4SEL 01Fh

Port P3 Port P3 selection P3SEL 01Bh

Port P2 Port P2 selection P2SEL 02Eh

FLL+ Control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h

Real Time Clock Month RTCMON 04Dh Real Time Clock Day of Month RTCDAY 04Ch Basic Timer1 Counter 2 BTCNT2 047h Basic Timer1 Counter 1 BTCNT1 046h Real Time Counter 4 RTCNT4 045h (Real Time Clock Day of Week) (RTCDOW) 044h Real Time Counter 3 RTCNT3 043h (Real Time Clock Hour) (RTCHOUR) 042h Real Time Counter 2 RTCNT2 041h (Real Time Clock Minute) (RTCMIN) 040h Real Time Counter 1 RTCNT1 (Real Time Clock Second) (RTCSEC) Real Time Clock Control RTCCTL Basic Timer1 Control BTCTL

Port P10 direction P10DIR 00Dh Port P10 output P10OUT 00Bh Port P10 input P10IN 009h

Port P9 direction P9DIR 00Ch Port P9 output P9OUT 00Ah Port P9 input P9IN 008h

Port P8 direction P8DIR 03Dh Port P8 output P8OUT 03Bh Port P8 input P8IN 039h

Port P7 direction P7DIR 03Ch Port P7 output P7OUT 03Ah Port P7 input P7IN 038h

Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h

Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h

Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch

Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h

Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-10. Peripherals With Byte Access (continued)

MODULE REGISTER NAME ACRONYM ADDRESS Port P1 Port P1 selection P1SEL 026h

Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h

Special functions SFR module enable 2 ME2 005h

SFR module enable 1 ME1 004h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

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Bus

Keeper

Direction 0: Input 1: Output

P 1SEL .x

P1DIR .x

P1IN .x

PadLogic

P1IRQ .x

ModuleXIN

ModuleXOUT

P1OUT .x

Note : x = 0,1,2,3,4,5

P1.0/TA 0 P1.1/TA 0/MCLK P1.2/TA 1 P1.3/TBOUTH /SVSOUT P1.4/TBCLK /SMCLK P1.5/TACLK /ACLK

Interrupt

Edge

Select

Set

P1SEL .x

P 1IES .x

P1IFG .x

P 1IE .x

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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6.10 Input/Output Schematics

6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-11. Port P1 (P1.0 to P1.5) Pin Functions

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PIN NAME (P1.x) x FUNCTION

P1.0/TA0 0 P1.0 (I/O) I: 0; O: 1 0

Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1

P1.1/TA0/MCLK 1 P1.1 (I/O) I: 0; O: 1 0

Timer_A3.CCI0B 0 1 MCLK 1 1

P1.2/TA1 2 P1.2 (I/O) I: 0; O: 1 0

Timer_A3.CCI1A 0 1 Timer_A3.TA1 1 1

P1.3/TBOUTH/SVSOUT 3 P1.3 (I/O) I: 0; O: 1 0

Timer_B7.TBOUTH 0 1 SVSOUT 1 1

P1.4/TBCLK/SMCLK 4 P1.4 (I/O) I: 0; O: 1 0

Timer_B7.TBCLK 0 1 SMCLK 1 1

P1.5/TACLK/ACLK 5 P1.5 (I/O) I: 0; O: 1 0

Timer_A3.TACLK 0 1 ACLK 1 1

CONTROL BITS OR SIGNALS

P1DIR.x P1SEL.x

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Comp_A

Bus

Keeper

Direction 0: Input 1: Output

P 1SEL .x

P1DIR .x

P1IN .x

PadLogic

CAPD .x

P1IRQ .x

ModuleXIN

ModuleXOUT

P1OUT .x

Note : x = 6,7

P1.6/CA 0 P1.7/CA 1

Interrupt

Edge

Select

Set

P1SEL .x

P1IES .x

P1IFG .x

P 1IE .x

P2CA 0

CA0

CA1

P2CA 1

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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6.10.2 Port P1, P1.6, P1.7, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-12. Port P1 (P1.6 and P1.7) Pin Functions

PIN NAME (P1.x) x FUNCTION

P1.6/CA0 6 P1.6 (I/O) 0 I: 0; O: 1 0

P1.7/CA1 7 P1.7 (I/O) 0 I: 0; O: 1 0

(1) X = don't care

CA0 1 X X

CA1 1 X X

CONTROL BITS OR SIGNALS

CAPD.x P1DIR.x P1SEL.x

(1)

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Bus

Keeper

Direction 0: Input 1: Output

P 2SEL .x

P2DIR .x

P2IN .x

PadLogic

TBOUTH

P2IRQ .x

ModuleXIN

ModuleXOUT

P2OUT .x

Note : x = 0,1,2,3,6,7

P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.3/TB2 P2.6/CAOUT P2.7/ADC 12CLK /DMAE 0

Interrupt

Edge

Select

Set

P2SEL .x

P 2IES .x

P2IFG .x

P 2IE.x

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.3 Port P2, P2.0 to P2.3, P2.6 to P2.7, Input/Output With Schmitt Trigger

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MSP430CG4618 MSP430CG4617 MSP430CG4616

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MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-13. Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) Pin Functions

PIN NAME (P2.x) x FUNCTION

CONTROL BITS OR SIGNALS

P2DIR.x P2SEL.x

P2.0/TA2 0 P2.0 (I/O) I: 0; O: 1 0

Timer_A3.CCI2A 0 1 Timer_A3.TA2 1 1

P2.1/TB0 1 P2.1 (I/O) I: 0; O: 1 0

Timer_B7.CCI0A and Timer_B7.CCI0B 0 1 Timer_B7.TB0

(1)

1 1

P2.2/TB1 2 P2.2 (I/O) I: 0; O: 1 0

Timer_B7.CCI1A and Timer_B7.CCI1B 0 1 Timer_B7.TB1

(1)

1 1

P2.3/TB3 3 P2.3 (I/O) I: 0; O: 1 0

Timer_B7.CCI2A and Timer_B7.CCI2B 0 1 Timer_B7.TB3

(1)

1 1

P2.6/CAOUT 6 P2.6 (I/O) I: 0; O: 1 0

CAOUT 1 1

P2.7/ADC12CLK/DMAE0 7 P2.7 (I/O) I: 0; O: 1 0

ADC12CLK 1 1 DMAE0 0 1

(1) Setting TBOUTH causes all Timer_B outputs to be set to high impedance.

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Bus

Keeper

Direction 0: Input 1: Output

P2SEL .x

P 2DIR .x

P2IN .x

PadLogic

P2IRQ .x

ModuleXIN

ModuleXOUT

P2OUT .x

Note: x = 4,5

P2.4/UCA 0TXD P2.5/UCA 0RXD

Interrupt

Edge

Select

Set

P2SEL .x

P2IES .x

P2IFG .x

P2IE.x

Directioncontrol

fromModuleX

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.4 Port P2, P2.4 to P2.5, Input/Output With Schmitt Trigger

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(1) X = don't care (2) When in USCI mode, P2.4 is set to output, P2.5 is set to input.

Table 6-14. Port P2 (P2.4 and P2.5) Pin Functions

PIN NAME (P2.x) x FUNCTION

P2.4/UCA0TXD 4

P2.5/UCA0RXD 5

P2.4 (I/O) I: 0; O: 1 0 USCI_A0.UCA0TXD P2.5 (I/O) I: 0; O: 1 0 USCI_A0.UCA0RXD

(2)

CONTROL BITS OR

SIGNALS

P2DIR.x P2SEL.x

X 1

(1)

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Bus

Keeper

Direction 0: Input 1: Output

P 3SEL .x

P3DIR .x

P3IN .x

PadLogic

ModuleXIN

ModuleXOUT

P3OUT .x

Note: x = 0,1,2,3

P 3.0/UCB 0STE P 3.1/UCB 0SIMO /UCB 0SDA P 3.2/UCB 0SOMI /UCB 0SCL P 3.3/UCB 0CLK

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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6.10.5 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-15. Port P3 (P3.0 to P3.3) Pin Functions

CONTROL BITS OR

PIN NAME (P3.x) x FUNCTION

P3.0/UCB0STE 0 P3.0 (I/O) I: 0; O: 1 0

UCB0STE

P3.1/UCB0SIMO/UCB0SDA 1 P3.1 (I/O) I: 0; O: 1 0

P3.2/UCB0SOMI/UCB0SCL 2 P3.2 (I/O) I: 0; O: 1 0

P3.3/UCB0CLK 3 P3.3 (I/O) I: 0; O: 1 0

(1) X = don't care (2) The pin direction is controlled by the USCI module. (3) If the I2C functionality is selected the output drives only the logical 0 to VSSlevel.

UCB0SIMO/UCB0SDA

UCB0SOMI/UCB0SCL

UCB0CLK

(2)

(2) (3)

(2)

SIGNALS

P3DIR.x P3SEL.x

X 1

(1)

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Bus

Keeper

Direction 0: Input 1: Output

P 3SEL .x

P3DIR .x

P3IN .x

PadLogic

TBOUTH

ModuleXIN

ModuleXOUT

P3OUT .x

Note: x = 4, 5,6,7

P3.4/TB 3 P3.5/TB 4 P3.6/TB 5 P3.7/TB 6

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.6 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger

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Table 6-16. Port P3 (P3.4 to P3.7) Pin Functions

PIN NAME (P3.x) x FUNCTION

P3.4/TB3 4 P3.4 (I/O) I: 0; O: 1 0

P3.5/TB4 5 P3.5 (I/O) I: 0; O: 1 0

P3.6/TB5 6 P3.6 (I/O) I: 0; O: 1 0

P3.7/TB6 7 P3.7 (I/O) I: 0; O: 1 0

(1) Setting TBOUTH causes all Timer_B outputs to be set to high impedance.

Timer_B7.CCI3A and Timer_B7.CCI3B 0 1 Timer_B7.TB3

Timer_B7.CCI4A and Timer_B7.CCI4B 0 1 Timer_B7.TB4

Timer_B7.CCI5A and Timer_B7.CCI5B 0 1 Timer_B7.TB5

Timer_B7.CCI6A and Timer_B7.CCI6B 0 1 Timer_B7.TB6

(1)

CONTROL BITS OR SIGNALS

P3DIR.x P3SEL.x

1 1

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Bus

Keeper

Direction 0: Input 1: Output

P4SEL .x

P4DIR .x

P4IN.x

PadLogic

ModuleXIN

ModuleXOUT

P4OUT .x

Note: x = 0, 1

P4.1/URXD 1 P4.0/UTXD 1

Directioncontrol

fromModuleX

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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6.10.7 Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

P4.0/UTXD1 0 P4.0 (I/O) I: 0; O: 1 0

P4.1/URXD1 1 P4.1 (I/O) I: 0; O: 1 0

(1) X = don't care (2) When in USART1 mode, P4.0 is set to output, P4.1 is set to input.

Table 6-17. Port P4 (P4.0 to P4.1) Pin Functions

PIN NAME (P4.x) x FUNCTION

(2)

USART1.UTXD1

USART1.URXD1

CONTROL BITS OR

SIGNALS

P4DIR.x P4SEL.x

X 1

(1)

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Bus

Keeper

Direction 0: Input 1: Output

P4SEL .x

P4DIR .x

P4IN .x

LCDS 32/36

SegmentSy

PadLogic

ModuleXIN

ModuleXOUT

P4OUT .x

Note : x = 2,3,4,5,6,7

= 34,35 ,36 ,37,38 ,39

P4.7/UCA 0RXD /S34 P4.6/UCA 0TXD /S35 P4.5/UCLK 1 /S36 P4.4/SOMI 1/S37 P4.3/SIMO 1/S38 P4.2/STE1/S39

Directioncontrol

fromModuleX

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.8 Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger

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(1) X = don't care (2) The pin direction is controlled by the USART1 module.

Table 6-18. Port P4 (P4.2 to P4.5) Pin Functions

PIN NAME (P4.x) x FUNCTION

P4.2 (I/O) I: 0; O: 1 0 0

P4.2/STE1/S39 2 USART1.STE1 X 1 0

S39 X X 1

P4.3/SIMO/S38 3 USART1.SIMO1

P4.4/SOMI/S37 4 USART1.SOMI1

P4.5/SOMI/S36 5 USART1.UCLK1

P4.3 (I/O) I: 0; O: 1 0 0

(2)

S38 X X 1 P4.4 (I/O) I: 0; O: 1 0 0

S37 X X 1 P4.5 (I/O) I: 0; O: 1 0 0

S36 X X 1

(2)

CONTROL BITS OR SIGNALS

P4DIR.x P4SEL.x LCDS36

X 1 0

(1)

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MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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Table 6-19. Port P4 (P4.6 and P4.7) Pin Functions

PIN NAME (P4.x) x FUNCTION

P4.6 (I/O) I: 0; O: 1 0 0

P4.6/UCA0TXD/S35 6 USCI_A0.UCA0TXD

S35 X X 1 P4.7 (I/O) I: 0; O: 1 0 0

P4.7/UCA0RXD/S34 7 USCI_A0.UCA0RXD

S34 X X 1

(1) X = don't care (2) When in USCI mode, P4.6 is set to output, P4.7 is set to input.

(2)

SLAS508J –APRIL 2006–REVISED JUNE 2015

CONTROL BITS OR SIGNALS

(1)

P4DIR.x P4SEL.x LCDS32

X 1 0

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P5SEL .x

P5DIR .x

P5IN.x

LCDS 0

SegmentSy

P5OUT .x

P 5.0/S1/A13/OA 1I1

INCH =13

A13

PadLogic

OA1

Note:x=0

y=1

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.9 Port P5, P5.0, Input/Output With Schmitt Trigger

www.ti.com

PIN NAME (P5.x) x FUNCTION

P5.0/S1/A13/OA1I1 0 P5.0 (I/O) I: 0; O: 1 0 X X 0

OAI11 0 X X 1 0 A13 S1 enabled X 0 X X 1 S1 disabled X 1 X X 1

(1) X = don't care (2) Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

Table 6-20. Port P5 (P5.0) Pin Functions

P5DIR.x P5SEL.x INCHx LCDS0

(2)

X 1 13 X X

CONTROL BITS OR SIGNALS

OAPx (OA1) OANx (OA1)

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P5SEL .x

P5DIR .x

P 5IN.x

LCDS0

SegmentSy

P5OUT .x

P5.1/S0/A12 /DAC 1

INCH =12

A12

PadLogic

DAC 12.1OPS

DAC1

0 ifDAC 12 .1AMPx = 0 andDAC 12.1OPS = 1 1 ifDAC 12 .1AMPx = 1 andDAC 12.1OPS = 1 2 ifDAC 12 .1AMPx > 1 andDAC 12.1OPS = 1

Note:x=1

y=0

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

6.10.10 Port P5, P5.1, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

www.ti.com

Table 6-21. Port P5 (P5.1) Pin Functions

PIN NAME (P5.x) x FUNCTION

P5.1/S0/A12/DAC1 1 P5.1 (I/O) I: 0; O: 1 0 X 0 X 0

DAC1 high impedance X X X 1 0 X DVSS X X X 1 1 X DAC1 output X X X 1 >1 X

(2)

A12 S0 enabled X 0 X 0 X 1 S0 disabled X 1 X 0 X 1

P5DIR.x P5SEL.x INCHx DAC12.1OPS DAC12.1AMPx LCDS0

X 1 12 0 X 0

CONTROL BITS OR SIGNALS

(1) X = don't care (2) Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P5SEL .x

P5DIR .x

P 5IN.x

LCDSignal

PadLogic

P5OUT .x

Note : x = 2,3,4

P5.2/COM1 P5.3/COM2 P5.4/COM3

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

6.10.11 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-22. Port P5 (P5.2 to P5.4) Pin Functions

CONTROL BITS OR

PIN NAME (P5.x) x FUNCTION

P5.2/COM1 2 P5.2 (I/O) I: 0; O: 1 0

COM1 X 1

P5.3/COM2 3 P5.3 (I/O) I: 0; O: 1 0

COM2 X 1

P5.4/COM3 4 P5.4 (I/O) I: 0; O: 1 0

COM3 X 1

(1) X = don't care

SIGNALS

P5DIR.x P5SEL.x

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P5SEL .x

P5DIR .x

P 5IN.x

LCDSignal

PadLogic

P5OUT .x

Note : x = 5,6,7

P5.5/R 03 P5.6/LCDREF /R 13 P5.7/R 03

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.12 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger

www.ti.com

Table 6-23. Port P5 (P5.5 to P5.7) Pin Functions

CONTROL BITS OR

PIN NAME (P5.x) x FUNCTION

P5.5/R03 5 P5.5 (I/O) I: 0; O: 1 0

R03 X 1

P5.6/LCDREF/R13 6 P5.6 (I/O) I: 0; O: 1 0

R13 or LCDREF

P5.7/R03 7 P5.7 (I/O) I: 0; O: 1 0

R03 X 1

(1) X = don't care (2) External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.

(2)

SIGNALS

P5DIR.x P5SEL.x

X 1

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P6SEL .x

P6DIR .x

P6IN .x

INCH =0/2/4

PadLogic

P 6OUT.x

P6.0/A0/OA 0I0 P6.2/A2/OA 0I1 P6.4/A4/OA 1I0

OA0/1

Note:x=0,2,4

y=0,1

#=Signalfromorto ADC12

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.13 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger

Table 6-24. Port P6 (P6.0, P6.2, and P6.4) Pin Functions

PIN NAME (P6.x) x FUNCTION

P6.0/A0/OA0I0 0 P6.0 (I/O) I: 0; O: 1 0 X X X

P6.2/A2/OA0I1 2 P6.2 (I/O) I: 0; O: 1 0 X X X

P6.4/A4/OA1I0 4 P6.4 (I/O) I: 0; O: 1 0 X X X

(1) X = don't care (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

OA0I0 0 X 0 X X

(2)

OA0I1 0 X 1 X X

(2)

OA1I0 0 X X 0 X

(2)

CONTROL BITS OR SIGNALS

P6DIR.x P6SEL.x INCHx

X 1 X X 0

X 1 X X 2

X 1 X X 4

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

(1)

OAPx (OA0) OAPx (OA1) OANx (OA0) OANx (OA1)

Bus

Keeper

Direction 0: Input 1: Output

P6SEL .x

P6DIR .x

P6IN .x

INCH =1/3/5

PadLogic

P 6OUT.x

P6.1/A1/OA0O P6.3/A3/OA1O P6.5/A5/OA2O

OAy

OAPMx > 0

OAADC 1

Note:x=1,3,5

y=0,1,2

#=Signalfromorto ADC12

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.14 Port P6, P6.1, P6.3, and P6.5 Input/Output With Schmitt Trigger

www.ti.com

PIN NAME (P6.x) x FUNCTION

P6.1/A1/OA0O 1 P6.1 (I/O) I: 0; O: 1 0 X 0 X

P6.3/A3/OA1O 3 P6.3 (I/O) I: 0; O: 1 0 X 0 X

P6.5/A5/OA2O 5 P6.5 (I/O) I: 0; O: 1 0 X 0 X

(1) X = don't care (2) Setting the OAADC1 bit or setting OAFCx = 00 will cause the operational amplifier to be present at the pin as well as internally

connected to the corresponding ADC12 input.

(3) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

Table 6-25. Port P6 (P6.1, P6.3, and P6.5) Pin Functions

OA0O A1

OA1O A3

OA2O A5

P6DIR.x P6SEL.x OAADC1 OAPMx INCHx

(2)

(3)

(2)

(3)

X X 1 >0 X X 1 X 0 1

X X 1 >0 X X 1 X 0 3

(2)

(3)

X X 1 >0 X X 1 X 0 5

CONTROL BITS OR SIGNALS

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P 6SEL .x

P6DIR .x

P6IN .x

INCH =6

PadLogic

P6OUT .x

P6.6/A6 /DAC0/OA 2I0

OA 2

DAC 0

DAC12 .0OPS

DAC 12 .0AMP > 0

0 ifDAC 12.0AMPx = 0 andDAC 12.0OPS = 0 1 ifDAC 12.0AMPx = 1 andDAC 12.0OPS = 0 2 ifDAC 12.0AMPx > 1 andDAC 12.0OPS = 0

DVSS

Note:x=6

#=Signalfromorto ADC12

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

6.10.15 Port P6, P6.6, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

www.ti.com

Table 6-26. Port P6 (P6.6) Pin Functions

CONTROL BITS OR SIGNALS

PIN NAME (P6.x) x FUNCTION

P6.6/A6/DAC0/OA2I0 6 P6.6 (I/O) I: 0; O: 1 0 X 1 X X

DAC0 high impedance X X X 0 0 X DVSS X X X 0 1 X DAC0 output X X X 0 >1 X

(2)

A6 OA2I0 0 X 0 X X 0

P6DIR.x P6SEL.x INCHx DAC12.0OPS DAC12.0AMPx

X 1 6 X X X

(1) X = don't care (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

(1)

OAPx (OA2) OANx (OA2)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P 6SEL .x

P6DIR .x

P6IN .x

INCH =7

PadLogic

P6OUT .x

P6.7/A7 /DAC 1/SVSIN

DAC 1

DAC12 .1OPS

DAC 12 .1AMP > 0

0 ifDAC 12.1AMPx = 0 andDAC 12.1OPS = 0 1 ifDAC 12.1AMPx = 1 andDAC 12.1OPS = 0 2 ifDAC 12.1AMPx > 1 andDAC 12.1OPS = 0

ToSVSMux

VLD =15

DVSS

Note:x=7

#=Signalfromorto ADC12

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

6.10.16 Port P6, P6.7, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

www.ti.com

Table 6-27. Port P6 (P6.7) Pin Functions

PIN NAME (P6.x) x FUNCTION

P6.7/A7/DAC1/SVSIN 7 P6.7 (I/O) I: 0; O: 1 0 X 1 X

DAC1 high impedance X X X 0 0 DVSS X X X 0 1 DAC1 output X X X 0 >1

(2)

SVSIN

P6DIR.x P6SEL.x INCHx DAC12.1OPS DAC12.1AMPx

X 1 7 X X

0 1 0 1 X

CONTROL BITS OR SIGNALS

(1) X = don't care (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog

signals.

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P7SEL .x

P7DIR .x

P7IN .x

LCDS28/32

SegmentSy

PadLogic

ModuleXIN

ModuleXOUT

P 7OUT .x

P7.3/UCA 0CLK /S30 P7.2/UCA 0SOMI/S 31 P7.1/UCA 0SIMO/S 32 P7.0/UCA 0STE /S33

Directioncontrol

fromModuleX

Note:x=0,1,2,3

y=30,31,32,33

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

6.10.17 Port P7, P7.0 to P7.3, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-28. Port P7 (P7.0 and P7.1) Pin Functions

PIN NAME (P7.x) x FUNCTION

CONTROL BITS OR SIGNALS

P7DIR.x P7SEL.x LCDS32

P7.0/UCA0STE/S33 0 P7.0 (I/O) I: 0; O: 1 0 0

USCI_A0.UCA0STE

(1)

S33

(2)

X 1 0 X X 1

P7.1/UCA0SIMO/S32 1 P7.1 (I/O) I: 0; O: 1 0 0

USCI_A0.UCA0SIMO

(2)

X 1 0

S32 X X 1

(1) X = don't care (2) The pin direction is controlled by the USCI module.

(1)

Table 6-29. Port P7 (P7.2 and P7.3) Pin Functions

PIN NAME (P7.x) x FUNCTION

CONTROL BITS OR SIGNALS

P7DIR.x P7SEL.x LCDS28

P7.2/UCA0SOMI/S31 2 P7.2 (I/O) I: 0; O: 1 0 0

USCI_A0.UCA0SOMI

(2)

X 1 0

S31 X X 1

P7.3/UCA0CLK/S30 3 P7.3 (I/O) I: 0; O: 1 0 0

USCI_A0.UCA0CLK

(2)

X 1 0

S30 X X 1

(1) X = don't care (2) The pin direction is controlled by the USCI module.

(1)

www.ti.com

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P7SEL .x

P7DIR .x

P7IN.x

LCDS 24/28

SegmentSy

PadLogic

P7OUT .x

P7.7/S26 P7.6/S27 P7.5/S28 P7.4/S29

Note:x=4,5,6,7

y=26,27,28,29

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

6.10.18 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-30. Port P7 (P7.4 and P7.5) Pin Functions

PIN NAME (P7.x) x FUNCTION

P7.4/S29 4 P7.4 (I/O) I: 0; O: 1 0 0

S29 X X 1

P7.5/S28 5 P7.5 (I/O) I: 0; O: 1 0 0

S28 X X 1

(1) X = don't care

CONTROL BITS OR SIGNALS

P7DIR.x P7SEL.x LCDS28

Table 6-31. Port P7 (P7.6 and P7.7) Pin Functions

PIN NAME (P7.x) x FUNCTION

P7.6/S27 6 P7.6 (I/O) I: 0; O: 1 0 0

P7.7/S26 7 P7.7 (I/O) I: 0; O: 1 0 0

(1) X = don't care

S27 X X 1

S26 X X 1

CONTROL BITS OR SIGNALS

P7DIR.x P7SEL.x LCDS24

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P8SEL .x

P8DIR .x

P 8IN.x

LCDS 16/20/24

SegmentSy

PadLogic

P8OUT .x

Note : x = 0,1,2,3,4,5,6,7

y = 25,24,23,22,21,20,19 ,18

P8.7/S18 P8.6/S19 P8.5/S20 P8.4/S21 P8.3/S22 P8.2/S23 P8.1/S24 P8.0/S25

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.19 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger

www.ti.com

Table 6-32. Port P8 (P8.0 and P8.1) Pin Functions

PIN NAME (P8.x) x FUNCTION

P8.0/S18 0 P8.0 (I/O) I: 0; O: 1 0 0

P8.1/S19 0 P8.0 (I/O) I: 0; O: 1 0 0

(1) X = don't care

Table 6-33. Port P8 (P8.2 to P8.5) Pin Functions

PIN NAME (P8.x) x FUNCTION

P8.2/S20 2 P8.2 (I/O) I: 0; O: 1 0 0

P8.3/S21 3 P8.3 (I/O) I: 0; O: 1 0 0

P8.4/S22 4 P8.4 (I/O) I: 0; O: 1 0 0

P8.5/S23 5 P8.5 (I/O) I: 0; O: 1 0 0

(1) X = don't care

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

CONTROL BITS OR SIGNALS

P8DIR.x P8SEL.x LCDS16

S18 X X 1

(1)

S19 X X 1

CONTROL BITS OR SIGNALS

P8DIR.x P8SEL.x LCDS20

S20 X X 1

S21 X X 1

S22 X X 1

(1)

S23 X X 1

Submit Documentation Feedback

MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

www.ti.com

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-34. Port P8 (P8.6 and P8.7) Pin Functions

PIN NAME (P8.x) X FUNCTION

P8.6/S24 6 P8.6 (I/O) I: 0; O: 1 0 0

S24 X X 1

P8.7/S25 7 P8.7 (I/O) I: 0; O: 1 0 0

S25 X X 1

(1) X = don't care

CONTROL BITS OR SIGNALS

P8DIR.x P8SEL.x LCDS24

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P9SEL .x

P9DIR .x

P 9IN.x

LCDS 8/12/16

SegmentSy

PadLogic

P9OUT .x

Note : x = 0,1,2,3,4,5,6,7

y = 17,16,15,14,13,12,11 ,10

P9.7/S10 P9.6/S11 P9.5/S12 P9.4/S13 P9.3/S14 P9.2/S15 P9.1/S16 P9.0/S17

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.20 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger

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Table 6-35. Port P9 (P9.0 and P9.1) Pin Functions

PIN NAME (P9.x) x FUNCTION

P9.0/S17 0 P9.0 (I/O) I: 0; O: 1 0 0

S17 X X 1

P9.1/S16 1 P9.1 (I/O) I: 0; O: 1 0 0

(1) X = don't care

PIN NAME (P9.x) x FUNCTION

P9.2/S15 2 P9.2 (I/O) I: 0; O: 1 0 0

P9.3/S14 3 P9.3 (I/O) I: 0; O: 1 0 0

P9.4/S13 4 P9.4 (I/O) I: 0; O: 1 0 0

P9.5/S12 5 P9.5 (I/O) I: 0; O: 1 0 0

(1) X = don't care

S16 X X 1

Table 6-36. Port P9 (P9.2 to P9.5) Pin Functions

S15 X X 1

S14 X X 1

S13 X X 1

S12 X X 1

CONTROL BITS OR SIGNALS

P9DIR.x P9SEL.x LCDS16

CONTROL BITS OR SIGNALS

P9DIR.x P9SEL.x LCDS12

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-37. Port P9 (P9.6 and P9.7) Pin Functions

PIN NAME (P9.x x FUNCTION

P9.6/S11 6 P9.6 (I/O) I: 0; O: 1 0 0

S11 X X 1

P9.7/S10 7 P9.7 (I/O) I: 0; O: 1 0 0

S10 X X 1

(1) X = don't care

CONTROL BITS OR SIGNALS

P9DIR.x P9SEL.x LCDS8

(1)

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P10SEL.x

P10DIR.x

P10IN.x

LCDS 4/8

SegmentSy

PadLogic

P10OUT.x

Note : x = 0,1,2,3,4,5

y = 9,8,7,6,5,4

P10.5/S4 P10.4/S5 P10.3/S6 P10.2/S7 P10.1/S8 P10.0/S9

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.21 Port P10, P10.0 to P10.5, Input/Output With Schmitt Trigger

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Table 6-38. Port P10 (P10.0 and P10.1) Pin Functions

PIN NAME (P10.x) x FUNCTION

P10.0/S9 0 P10.0 (I/O) I: 0; O: 1 0 0

P10.1/S8 1 P10.1 (I/O) I: 0; O: 1 0 0

(1) X = don't care

PIN NAME (P10.x) x FUNCTION

P10.2/S7 2 P10.2 (I/O) I: 0; O: 1 0 0

Table 6-39. Port P10 (P10.2 to P10.5) Pin Functions

P10.3/S6 3 P10.3 (I/O) I: 0; O: 1 0 0

P10.4/S5 4 P10.4 (I/O) I: 0; O: 1 0 0

P10.5/S4 5 P10.5 (I/O) I: 0; O: 1 0 0

(1) X = don't care

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

CONTROL BITS OR SIGNALS

P10DIR.x P10SEL.x LCDS8

S9 X X 1

S8 X X 1

S7 X X 1

S6 X X 1

S5 X X 1

S4 X X 1

CONTROL BITS OR SIGNALS

P10DIR.x P10SEL.x LCDS4

(1)

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Bus

Keeper

Direction 0: Input 1: Output

P10SEL.x

P10DIR.x

P10IN.x

LCDS 0

SegmentSy

0P10OUT.x

Note : x = 6

= 3

P10.6/S 3/A15

INCH =15

A15

PadLogic

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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6.10.22 Port P10, P10.6, Input/Output With Schmitt Trigger

SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 6-40. Port P10 (P10.6) Pin Functions

PIN NAME (P10.x) x FUNCTION

P10.6/S3/A15 P5.0 (I/O) I: 0; O: 1 0 X 0

(2)

A15

S3 enabled X 0 X 1

(1) X = don't care (2) Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

S3 disabled X 1 X 1

P10DIR.x P10SEL.x INCHx LCDS0

CONTROL BITS OR SIGNALS

X 1 15 0

(1)

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Bus

Keeper

Direction 0: Input 1: Output

P10SEL.x

P10DIR.x

P10IN.x

LCDS 0

SegmentSy

P10OUT.x

Note : x = 7

y = 2

P10.7/S2/A14/OA 2I1

INCH =14

A14

PadLogic

OA2

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.23 Port P10, P10.7, Input/Output With Schmitt Trigger

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PIN NAME (P10.x) x FUNCTION

P10.7/S2/A14/OA2I1 7 P10.7(I/O) I: 0; O: 1 0 X X 0

A14 OA2I1 S2 enabled X 0 X X 1 S2 disabled X 1 X X 1

(1) X = don't care (2) Setting the P10SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying

analog signals.

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

Table 6-41. Port P10 (P10.7) Pin Functions

CONTROL BITS OR SIGNALS

P10DIR.x P10SEL.x INCHx LCDS0

(2)

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MSP430CG4618 MSP430CG4617 MSP430CG4616

X 1 14 X 0

0 X X 1 0

(1)

OAPx (OA1) OANx (OA1)

REF+

/DAC0

ReferenceVoltageto ADC12

'0',ifDAC12CALON=0

DAC12AMPx>1 ANDDAC12OPS=1

'1',ifDAC12AMPx=1

'1',ifDAC12AMPx>1

DAC12OPS

ReferenceVoltagetoDAC1

ReferenceVoltagetoDAC0

IfthereferenceofDAC0istakenfrompinVe

REF+

/DAC0 ,unpredictablevoltagelevelswillbeonpin.

Inthissituation,theDAC0outputisfedbacktoitsownreferenceinput.

DAC0_2_OA

DAC12.0OPS

P6.6/A6/DAC0/OA2I0

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MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

6.10.24 Ve

REF+

/DAC0

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MSP430CG4618 MSP430CG4617 MSP430CG4616

TDI

TDO

TMS

TDI/TCLK

TDO/TDI

Controlled

byJTAG

TCK

TMS

TCK

ControlledbyJTAG

Test

JTAG

and

Emulation

Module

BurnandTest

Fuse

RST/NMI

TCK

Tau~50ns

Brownout

ControlledbyJTAG

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

www.ti.com

6.10.25 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output

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MSP430CG4618 MSP430CG4617 MSP430CG4616

TimeTMSGoesLow AfterPOR

TMS

I(TF)

ITDI/TCLK

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6.10.26 JTAG Fuse Check Mode

Devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 6-1). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination.

) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.

(TF)

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

Figure 6-1. Fuse Check Mode Current

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

7 Device and Documentation Support

7.1 Device Support

7.1.1 Getting Started and Next Steps

For more information on the MSP430F4x family of devices and the tools and libraries that are available to help with your development, visit the Getting Started page.

7.1.2 Development Tools Support

All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.

7.1.2.1 Hardware Features

See the Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.

MSP430 4-Wire 2-Wire Clock State Trace

Architecture JTAG JTAG Control Sequencer Buffer

MSP430 Yes No 2 No Yes No No No

Break- Range LPMx.5 points Break- Debugging

(N) points Support

www.ti.com

7.1.2.2 Recommended Hardware Options

7.1.2.2.1 Target Socket Boards

The target socket boards allow easy programming and debugging of the device using JTAG. They also feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG programmer and debugger included. The following table shows the compatible target boards and the supported packages.

Package Target Board and Programmer Bundle Target Board Only

100-pin LQFP (PZ) MSP-FET430U100 MSP-TS430PZ100

7.1.2.2.2 Experimenter Boards

Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional hardware components and connectivity for full system evaluation and prototyping. See

www.ti.com/msp430tools for details.

7.1.2.2.3 Debugging and Programming Tools

Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full list of available tools at www.ti.com/msp430tools.

7.1.2.2.4 Production Programmers

The production programmers expedite loading firmware to devices by programming several devices simultaneously.

Part Number PC Port Features Provider

MSP-GANG Serial and USB Program up to eight devices at a time. Works with PC or standalone. Texas Instruments

7.1.2.3 Recommended Software Options

7.1.2.3.1 Integrated Development Environments

Software development tools are available from TI or from third parties. Open source solutions are also available.

This device is supported by Code Composer Studio™ IDE (CCS).

Product Folder Links: MSP430FG4619 MSP430FG4618 MSP430FG4617 MSP430FG4616 MSP430CG4619

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MSP430CG4618 MSP430CG4617 MSP430CG4616

Texas Instruments MSP430FG4618, MSP430FG4617, MSP430FG4619, MSP430CG4618, MSP430FG4616 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual