TEXAS INSTRUMENTS MSC1200 Technical data

查询MSC1200供应商

Precision Analog-to-Digital Converter (ADC)

and Digital-to-Analog Converter (DAC)

with 8051 Microcontroller and Flash Memory

M

MSC1200

S

C

1

2

0

0

SBAS289E – JUNE 2003 – REVISED NOVEMBER 2004

FEATURES

ANALOG FEATURES

● 24-BITS NO MISSING CODES

● 22-BITS EFFECTIVE RESOLUTION AT 10Hz

Low Noise: 75nV

● PGA FROM 1 TO 128

● PRECISION ON-CHIP VOLTAGE REFERENCE

● 8 DIFFERENTIAL/SINGLE-ENDED CHANNELS

● ON-CHIP OFFSET/GAIN CALIBRATION

● OFFSET DRIFT: 0.02ppm/°C

● GAIN DRIFT: 0.5ppm/°C

● ON-CHIP TEMPERATURE SENSOR

● SELECTABLE BUFFER INPUT

● BURNOUT DETECT

● 8-BIT CURRENT DAC

DIGITAL FEATURES
Microcontroller Core

● 8051-COMPATIBLE

● HIGH-SPEED CORE:

4 Clocks per Instruction Cycle

● DC TO 33MHz

● ON-CHIP OSCILLATOR

● PLL WITH 32kHz CAPABILITY

● SINGLE INSTRUCTION 121ns

● DUAL DATA POINTER

Memory

● 4kB OR 8kB OF FLASH MEMORY

● FLASH MEMORY PARTITIONING

● ENDURANCE 1M ERASE/WRITE CYCLES,

100 YEAR DATA RETENTION

● 128 BYTES DATA SRAM

● IN-SYSTEM SERIALLY PROGRAMMABLE

● FLASH MEMORY SECURITY

● 1kB BOOT ROM

Peripheral Features

● 16 DIGITAL I/O PINS

● ADDITIONAL 32-BIT ACCUMULATOR

● TWO 16-BIT TIMER/COUNTERS

● SYSTEM TIMERS

● PROGRAMMABLE WATCHDOG TIMER

● FULL DUPLEX USART

● BASIC SPI

● BASIC I2C

™

™

● POWER MANAGEMENT CONTROL

● INTERNAL CLOCK DIVIDER

● IDLE MODE CURRENT < 200µA

● STOP MODE CURRENT < 100nA

● DIGITAL BROWNOUT RESET

● ANALOG LOW VOLTAGE DETECT

● 20 INTERRUPT SOURCES

GENERAL FEATURES

● PACKAGE: TQFP-48

● LOW POWER: 3mW

● INDUSTRIAL TEMPERATURE RANGE:

–40°C to +85°C

● POWER SUPPLY: 2.7V to 5.25V

APPLICATIONS

● INDUSTRIAL PROCESS CONTROL

● INSTRUMENTATION

● LIQUID/GAS CHROMATOGRAPHY

● BLOOD ANALYSIS

● SMART TRANSMITTERS

● PORTABLE INSTRUMENTS

● WEIGH SCALES

● PRESSURE TRANSDUCERS

● INTELLIGENT SENSORS

● PORTABLE APPLICATIONS

● DAS SYSTEMS

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright © 2003-2004, Texas Instruments Incorporated

www.ti.com

PACKAGE/ORDERING INFORMATION

PRODUCT MEMORY PACKAGE-LEAD DESIGNATOR RANGE MARKING

MSC1200Y2 4k TQFP-48 PFB –40°C to +85°C MSC1200Y2
MSC1200Y2 4k

MSC1200Y3 8k TQFP-48 PFB –40°C to +85°C MSC1200Y3
MSC1200Y3 8k

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our web site at
www.ti.com/msc.

FLASH PACKAGE TEMPERATURE PACKAGE

ABSOLUTE MAXIMUM RATINGS

Analog Inputs

Input Current ............................................................ 100mA, Momentary

Input Current ..............................................................10mA, Continuous

Input Voltage.............................................AGND – 0.3V to AV

Power Supply

DV

to DGND......................................................................–0.3V to 6V

DD

AV

to AGND ......................................................................–0.3V to 6V

DD

AGND to DGND .............................................................. –0.3V to +0.3V

V

to AGND ....................................................... –0.3V to AVDD + 0.3V

REF

Digital Input Voltage to DGND .............................. –0.3V to DV

Digital Output Voltage to DGND ...........................–0.3V to DV

Maximum Junction Temperature ................................................ +150°C

Operating Temperature Range ...................................... –40°C to +85°C

Storage Temperature Range ....................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................ +235°C

Package Power Dissipation ............................... (T

Output Current All Pins ................................................................ 200mA

Output Pin Short Circuit .....................................................................10s

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case (

Digital Outputs

Output Current ......................................................... 100mA, Continuous

I/O Source/Sink Current............................................................... 100mA

Power Pin Maximum .................................................................... 300mA

NOTE: (1) Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute-maximum­rated conditions for extended periods may affect device reliability.

(

θ

JA

θ

) ...........................12.8°C/W

JC

(1)

SPECIFIED

"" " "
"" " "

(1)

ELECTROSTATIC
DISCHARGE SENSITIVITY

+ 0.3V

DD

+ 0.3V

DD

+ 0.3V

DD

Max – T

J

)....................... 56.5°C/W

AMBIENT

)/

θ

JA

This integrated circuit can be damaged by ESD. Texas Instru­ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

MSC1200Yx FAMILY FEATURES

FEATURES

Flash Program Memory (Bytes) Up to 4k Up to 8k
Flash Data Memory (Bytes) Up to 2k Up to 4k
Internal Scratchpad RAM (Bytes) 128 128

NOTES: (1) All peripheral features are the same on all devices; the flash
memory size is the only difference. (2) The last digit of the part number (N)
represents the onboard flash size = (2

(1)

MSC1200Y2

N

)kBytes.

(2)

MSC1200Y3

(2)

ELECTRICAL CHARACTERISTICS: AVDD = 5V

All specifications from T
unless otherwise noted.

PARAMETER CONDITION MIN TYP MAX UNITS
ANALOG INPUT (AIN0-AIN7, AINCOM)

Analog Input Range Buffer OFF AGND – 0.1 AV

Full-Scale Input Voltage Range (In+) – (In–) ±V
Differential Input Impedance Buffer OFF 7/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
Sinc2 Filter –3dB 0.318 • f
Sinc3 Filter –3dB 0.262 • f
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance Buffer ON 7 pF
Input Leakage Current Multiplexer Channel Off, T = +25°C 0.5 pA
Burnout Current Sources Buffer ON ±2 µA

ADC OFFSET DAC

Offset DAC Range
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±1.0 % of Range
Offset DAC Gain Error Drift 0.6 ppm/°C

MIN

to T

MAX

, DV

= +2.7V to 5.25V, f

DD

= 15.625kHz, PGA = 1, Buffer ON, f

MOD

Buffer ON AGND + 50mV AV

= 10Hz, Bipolar, and V

DATA

MSC1200Yx

±V

/(2 • PGA)

REF

≡ (REF IN+) – (REF IN–) = +2.5V,

REF

+ 0.1 V

DD

– 1.5 V

DD

/PGA V

REF

DATA
DATA
DATA

V

2

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MSC1200

SBAS289E

ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)

All specifications from T
unless otherwise noted.

PARAMETER CONDITION MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Resolution 24 Bits
ENOB 22 Bits
Output Noise See Typical Characteristics
No Missing Codes Sinc
Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 %FSR
Offset Error After Calibration 1.5 ppm of FS
Offset Drift
Gain Error

(1)

(2)

Gain Error Drift
System Gain Calibration Range 80 120 % of FS
System Offset Calibration Range –50 50 % of FS
Common-Mode Rejection At DC 100 120 dB

Normal Mode Rejection f

Power-Supply Rejection At DC, dB = –20log(∆V

VOLTAGE REFERENCE INPUTS

Reference Input Range REF IN+, REF IN– AGND AV
V

REF

Common-Mode Rejection At DC 115 dB
Input Current V

ON-CHIP VOLTAGE REFERENCE

Output Voltage VREFH = 1 at +25°C 2.5 V

Short-Circuit Current Source 9mA
Short-Circuit Current Sink 10 mA
Short-Circuit Duration Sink or Source Indefinite
Startup Time from Power ON 0.4 ms
Temperature Sensor

Temperature Sensor Voltage T = +25°C115mV
Temperature Sensor Coefficient 375 µV/°C

IDAC OUTPUT CHARACTERISTICS

Full-Scale Output Current 1mA
Maximum Short-Circuit Current Duration Indefinite
Compliance Voltage AVDD – 1.5 V

ANALOG POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage AV

Analog Current Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 nA
ADC Current I

V

Supply Current I

REF

I

Supply Current I

DAC

NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AV
turn buffer off. (3) DV

to T

MIN

MAX

(1)

is change in digital result.

OUT

, DV

= +2.7V to 5.25V, f

DD

ADC

VREF

IDAC

= 15.625kHz, PGA = 1, Buffer ON, f

MOD

= 10Hz, Bipolar, and V

DATA

≡ (REF IN+) – (REF IN–) = +2.5V,

REF

MSC1200Yx

3

Filter 24 Bits

Before Calibration 0.02 ppm of FS/°C

After Calibration 0.005 %

Before Calibration 0.5 ppm/°C

f

= 60Hz, f

CM

f

= 50Hz, f

CM

f

= 60Hz, f

CM

= 50Hz, f

SIG

f

= 60Hz, f

SIG

V

≡ (REF IN+) – (REF IN–) 0.3 2.5 AV

REF

= 2.5V, PGA = 1 1 µA

REF

= 10Hz 130 dB

DATA

= 50Hz 120 dB

DATA

= 60Hz 120 dB

DATA

= 50Hz 100 dB

DATA

= 60Hz 100 dB

DATA

OUT

/∆VDD)

(3)

100 dB

(2)

DD

DD

VREFH = 0 1.25 V

DD

4.75 5.0 5.25 V

PGA = 1, Buffer OFF 170 µA

PGA = 128, Buffer OFF 430 µA

PGA = 1, Buffer ON 230 µA

PGA = 128, Buffer ON 770 µA

ADC ON 360 µA

IDAC = 00

H

230 µA

– 1.5V with buffer ON. To calibrate gain,

DD

V
V

MSC1200

SBAS289E

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3

ELECTRICAL CHARACTERISTICS: AVDD = 3V

All specifications from T
unless otherwise noted.

PARAMETER CONDITION MIN TYP MAX UNITS
ANALOG INPUT (AIN0-AIN7, AINCOM)

Analog Input Range Buffer OFF AGND – 0.1 AV

Full-Scale Input Voltage Range (In+) – (In–) ±V
Differential Input Impedance Buffer OFF 7/PGA MΩ
Input Current Buffer ON 0.5 nA
Bandwidth
Fast Settling Filter –3dB 0.469 • f
Sinc2 Filter –3dB 0.318 • f
Sinc3 Filter –3dB 0.262 • f
Programmable Gain Amplifier User-Selectable Gain Ranges 1 128
Input Capacitance Buffer On 7 pF
Input Leakage Current Multiplexer Channel Off, T = +25°C 0.5 pA
Burnout Current Sources Buffer ON ±2 µA

ADC OFFSET DAC

Offset DAC Range
Offset DAC Monotonicity 8 Bits
Offset DAC Gain Error ±1.5 % of Range
Offset DAC Gain Error Drift 0.6 ppm/°C

SYSTEM PERFORMANCE

Resolution 24 Bits
ENOB 22 Bits
Output Noise See Typical Characteristics
No Missing Codes Sinc
Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 %FSR
Offset Error After Calibration 1.3 ppm of FS
Offset Drift
Gain Error

(1)

(2)

Gain Error Drift
System Gain Calibration Range 80 120 % of FS
System Offset Calibration Range –50 50 % of FS
Common-Mode Rejection At DC 100 130 dB

Normal Mode Rejection f

Power-Supply Rejection At DC, dB = –20log(DV

VOLTAGE REFERENCE INPUTS

Reference Input Range REF IN+, REF IN– AGND AV
V

REF

Common-Mode Rejection At DC 110 dB
Input Current V

ON-CHIP VOLTAGE REFERENCE

Output Voltage VREFH = 0 at +25°C 1.25 V
Short-Circuit Current Source 4mA
Short-Circuit Current Sink 5 µA
Short-Circuit Duration Sink or Source Indefinite
Startup Time from Power ON 0.2 ms
Temperature Sensor

Temperature Sensor Voltage T = +25°C 115 mV
Temperature Sensor Coefficient 375 µV/°C

IDAC OUTPUT CHARACTERISTICS

Full-Scale Output Current 1mA
Maximum Short-Circuit Current Duration Indefinite
Compliance Voltage AVDD – 1.5 V

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage AV
Analog Current Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 < 1 nA

ADC Current I

V

Supply Current I

REF

I

Supply Current I

DAC

NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AV
turn buffer off. (3) DV

to T

MIN

(1)

, AV

MAX

is change in digital result.

OUT

= +3V, DV

DD

= +2.7V to 5.25V, f

DD

ADC

VREF

IDAC

= 15.625kHz, PGA = 1, Buffer ON, f

MOD

= 10Hz, Bipolar, and V

DATA

≡ (REF IN+) – (REF IN–) = +1.25V,

REF

MSC1200Yx

+ 0.1 V

Buffer ON AGND + 50mV A V

DATA
DATA
DATA

±V

/(2 • PGA)

REF

3

Filter 24 Bits

DD

– 1.5 V

DD

/PGA V

REF

Before Calibration 0.02 ppm of FS/°C

After Calibration 0.005 %

Before Calibration 0.5 ppm/°C

f

= 60Hz, f

CM

f

= 50Hz, f

CM

f

= 60Hz, f

CM

= 50Hz, f

SIG

f

= 60Hz, f

SIG

V

≡ (REF IN+) – (REF IN–) 0.3 1.25 AV

REF

= 1.25V, PGA = 1 0.5 µA

REF

= 10Hz 130 dB

DATA

= 50Hz 120 dB

DATA

= 60Hz 120 dB

DATA

= 50Hz 100 dB

DATA

= 60Hz 100 dB

DATA

OUT

DD

/DVDD)

(3)

88 dB

(2)

DD

DD

2.7 3.0 3.6 V

PGA = 1, Buffer OFF 150 µA

PGA = 128, Buffer OFF 380 µA

PGA = 1, Buffer ON 200 µA

PGA = 128, Buffer ON 610 µA

ADC ON 330 µA

IDAC = 00

H

220 µA

– 1.5V with buffer ON. To calibrate gain,

DD

V

V
V

4

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MSC1200

SBAS289E

DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V

All specifications from T

PARAMETER CONDITION MIN TYP MAX UNITS
POWER-SUPPLY REQUIREMENTS

Digital Supply Current DV

DIGITAL INPUT/OUTPUT (CMOS)

Logic Level: V

Ports 1 and 3, Input Leakage Current, Input Mode V

IH

V

IL

Pin XIN Input Leakage Current 0 µA
I/O Pin Hysteresis 700 mV
V

, Ports 1 and 3, All Output Modes IOL = 1mA DGND 0.4 V

OL

V

, Ports 1 and 3, All Output Modes IOL = 30mA, 3V (20mA) 1.5 V

OL

V

, Ports 1 and 3, Strong Drive Output IOH = 1mA DVDD – 0.4 DVDD – 0.1 DV

OH

V

, Ports 1 and 3, Strong Drive Output IOH = 30mA, 3V (20mA) DVDD – 1.5 V

OH

Ports 1 and 3 Pull-Up Resistors 11 kΩ

to T

MIN

, unless otherwise specified.

MAX

MSC1200Yx

Normal Mode, f

Normal Mode, f

Internal Oscillator LF Mode (12.8MHz nominal) 7.1 mA

DD

= 1MHz 0.6 mA

OSC

= 8MHz, All Peripherals ON 5 mA

OSC

2.7 3.0 3.6 V

Stop Mode, DBOR OFF 100 nA

DV

Normal Mode, f

Normal Mode, f

Internal Oscillator LF Mode (12.8MHz nominal) 15 mA

DD

= 1MHz 1.2 mA

OSC

= 8MHz, All Peripherals ON 9 mA

OSC

4.75 5.0 5.25 V

Internal Oscillator HF Mode (25.6MHz nominal) 29 mA

Stop Mode, DBOR OFF 100 nA

(except XIN pin) 0.6 • DV

(except XIN pin) DGND 0.2 • DV

= DVDD or VIH = 0V 0 µA

IH

DD

DV

DD

DD

DD

V
V

V

FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V

t

= 1µs, t

USEC

PARAMETER CONDITION MIN TYP MAX UNITS

Flash Memory Endurance 100,000 1,000,000 cycles
Flash Memory Data Retention 100 Years
Mass and Page Erase Time Set with FER Value in FTCON 10 ms
Flash Memory Write Time Set with FWR Value in FTCON 30 40 µs

MSEC

= 1ms

MSC1200Yx

MSC1200

SBAS289E

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5

AC ELECTRICAL CHARACTERISTICS

(1)

: DVDD = 2.7V to 5.25V

MSC1200Yx

PARAMETER CONDITION MIN TYP MAX UNITS
PHASE LOCK LOOP (PLL)

Input Frequency Range External Crystal/Clock Frequency (f
PLL LF Mode PLLDIV = 449 (default) 14.7456 MHz

) 32.768 kHz

OSC

PLL HF Mode PLLDIV = 899 (must be set by user) 29.4912 MHz
PLL Lock Time Within 1% 2 ms

INTERNAL OSCILLATOR (IO) See Typical Characteristics
IO LF Mode 12.8 MHz
IO HF Mode 25.6 MHz
Internal Oscillator Settling Time Within 1% 1 ms

NOTE: (1) Parameters are valid over operating temperature range, unless otherwise specified.

EXTERNAL CLOCK DRIVE CLK TIMING

2.7V to 3.6V 4.75V to 5.25V
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNITS
External Clock Mode

(1)

f

OSC

(1)

1/t

OSC

(1)

f

OSC

t

HIGH

t

LOW

t

R

t

F

NOTES: (1) t

CLK

= 1/f

A External Crystal Frequency (f
A External Clock Frequency (f
A External Ceramic Resonator Frequency (f
A HIGH Time
A LOW Time
A Rise Time
A Fall Time

= one oscillator clock period for clock divider = 1. (2) These values are characterized but not 100% production tested.

OSC

(2)
(2)
(2)

(2)

)120133MHz

OSC

)020033MHz

OSC

)1 12 1 12 MHz

OSC

15 10 ns
15 10 ns

55ns
55ns

t

HIGH

V

IH

V

IH

0.8V 0.8V
t

LOW

t

R

V

IH

V

IH

0.8V 0.8V

t

OSC

t

F

FIGURE A. External Clock Drive CLK.

SERIAL FLASH PROGRAMMING TIMING

SYMBOL FIGURE PARAMETER MIN MAX UNIT

t

RW

t

RRD

t

RFD

t

RS

t

RH

RST

P1.0/PROG

B RST width 2 t

OSC

— ns
B RST rise to P1.0 internal pull high — 5 µs
B RST falling to CPU start — 18 ms
B Input signal to RST falling setup time t

OSC

— ns
B RST falling to P1.0 hold time 18 — ms

t

RW

t

RRD

t

RS

, t

t

RFD

RH

NOTE: P1.0 is internally pulled-up with ~11kΩ during RST high.

FIGURE B. Serial Flash Programming Power-On Timing.

6

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MSC1200

SBAS289E

PIN CONFIGURATION

Top View TQFP

NC

XIN

XOUT

DGND

RST

NC
NC

CAP

AV
AGND
AGND

AINCOM

DGNDNCDVDDP3.7

48 47 46 45 44 43 42

1
2
3
4
5
6
7
8
9

DD

10
11
12

13 14 15 16 17 18 19 20 21 22 233724

IDAC

REFIN–

P3.6/SCK/SCL/CLKS

P3.5/T1

MSC1200

NC

AIN7

AIN6

P3.4/T0

P3.3/INT1

P3.2/INT0

41 40 39 38

AIN5

AIN4

AIN3

P3.1/TxD0

P3.0/RxD0

AIN2

AIN1

P1.7/INT5

36
35
34
33
32
31
30
29
28
27
26
25

AIN0

DV

DD

DV

DD

DGND
DGND
P1.6/INT4
P1.5/INT3
P1.4/INT2/SS
P1.3/DIN
P1.2/DOUT
P1.1
P1.0/PROG
NC

REFOUT/REFIN+

MSC1200

SBAS289E

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7

PIN DESCRIPTIONS

PIN # NAME DESCRIPTION

1,6,7,16,25,47 NC No Connection

2 XIN The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators.

3 X OUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators.

4, 33, 34, 48 DGND Digital Ground

5 RST A HIGH on the reset input for two t
8 CAP Capacitor (220pF ceramic)

9AV

10, 11 AGND Analog Ground

12 AINCOM Analog Input (can be analog common for single-ended inputs or analog input for differential inputs)
13 IDAC IDAC Output

14 REFOUT/REF IN+ Internal Voltage Reference Output/Voltage Reference Positive Input
15 REF IN– Voltage Reference Negative Input (tie to AGND for internal voltage reference)
17 AIN7 Analog Input Channel 7
18 AIN6 Analog Input Channel 6
19 AIN5 Analog Input Channel 5
20 AIN4 Analog Input Channel 4
21 AIN3 Analog Input Channel 3
22 AIN2 Analog Input Channel 2
23 AIN1 Analog Input Channel 1
24 AIN0 Analog Input Channel 0

26-32, 37 P1.0-P1.7 Port 1 is a bidirectional I/O port (refer to P1DDRL, SFR AE

DD

XIN can also be an input if there is an external clock source instead of a crystal.

XOUT serves as the output of the crystal amplifier.

periods will reset the device.

OSC

Analog Power Supply

, and P1DDRH, SFR AFH, for port pin configuration control).

Port 1—Alternate Functions:

PORT ALTERNATE MODE

P1.0
P1.1 N/A
P1.2 DOUT Serial Data Out
P1.3 DIN Serial Data In
P1.4 INT2/
P1.5
P1.6 INT4 External Interrupt 4
P1.7

PROG

INT3

INT5

H

Serial Programming Mode

External Interrupt 2/Slave Select

SS

External Interrupt 3

External Interrupt 5

38-45 P3.0-P3.7 Port 3 is a bidirectional I/O port (refer to P3DDRL, SFR B3H, and P3DDRH, SFR B4H, for port pin configuration control).

35, 36, 46 DV

DD

Port 3—Alternate Functions:

Digital Power Supply

PORT ALTERNATE MODE

P3.0 RxD0 Serial Port 0 Input
P3.1 TxD0 Serial Port 0 Output
P3.2
P3.3
P3.4 T0 Timer 0 External Input
P3.5 T1 Timer 1 External Input
P3.6 SCK/SCL/CLKS SCK/SCL/Various Clocks (refer to PASEL, SFR F2
P3.7 N/A

INT0
INT1

External Interrupt 0
External Interrupt 1

)

H

8

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MSC1200

SBAS289E

TYPICAL CHARACTERISTICS

22
21
20
19
18
17
16
15
14
13
12

EFFECTIVE NUMBER OF BITS

vs DECIMATION RATIO

Decimation Ratio =

f

MOD

f

DATA

0 500 1000 1500 2000

PGA4

ENOB (rms)

PGA1

PGA2

PGA16

PGA8

PGA32

PGA64 PGA128

Sinc3 Filter, Buffer OFF

22
21
20
19
18
17
16
15
14
13
12

EFFECTIVE NUMBER OF BITS

vs DECIMATION RATIO

0 500 1000 1500 2000

ENOB (rms)

PGA4

PGA8

PGA1

PGA2

PGA16

PGA32

PGA64

PGA128

Decimation Ratio =

f

MOD

f

DATA

AVDD = 3V, Sinc3 Filter,
V

REF

= 1.25V, Buffer OFF

22
21
20
19
18
17
16
15
14
13
12

EFFECTIVE NUMBER OF BITS

vs DECIMATION RATIO

0 500 1000 1500 2000

ENOB (rms)

PGA4

PGA8

PGA1

PGA2

PGA32

PGA128

PGA16 PGA64

Decimation Ratio =

f

MOD

f

DATA

Sinc2 Filter

AVDD = +5V, DVDD = +5V, f

EFFECTIVE NUMBER OF BITS vs DATA RATE
23
22
21
20
19
18
17
16
15

ENOB (rms)

14
13
12

Sinc3 Filter, Buffer OFF

11
10

1 10 100 1000

22
21

PGA2

PGA1

20
19
18
17
16

ENOB (rms)

15
14
13
12

0 500 1000 1500 2000

= 8MHz, PGA = 1, f

OSC

PGA1
PGA8

PGA32
PGA64

PGA128

Data Rate (SPS)

EFFECTIVE NUMBER OF BITS

vs DECIMATION RATIO

PGA32

PGA8

PGA64

PGA4

PGA16

Sinc3 Filter, Buffer ON

Decimation Ratio =

f

= 15.625kHz, Bipolar, Buffer ON, and V

MOD

PGA128

f

MOD
DATA

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

EFFECTIVE NUMBER OF BITS

vs DECIMATION RATIO

22
21

PGA2

PGA1

20
19
18
17
16

ENOB (rms)

15
14
13
12

0 500 1000 1500 2000

MSC1200

SBAS289E

PGA16

Decimation Ratio =

PGA4

PGA32

PGA8

PGA64

AVDD = 3V, Sinc3 Filter,
V

REF

PGA128

= 1.25V, Buffer ON

f

MOD

f

DATA

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9

TYPICAL CHARACTERISTICS (Cont.)

AVDD = +5V, DVDD = +5V, f

= 8MHz, PGA = 1, f

OSC

= 15.625kHz, Bipolar, Buffer ON, and V

MOD

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO

FAST SETTLING FILTER

22
21
20
19
18
17
16

ENOB (rms)

15
14
13

Fast Settling Filter

12

0 500 1000 1500 2000

Decimation Ratio =

EFFECTIVE NUMBER OF BITS vs f

WITH FIXED DECIMATION

25

DEC = 2020

DEC = 500

1500

f

MOD

f

DATA

(set with ACLK)

MOD

20

DEC = 50

DEC = 20

DEC = 10

15

10

ENOB (rms)

5

DEC = 255

0

10 100 1k 10k 100k

Data Rate (SPS)

EFFECTIVE NUMBER OF BITS vs f

(set with ACLK)

MOD

25

f

= 203kHz

f

MOD

MOD

= 62.5kHz

f

MOD

= 110kHz

20

15

10

ENOB (rms)

5

f

MOD

= 15.6kHz

f

= 31.25kHz

MOD

0

1 10 100 1k 10k 100k

Data Rate (SPS)

NOISE vs INPUT SIGNAL

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Noise (rms, ppm of FS)

0.1
0

–2.5 –1.5 0.5–0.5 1.5 2.5

(V)

V

IN

10

−2

INL (ppm of FS)

−4

−6

−8

−10

10

INTEGRAL NONLINEARITY vs INPUT SIGNAL

V

= 2.5V

8

REF

6
4
2

–40°C

+85°C

0

+25°C

−2.5 −2.0 −1.0 −0.5−1.5 0 0.5 1.0 1.5 2.0 2.5
(V)

V

IN

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15

10

5

0

−5

INL (ppm of FS)

−10

−15

= −V

V

IN

REF

INTEGRAL NONLINEARITY vs INPUT SIGNAL

V

= AVDD = 5V

REF

Buffer OFF

0V

V

(V)

IN

MSC1200

SBAS289E

IN

= +V

REF

TYPICAL CHARACTERISTICS (Cont.)

10

8
6
4
2
0

–2
–4
–6

–8
–10
–12

OFFSET DAC: OFFSET vs TEMPERATURE

Offset (ppm of FSR)

Temperature (°C)

–40 +25 +85

AVDD = +5V, DVDD = +5V, f

= 8MHz, PGA = 1, f

OSC

= 15.625kHz, Bipolar, Buffer ON, and V

MOD

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

30

ADC INTEGRAL NONLINEARITY vs V

25

Buffer OFF

20

15

10

INL (ppm of FS)

AVDD = 3V

AVDD = 5V

5

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

V

(V)

REF

ANALOG SUPPLY CURRENT

1.3

1.3

1.2

PGA = 128, ADC = ON

1.2

V

= ON, DBOR = ON

REF

ALVD = ON, IDAC = ON

1.1

1.1

1.0

Analog Supply Current (mA)

1.0

0.9

2.5 3.0 3.5 4.0 4.5 5.0 5.5
Analog Supply Voltage (V)

REF

VIN = V

+85°C

+25°C

–40°C

REF

50

AVDD = 5V

45

V

= 2.5V

REF

40
35
30
25
20

INL (ppm of FS)

15
10

5
0

142168 1286432

INL ERROR vs PGA

PGA Setting

ADC CURRENT vs PGA

0.8

0.7
AVDD = 5V, Buffer = ON

0.6

0.5

(µA)

0.4

ADC

I

0.3

AVDD = 3V, Buffer = ON

AVDD = 5V, Buffer = OFF

AVDD = 3V, Buffer = OFF

0.2

0.1

1824 3216 12864

PGA Setting

4500
4000
3500
3000
2500
2000
1500

Number of Occurrences

1000

500

0

–2

HISTOGRAM OF OUTPUT DATA

–1.5 –1 –0.5 0 0.5 1 1.5 2

MSC1200

SBAS289E

ppm of FS

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11

TYPICAL CHARACTERISTICS (Cont.)

AVDD = +5V, DVDD = +5V, f

= 8MHz, PGA = 1, f

OSC

= 15.625kHz, Bipolar, Buffer ON, and V

MOD

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

1.00006

1.00004

1.00002

1

0.99998

Normalized Gain

0.99996

0.99994
–40 +25 +85

100

Digital Supply Current (mA)

DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER

10

1

OFFSET DAC: GAIN vs TEMPERATURE

Temperature (°C)

Divider Values

1
2
4

8
16

32
1024

100

10

Digital Supply Current (mA)

0.1

10

Digital Supply Current (mA)

DIGITAL SUPPLY CURRENT vs FREQUENCY

1

DVDD = 5V

1 10 100

Clock Frequency (MHz)

DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE

8

+25°C

6

4

2

+85°C

–40°C

0.1
1 10 100

Clock Frequency (MHz)

NORMALIZED GAIN vs PGA

101

100

99

98

97

Normalized Gain (%)

96

95

142168 1286432

PGA Setting

Buffer ON

0

2.7 3.1 3.5 3.9 4.3 4.7 5.1
Supply Voltage (V)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

Output Voltage (V)

1.0

0.5
0

02010 4030 706050

CMOS DIGITAL OUTPUT

3V

Low

Output

3V

Output Current (mA)

5V

Low

Output

5V

12

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MSC1200

SBAS289E

TYPICAL CHARACTERISTICS (Cont.)

IO HF MODE vs FREQUENCY

Temperature (°C)

IO Frequency (MHz)

−40 25 85

28

27

26

25

24

23

4.75V

5.25V

AVDD = DV

DD

AVDD = +5V, DVDD = +5V, f

14

AVDD = DV

13

12

IO Frequency (MHz)

11

10

−40 25 85

IO LF MODE vs TEMPERATURE

DD

= 8MHz, PGA = 1, f

OSC

4.75V

Temperature (°C)

= 15.625kHz, Bipolar, Buffer ON, and V

MOD

5.25V

3.3V

2.7V

≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.

REF

MSC1200

SBAS289E

www.ti.com

13

DESCRIPTION

The MSC1200Yx is a completely integrated family of mixed­signal devices incorporating a high-resolution delta-sigma
ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect cur­rent sources, selectable buffered input, offset DAC, program­mable gain amplifier (PGA), temperature sensor, voltage
reference, 8-bit microcontroller, Flash Program Memory, Flash
Data Memory, and Data SRAM, as shown in Figure 1.

On-chip peripherals include an additional 32-bit accumulator,
basic SPI, basic I
ports, watchdog timer, low-voltage detect, on-chip power-on
reset, brownout reset, timer/counters, system clock divider,
PLL, on-chip oscillator, and external interrupts.

The device accepts low-level differential or single-ended
signals directly from a transducer. The ADC provides 24 bits
of resolution and 24 bits of no-missing-code performance
using a Sinc
ADC also has a selectable filter that allows for high-resolu­tion single-cycle conversion.

The microcontroller core is 8051 instruction set compatible. The
microcontroller core is an optimized 8051 core that executes up
to three times faster than the standard 8051 core, given the
same clock source. This makes it possible to run the device at
a lower external clock frequency and achieve the same perfor­mance at lower power than the standard 8051 core.

2

C, USART, multiple digital input/output

3

filter with a programmable sample rate. The

The MSC1200Yx allows the user to uniquely configure the
Flash memory map to meet the needs of their application.
The Flash is programmable down to 2.7V using serial pro­gramming. Flash endurance is typically 1M Erase/Write cycles.

The part has separate analog and digital supplies, which can
be independently powered from 2.7V to +5.25V. At +3V
operation, the power dissipation for the part is typically less
than 4mW. The MSC1200Yx is packaged in a TQFP-48
package.

The MSC1200Yx is designed for high-resolution measurement
applications in smart transmitters, industrial process control,
weigh scales, chromatography, and portable instrumentation.

ENHANCED 8051 CORE

All instructions in the MSC1200 family perform exactly the same
functions as they would in a standard 8051. The effect on bits,
flags, and registers is the same. However, the timing is different.
The MSC1200 family utilizes an efficient 8051 core which results
in an improved instruction execution speed of between 1.5 and
3 times faster than the original core for the same external clock
speed (4 clock cycles per instruction versus 12 clock cycles per
instruction, as shown in Figure 2). This translates into an effective
throughput improvement of more than 2.5 times, using the same
code and same external clock speed. Therefore, a device
frequency of 33MHz for the MSC1200Yx actually performs at an
equivalent execution speed of 82.5MHz compared to the

AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7

AINCOM

IDAC

FIGURE 1. Block Diagram.

instr_cycle

AGND REFOUT/REFIN+ REFIN– DVDDDGND

AV

DD

AV

DD

Burnout
Detect

Temperature

Sensor

MUX

AGND

NOTE (1) REF IN− must be tied to AGND when using internal V

CLK

BUFFER PGA

Burnout
Detect

8-Bit IDAC

n + 1 n + 2

V

REF

8-Bit

Offset DAC

REF

Modulator

4K or 8K

FLASH

128 Bytes

SRAM

.

POR

(1)

ALVD

DBOR

Digital

System

Clock

Divider

Filter

ACC

8051

SFR

Timers/

Counters

WDT

PORT1

PORT3

On-Chip

Oscillator

PLL

XIN XOUT

RST

CAP

Alternate
Functions

DIN
DOUT

SS
EXT (4)

PROG

USART
EXT (2)
T0
T1
SCK/SCL/CLKS

220pF Ceramic

cpu_cycle

FIGURE 2. Instruction Cycle Timing.

14

C1 C2 C3 C4 C1 C2 C3 C4 C1

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MSC1200

SBAS289E

standard 8051 core. This allows the user to run the device at
slower clock speeds, which reduces system noise and power
consumption, but provides greater throughput. This performance
difference can be seen in Figure 3. The timing of software loops
will be faster with the MSC1200. However, the timer/counter
operation of the MSC1200 may be maintained at 12 clocks per
increment or optionally run at 4 clocks per increment.

Single-Byte, Single-Cycle

Instruction

ALE

PSEN

Internal

AD0-AD7

Internal
A8-A15

4 Cycles

CLK

12 Cycles

ALE

PSEN

AD0-AD7

PORT 2

Standard 8051 Timing MSC1200 Timing

Single-Byte, Single-Cycle

Instruction

FIGURE 3. Comparison of MSC1200 Timing to Standard

8051 Timing.

The MSC1200 also provides dual data pointers (DPTRs).
Furthermore, improvements were made to peripheral fea-

tures that off-load processing from the core and the user, to
further improve efficiency. For instance, a 32-bit accumulator
was added to significantly reduce the processing overhead
for the multiple byte data from the ADC or other sources. This
allows for 24-bit addition and shifting to be accomplished in
a few instruction cycles, compared to hundreds of instruction
cycles through software implementation.

Family Device Compatibility

The hardware functionality and pin configuration across the
MSC1200 family is fully compatible. To the user, the only
difference between family members is the memory configuration.
This makes migration between family members simple. Code
written for the MSC1200Y2 can be executed directly on an
MSC1200Y3. This gives the user the ability to add or subtract
software functions and to freely migrate between family mem­bers. Thus, the MSC1200 can become a standard device used
across several application platforms.

Family Development Tools

The MSC1200 is fully compatible with the standard 8051
instruction set. This means that the user can develop soft­ware for the MSC1200 with existing 8051 development tools.
Additionally, a complete, integrated development environ­ment is provided with each demo board, and third-party
developers also provide support.

Power Down Modes

The MSC1200 can power several of the peripherals and put
the CPU into IDLE. This is accomplished by shutting off the
clocks to those sections, as shown in Figure 4.

t

SYS

SYSCLK

t

CLK

USEC

MSECH

ADC Power Down

PDCON.3

IDLE

C7

9A

Flash Write
Timing

Flash Erase
Timing

SECINT

WDTCON

SCL/SCK

(30µs to 40µs)

(5ms to 11ms)

milliseconds

interrupt

FA

ADC Output Rate

F9

FF

seconds

interrupt

watchdog

FD

ACLK

FB

MSECL

FC

F6

Timers 0/1

CPU Clock

PDCON.0

ms

PDCON.1

HMSEC

divide
by 64

Modulator Clock

SPICON/
I2CCON

µs

FE

ADCON3 ADCON2

FTCON
[3:0]

FTCON
[7:4]

100ms

PDCON.2

DF DE

Decimation Ratio

USART

EF

EF

MSINT

FIGURE 4. MSC1200 Timing Chain and Clock Control.

MSC1200

SBAS289E

www.ti.com

15

OVERVIEW

The MSC1200 ADC structure is shown in Figure 5. The figure lists the components that make up the ADC, along with the
corresponding special function register (SFR) associated with each component.

AV

DD

AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7

AINCOM

Input

Multiplexer

Temperature

Sensor

ADMUXD7

H

REFIN+ f

V

IN

∆Σ ADC

Modulator

REFIN−

Burnout

MOD

H
H
H

Burnout

Detect

Detect

ADCON1DD
ADCON2DE
ADCON3DF

In+
In−

AGND

f

DATA

FAST
SINC2
SINC3
AUTO

REFIN+

Buffer PGA

REFIN−

ADCON0DC

H

Σ X

Offset

Calibration

Register

OCR GCR ADRES

D3

HD2HD1H

Gain

Calibration

Register

D6HD5HD4HDBHDAHD9

f

SAMP

Sample

and Hold

ACLKF6

H

ADC

Result Register

H

Σ

Offset

DAC

ODACE6

H

Summation
Block

Σ

SUMR

E5HE4HE3HE2

E1

SSCON

H

H

FIGURE 5. MSC1200 ADC Structure.

16

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MSC1200

SBAS289E

INPUT MULTIPLEXER

R

SWITCH

(3kΩ typical)

Sampling Frequency = f

SAMP

High Impedance

> 1GΩ

C

S

AGND

A

IN

PGA f

SAMP

1, 2, 4 f

MOD

82 × f

MOD

16 4 × f

MOD

32 8 × f

MOD

64, 128 16 × f

MOD

PGA C

S

1 9pF
2 18pF

4 to 128 36pF

The input multiplexer provides for any combination of differential
inputs to be selected as the input channel, as shown in Figure 6.
If AIN0 is selected as the positive differential input channel, any
other channel can be selected as the negative differential input
channel. With this method, it is possible to have up to eight fully
differential input channels. It is also possible to switch the polarity
of the differential input pair to negate any offset voltages.

AIN0

AIN1

AIN2

AV

DD

Burnout Detect (2µA)

BURNOUT DETECT

When the Burnout Detect (BOD) bit is set in the ADC control
configuration register (ADCON0 DC

), two current sources are

H

enabled. The current source on the positive input channel sources
approximately 2µA of current. The current source on the negative
input channel sinks approximately 2µA. This allows for the
detection of an open circuit (full-scale reading) or short circuit
(small differential reading) on the selected input differential pair.
Enabling the buffer is recommended when BOD is enabled.

INPUT BUFFER

The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always pre­ferred.

The input impedance of the MSC1200 without the buffer
is 7MΩ/PGA. The buffer is controlled by the state of the BUF
bit in the ADC control register (ADCON0 DC

).

H

AIN3

In+

AIN4

In–

AIN5

AIN6

AGND

AIN7

AINCOM

Buffer

Burnout Detect (2µA)

Temperature Sensor

AV

DD

80 • I

AV

DD

I

FIGURE 6. Input Multiplexer Configuration.

In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the pins.

ANALOG INPUT

When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK
F6

) and gain (PGA). The relationship is:

H

A pedance

Im ( )Ω=

IN






where ACLK frequency (f

f

and f

MOD

=

ACLK

64

.

MHz

17

ACLKFrequencyMPGA

) =

ACLK

Figure 7 shows the basic input structure of the MSC1200.

f

CLK

ACLK

+1



Ω



•















TEMPERATURE SENSOR

On-chip diodes provide temperature sensing capability. When
the configuration register for the input MUX is set to all 1s,
the diodes are connected to the input of the ADC. All other
channels are open.

MSC1200

SBAS289E

FIGURE 7. Analog Input Structure (without buffer).

www.ti.com

17

PGA

The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective resolution
of the ADC. For instance, with a PGA of 1 on a ±2.5V full­scale range, the ADC can resolve to 1.5µV. With a PGA of
128 on a ±19mV full-scale range, the ADC can resolve to
75nV. With a PGA of 1 on a ±2.5V full-scale range, it would
require a 26-bit ADC to resolve 75nV, as shown in Table I.

PGA RANGE AT 10Hz RESOLUTION

FULL-SCALE ENOB MEASUREMENT

SETTING (V) (BITS) (nV)

1 ±2.5 21.7 1468
2 ±1.25 21.5 843
4 ±0.625 21.4 452

8 ±0.313 21.2 259
16 ±0.156 20.8 171
32 ±0.0781 20.4 113
64 ±0.039 20 74.5

128 ±0.019 19 74.5

RMS

TABLE I. ENOB Versus PGA.

OFFSET DAC

The analog output from the PGA can be offset by up to half
the full-scale input range of the PGA by using the ODAC
register (SFR E6
bit value; the MSB is the sign and the seven LSBs provide
the magnitude of the offset. Since the ODAC introduces an
analog (instead of digital) offset to the PGA, using the ODAC
does not reduce the range of the ADC.

). The ODAC (Offset DAC) register is an 8-

H

requires a positive full-scale differential input signal. It then
computes a gain value to nullify gain errors in the system.
Each of these calibrations will take seven t

periods to

DATA

complete.
Calibration should be performed after power on, a change in

temperature, power supply, voltage reference, decimation
ratio, buffer, or a change of the PGA. Calibration will remove
the effects of the Offset DAC; therefore, changes to the
Offset DAC register should be done after calibration.

At the completion of calibration, the ADC Interrupt bit goes
high, which indicates the calibration is finished and valid data
is available.

DIGITAL FILTER

The Digital Filter can use either the Fast Settling, Sinc2, or

3

Sinc

filter, as shown in Figure 8. In addition, the Auto mode
changes the Sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
Fast Settling filter, for the next two conversions the first of
which should be discarded. It will then use the Sinc
by the Sinc

3

filter to improve noise performance. This com­bines the low-noise advantage of the Sinc
quick response of the Fast Settling Time filter. The frequency
response of each filter is shown in Figure 9.

Adjustable Digital Filter

3

Sinc

2

followed

3

filter with the

MODULATOR

The modulator is a single-loop 2nd-order system. The modu­lator runs at a clock speed (f
using the value in the Analog Clock register (ACLK, F6

) that is derived from the CLK

MOD

H

The data output rate is:

f

MOD

DecimationRatio

f

=

where f

Data Rate = f

=

MOD

ACLK

()+•

=

DATA

f

CLK ACLK

164 64

CALIBRATION

The offset and gain errors in the MSC1200, or the complete
system, can be reduced with calibration. Calibration is con­trolled through the ADCON1 register (SFR DD
CAL2:CAL0. Each calibration process takes seven t
periods (data conversion time) to complete. Therefore, it
takes 14 t

periods to complete both an offset and gain

DATA

calibration.
For system calibration, the appropriate signal must be

applied to the inputs. The system offset calibration requires a
zero-differential input signal. It then computes an offset value
that will nullify offset in the system. The system gain calibration

), bits

H

DATA

Modulator

).

FILTER SETTLING TIME

FILTER (Conversion Cycles)

3

Sinc

2

Sinc

Fast 1

NOTE: (1) With Synchronized Channel Changes.

AUTO MODE FILTER SELECTION

1234+

Discard Fast Sinc

FIGURE 8. Filter Step Responses.

2

Sinc

Fast Settling

SETTLING TIME

CONVERSION CYCLE

Data Out

(1)

3

(1)

2

(1)

2

Sinc

3

18

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MSC1200

SBAS289E