Texas Instruments MICROPROCESSOR TI SITARA User Manual
TI
Sitara™ARM
Microprocessors
Microprocessors
Yair Hougui
Application Engineer
1
TI Embedded Processors Portfolio
TI Embedded Processors
TI Embedded Processors
Cortex
™-M3
low power
performance
Cortex
-
A8
DSPs
real
-
time
ARM
Cortex™
-
M3
& ARM9
OMAP
™
RAM, ROM
1 KB to 256 KB
Up to 128KB ROM
RAM, ROM
Piccolo
™
RAM, ROM
1 KB to 256 KB
Up to 128KB ROM
RAM, ROM
Software & Dev. Tools
16-bit ultra-
MCUs
MSP430
Up to
25 MHz
Flash
Analog I/O, ADC
LCD, USB, RF
Measurement,
Sensing, General
Purpose
™
32-bit
MCUs
C2000
Delfino
40MHz to
300 MHz
Flash, RAM
16 KB to 512 KB
PWM, ADC,
CAN, SPI, I2C
Motor Control,
Digital Power,
Lighting, Ren. Energy
™
™
ARM®-Based Processors
32-bit ARM
MCUs
Stellaris
®
Up to
100 MHz
Flash
64 KB to 256 KB
USB, ENET MAC+PHY
CAN, ADC, PWM, SPI
Connectivity, Security,
Motion Control, HMI,
Industrial Automation
®
ARM
MPUs
Sitara
ARM® Cortex™-A8
300MHz to
>1GHz
Cache,
USB, CAN,
PCIe, EMAC
Industrial computing,
POS & portable
data terminals
™
Digital Signal Processors (DSPs)Microcontrollers (MCUs)
High-
DSPs
C6000
DaVinci
300MHz to >1GHz
+Accelerator
USB, ENET,
PCIe, SATA, SPI
Test & Meas., Video,
audio, security,
imaging, infrastructure
™
™
Cache
Low-power
C5000
Up to 300 MHz
+Accelerator
Up to 320KB RAM
USB, ADC
McBSP, SPI, I2C
Port. Telecom, audio,
medical monitor
& diag, industrial
™
$0.49 to $9.00
MPUs – Microprocessors
$1.50 to $20.00
$1.00 to $8.00
$5.00 to $20.00
$5.00 to $200.00
$3.00 to $10.00
2
What is Sitara
•
Advanced graphical user interfaces
–
ARM9 to ARM
®
Cortex
™
-
A8 MPU’s
•
Coming soon:
•
And…
•
Coming soon:
building
of service
building
controls
measurement
board
™
?
What’s new
• New platform of high-performance
ARM microprocessors:
• First new devices:
– AM35xx & AM17xx/AM18xx
– , AM3703/AM3715
• Software compatible roadmap
Ideal for applications requiring
• High-level operating system
• 300MHz – 1GHz+ in future devices
• Flexible connectivity and multiple
interface options
• High system integration
• Scalability
• System cost constraints
• Application software portability
Sitara ARM MPUs – a good fit for industrial, instrumentation, POS
Industrial
automation
Medical
instrumentation
Point
HVAC and
Test &
Single
computing
3
Sitara
In Development
Available Now
AM1808
AM3517
•
Power efficient (down to 10mW
standby, 182mW active)
•
Integrated interfaces to display,
PCIe
Ethernet, USB, SATA, and many
™
ARM
®
microprocessors
AM1705
AM1707
AM1806
Low power ARM9 with
Integrated peripherals
• Power efficient (down to 7mW
• Cost efficient
• Flexible industrial I/O PRU (CAN,
UART)
• Integrated peripherals, 10/100
ARM Cortex-A8
OMAP3503
OMAP3515
AM3505
Advanced ARM Cortex-A8
with system integration
• Up to 1440 DMIPS
USB, 10/100 Ethernet, SD card,
Wi-Fi®, CAN, and many others
• Integrated graphics for rich user
interface functions
ARM Cortex-A8ARM9
AM37xx (2Q10)
“AM38x Next” (2011)
“AM33x Next” (2011)
Higher Performance Cortex-
A8 with enhanced integration
• Up to 2000 DMIPS
standby, 1W active)
• Enhanced graphics/UI
• Enhanced integrated
peripherals, 1Gb Ethernet,
more
4
Develop product designs with TI’s
expanding Sitara
MPU portfolio
expanding Sitara
MPU portfolio
AM18x
Performance
processor
•
Starting @ $5 (1ku)
™
ARM926
AM17x
• Power and cost-efficient
• Flexible industrial I/O
• Up to 450 MHz (495 DMIPS)
Cortex™-A8
AM37x
Sampling
AM35x
• High performance general purpose
• Advanced graphics/UI
• Roadmap to > 1 GHz (>2000 DMIPS)
Linux and Windows®Embedded CE kernel & drivers
Example code & demos
Now
Sampling
5
CORTEX-A8
PRODUCT DETAILS
6
AM3517/05 Core and Accelerators
Cores
ARM
®
Display Subsystem
Cores
16-bit Video
Processing
polygons
/ second
USB HS Host x2
Timers
HDQ /
CAN
McBSP x5
16
kB
I-Cache; 16
kB
D-Cache;
GPMC: NAND/NOR I/F
•
Easily create robust GUI’s
Multi window overlay system and
resizing for hardware accelerated
user interfaces
AM3517/05
processors
600 MHz Cortex A-8 with NEON™
coprocessor
PowerVR SGX 3D graphics
Accelerator – up to 10M
Up to 1000 Dhrystone MIPS:
• OS’s like Linux or WinCE
• Excellent web experience
Memory
ARM:
256kB L2 Cache
On chip: 64kB SRAM; 128kB
ROM
DDR2 interface
• Up to 10M polygons per second
• Hardware based on screen display
Cortex™-
A8
EMAC
I2C x3
McSPI x4
Graphics
Accelerator
L3/L4 Interconnect
GP x12
WDT x1
UARTx3
+1 w/IrDA
3D
(3517)
1-wire
DDR2
GPMC
LCD
Video
Controller
Front End
Enc
Video
USB OTG
w/PHY
MMC/SD/
SDIO x3
10 bit DAC
10 bit DAC
Input
7
AM3517/05 Peripherals
Peripherals
(3517)
Video
RMII EMAC controller 10/100
(3517)
16-bit Video
Video
Display subsystem with PIP,
Timers
HDQ /
CAN
McBSP x5
plus design rules.
CAN – High end controller area
network Controller (HECC)
USB 2.0 OTG w/PHY
AM3517/05
processors
USB HS host x2
MMC/SD card interface x3
LCD controller and TV out
color space conversion, rotation,
resizing
1.8V or 3.3V IO
Power
Total Power: 0.5W – 1.5W
Standby Power: 12mW
Package
ZCN – 17x17 mm, 0.65 mm pitch
Utilizes Via Channel™ Array
Technology with 0.8mm pitch
ARM
Cortex™-
A8
EMAC
I2C x3
McSPI x4
®
GP x12
WDT x1
3D
Graphics
Accelerator
L3/L4 Interconnect
1-wire
UARTx3
+1 w/IrDA
DDR2
GPMC
Display Subsystem
LCD
Controller
Processing
Front End
Video
Enc
10 bit DAC
10 bit DAC
Input
USB HS Host x2
USB OTG
w/PHY
MMC/SD/
SDIO x3
ZER – 23x23 mm, 1.0mm pitch.
8
AM3505/17 Platforms
AM3505
Cortex
-
A8
Peripherals
Pin-for-pin compatible
™
AM
AM3517
™
AM
Applications
Software
Compatibility
ARM
Cortex-A8
600 MHz
ARM
Shared
Peripheral
Set
Peripherals
3D
Graphics
Compatibility
Graphics
Open GL ES 2.0
600 MHz
Availability subject to applicable lead times
9
CORTEX A-8 : Highlights
–
Advanced dynamic Branch prediction
–
Dedicated, low
-
latency, high
-
BW interface to L1 cache
–
Dedicated, low
-
latency, high
-
BW interface to L1 cache
–
Adds new instructions to convert between fixed and floating point
–
Jazelle
-
RCT: Target for Java. Memory footprint reduced up to 3x
–
Jazelle
-
RCT: Target for Java. Memory footprint reduced up to 3x
• First ARMv7 instruction-set architecture
• Superscalar architecture delivers high performance
• 256 KB unified L2 cache
• Enhanced VFPv3
– Doubles number of double-precision registers
• Efficient Run Time Compilation Target
• Trust Zone
– Normal & Secure worlds have different memory views
10
AM35x Memory Controller
controllers/one
internal
–
General purpose
memory
•
Operates
at full L3
interconnect
• Two dedicated memory
memory
– SDRAM controller (EMIF4)
controller (GPMC)
– Internal memory (SRAM)
• On Chip Memory [SRAM-64 Kb]
(64bit@Core Clock /2)
11
GPMC Controller
•
GPMC can communicate with
mux
mode)
bit wide memory/device
–
External 16
-
bit non
-
multiplexed device
multiplexed NOR flash device
–
External 16
-
bit pseudo SRAM
Data Width
16 b
–
External 16
-
bit pseudo SRAM
• 16-bit external memory
controller
AM35x
Supported PsRAM, OneNAND,
NOR/NAND Flash,
many external devices:
– External asynchronous/synchronous 8-
– External asynchronous/synchronous
16-bit wide memory/device
with limited address range (2 Kbytes)
– External 16-bit address/data-
– External 8-bit/16-bit NAND flash
device
ASYNC Logic
1GB (128MB per CS-
Supported Size
(bits)
Max Clock
Speed
Chip Selects 8
Max Address
Space
16 KB (2 KB per CS
non-mux
100 MHz
2 KB non mux mode
128 MB mux mode
mode)
(pSRAM) device
12
DDR Controller
AM3517/05
•
DDR
controller has three
Supported
•
DDR
controller has three
64M, 128M, 256M,
0
, 90
, 180
,270
64M, 128M, 256M,
•
Optimizes latency and
Speed
Data Width
–
SDRAM Controller
Data Width
•
Two chip selects
• Supports mDDR / DDR2
SDRAM
mDDR/DDR2
functional blocks:
– Virtual Rotated Frame Buffer
(VRFB), supporting rotations of
– SDRAM memory-access
scheduler (SMS)
bandwidth usage among
requestors
• Physical interface to DDR2 or
mDDR
Measured
Throughput
Supported
Size (bits)
Max Clock
Chip Selects
810MB/sec
16M, 32M (2
Banks)
512M,1G,
2G (4 Banks)
166MHz
2
16/32b
13
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