TEXAS INSTRUMENTS LM3S2950 Technical data
PRELIMINARY
LM3S2950 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S2950-1972
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Preliminary
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LM3S2950 Microcontroller
Table of Contents
About This Document .................................................................................................................... 20
Audience .............................................................................................................................................. 20
About This Manual ................................................................................................................................ 20
Related Documents ............................................................................................................................... 20
Documentation Conventions .................................................................................................................. 20
1 Architectural Overview ...................................................................................................... 22
1.1 Product Features ...................................................................................................................... 22
1.2 Target Applications .................................................................................................................... 28
1.3 High-Level Block Diagram ......................................................................................................... 28
1.4 Functional Overview .................................................................................................................. 29
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 30
1.4.2 Motor Control Peripherals .......................................................................................................... 30
1.4.3 Analog Peripherals .................................................................................................................... 31
1.4.4 Serial Communications Peripherals ............................................................................................ 32
1.4.5 System Peripherals ................................................................................................................... 33
1.4.6 Memory Peripherals .................................................................................................................. 34
1.4.7 Additional Features ................................................................................................................... 34
1.4.8 Hardware Details ...................................................................................................................... 35
2 ARM Cortex-M3 Processor Core ...................................................................................... 36
2.1 Block Diagram .......................................................................................................................... 37
2.2 Functional Description ............................................................................................................... 37
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 37
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 38
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 38
2.2.4 ROM Table ............................................................................................................................... 38
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 38
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 38
3 Memory Map ....................................................................................................................... 42
4 Interrupts ............................................................................................................................ 44
5 JTAG Interface .................................................................................................................... 47
5.1 Block Diagram .......................................................................................................................... 48
5.2 Functional Description ............................................................................................................... 48
5.2.1 JTAG Interface Pins .................................................................................................................. 49
5.2.2 JTAG TAP Controller ................................................................................................................. 50
5.2.3 Shift Registers .......................................................................................................................... 51
5.2.4 Operational Considerations ........................................................................................................ 51
5.3 Initialization and Configuration ................................................................................................... 54
5.4 Register Descriptions ................................................................................................................ 54
5.4.1 Instruction Register (IR) ............................................................................................................. 54
5.4.2 Data Registers .......................................................................................................................... 56
6 System Control ................................................................................................................... 58
6.1 Functional Description ............................................................................................................... 58
6.1.1 Device Identification .................................................................................................................. 58
6.1.2 Reset Control ............................................................................................................................ 58
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6.1.3 Power Control ........................................................................................................................... 61
6.1.4 Clock Control ............................................................................................................................ 61
6.1.5 System Control ......................................................................................................................... 63
6.2 Initialization and Configuration ................................................................................................... 64
6.3 Register Map ............................................................................................................................ 64
6.4 Register Descriptions ................................................................................................................ 65
7 Hibernation Module .......................................................................................................... 117
7.1 Block Diagram ........................................................................................................................ 118
7.2 Functional Description ............................................................................................................. 118
7.2.1 Register Access Timing ........................................................................................................... 118
7.2.2 Clock Source .......................................................................................................................... 119
7.2.3 Battery Management ............................................................................................................... 119
7.2.4 Real-Time Clock ...................................................................................................................... 119
7.2.5 Non-Volatile Memory ............................................................................................................... 120
7.2.6 Power Control ......................................................................................................................... 120
7.2.7 Interrupts and Status ............................................................................................................... 120
7.3 Initialization and Configuration ................................................................................................. 121
7.3.1 Initialization ............................................................................................................................. 121
7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 121
7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 121
7.3.4 External Wake-Up from Hibernation .......................................................................................... 122
7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 122
7.4 Register Map .......................................................................................................................... 122
7.5 Register Descriptions .............................................................................................................. 123
8 Internal Memory ............................................................................................................... 136
8.1 Block Diagram ........................................................................................................................ 136
8.2 Functional Description ............................................................................................................. 136
8.2.1 SRAM Memory ........................................................................................................................ 136
8.2.2 Flash Memory ......................................................................................................................... 137
8.3 Flash Memory Initialization and Configuration ........................................................................... 138
8.3.1 Flash Programming ................................................................................................................. 138
8.3.2 Nonvolatile Register Programming ........................................................................................... 139
8.4 Register Map .......................................................................................................................... 139
8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 140
8.6 Flash Register Descriptions (System Control Offset) .................................................................. 147
9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 160
9.1 Functional Description ............................................................................................................. 160
9.1.1 Data Control ........................................................................................................................... 161
9.1.2 Interrupt Control ...................................................................................................................... 162
9.1.3 Mode Control .......................................................................................................................... 163
9.1.4 Commit Control ....................................................................................................................... 163
9.1.5 Pad Control ............................................................................................................................. 163
9.1.6 Identification ........................................................................................................................... 163
9.2 Initialization and Configuration ................................................................................................. 163
9.3 Register Map .......................................................................................................................... 164
9.4 Register Descriptions .............................................................................................................. 166
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10 General-Purpose Timers ................................................................................................. 201
10.1 Block Diagram ........................................................................................................................ 201
10.2 Functional Description ............................................................................................................. 202
10.2.1 GPTM Reset Conditions .......................................................................................................... 203
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 203
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 204
10.3 Initialization and Configuration ................................................................................................. 208
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 208
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 209
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 209
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 210
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 210
10.3.6 16-Bit PWM Mode ................................................................................................................... 211
10.4 Register Map .......................................................................................................................... 211
10.5 Register Descriptions .............................................................................................................. 212
11 Watchdog Timer ............................................................................................................... 237
11.1 Block Diagram ........................................................................................................................ 237
11.2 Functional Description ............................................................................................................. 237
11.3 Initialization and Configuration ................................................................................................. 238
11.4 Register Map .......................................................................................................................... 238
11.5 Register Descriptions .............................................................................................................. 239
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 260
12.1 Block Diagram ........................................................................................................................ 261
12.2 Functional Description ............................................................................................................. 261
12.2.1 Transmit/Receive Logic ........................................................................................................... 261
12.2.2 Baud-Rate Generation ............................................................................................................. 262
12.2.3 Data Transmission .................................................................................................................. 263
12.2.4 Serial IR (SIR) ......................................................................................................................... 263
12.2.5 FIFO Operation ....................................................................................................................... 264
12.2.6 Interrupts ................................................................................................................................ 264
12.2.7 Loopback Operation ................................................................................................................ 265
12.2.8 IrDA SIR block ........................................................................................................................ 265
12.3 Initialization and Configuration ................................................................................................. 265
12.4 Register Map .......................................................................................................................... 266
12.5 Register Descriptions .............................................................................................................. 267
13 Synchronous Serial Interface (SSI) ................................................................................ 301
13.1 Block Diagram ........................................................................................................................ 301
13.2 Functional Description ............................................................................................................. 301
13.2.1 Bit Rate Generation ................................................................................................................. 302
13.2.2 FIFO Operation ....................................................................................................................... 302
13.2.3 Interrupts ................................................................................................................................ 302
13.2.4 Frame Formats ....................................................................................................................... 303
13.3 Initialization and Configuration ................................................................................................. 310
13.4 Register Map .......................................................................................................................... 311
13.5 Register Descriptions .............................................................................................................. 312
14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 338
14.1 Block Diagram ........................................................................................................................ 338
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14.2 Functional Description ............................................................................................................. 338
14.2.1 I2C Bus Functional Overview .................................................................................................... 339
14.2.2 Available Speed Modes ........................................................................................................... 341
14.2.3 Interrupts ................................................................................................................................ 342
14.2.4 Loopback Operation ................................................................................................................ 342
14.2.5 Command Sequence Flow Charts ............................................................................................ 343
14.3 Initialization and Configuration ................................................................................................. 349
14.4 I2C Register Map ..................................................................................................................... 350
14.5 Register Descriptions (I2C Master) ........................................................................................... 351
14.6 Register Descriptions (I2C Slave) ............................................................................................. 364
15 Controller Area Network (CAN) Module ......................................................................... 373
15.1 Controller Area Network Overview ............................................................................................ 373
15.2 Controller Area Network Features ............................................................................................ 373
15.3 Controller Area Network Block Diagram .................................................................................... 374
15.4 Controller Area Network Functional Description ......................................................................... 375
15.4.1 Initialization ............................................................................................................................. 375
15.4.2 Operation ............................................................................................................................... 376
15.4.3 Transmitting Message Objects ................................................................................................. 376
15.4.4 Configuring a Transmit Message Object .................................................................................... 376
15.4.5 Updating a Transmit Message Object ....................................................................................... 377
15.4.6 Accepting Received Message Objects ...................................................................................... 377
15.4.7 Receiving a Data Frame .......................................................................................................... 378
15.4.8 Receiving a Remote Frame ...................................................................................................... 378
15.4.9 Receive/Transmit Priority ......................................................................................................... 378
15.4.10 Configuring a Receive Message Object .................................................................................... 378
15.4.11 Handling of Received Message Objects .................................................................................... 379
15.4.12 Handling of Interrupts .............................................................................................................. 379
15.4.13 Bit Timing Configuration Error Considerations ........................................................................... 380
15.4.14 Bit Time and Bit Rate ............................................................................................................... 380
15.4.15 Calculating the Bit Timing Parameters ...................................................................................... 382
15.5 Controller Area Network Register Map ...................................................................................... 384
15.6 Register Descriptions .............................................................................................................. 386
16 Analog Comparators ....................................................................................................... 414
16.1 Block Diagram ........................................................................................................................ 415
16.2 Functional Description ............................................................................................................. 415
16.2.1 Internal Reference Programming .............................................................................................. 417
16.3 Initialization and Configuration ................................................................................................. 418
16.4 Register Map .......................................................................................................................... 418
16.5 Register Descriptions .............................................................................................................. 419
17 Pulse Width Modulator (PWM) ........................................................................................ 427
17.1 Block Diagram ........................................................................................................................ 427
17.2 Functional Description ............................................................................................................. 427
17.2.1 PWM Timer ............................................................................................................................. 427
17.2.2 PWM Comparators .................................................................................................................. 428
17.2.3 PWM Signal Generator ............................................................................................................ 429
17.2.4 Dead-Band Generator ............................................................................................................. 430
17.2.5 Interrupt Selector ..................................................................................................................... 430
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17.2.6 Synchronization Methods ......................................................................................................... 430
17.2.7 Fault Conditions ...................................................................................................................... 431
17.2.8 Output Control Block ............................................................................................................... 431
17.3 Initialization and Configuration ................................................................................................. 431
17.4 Register Map .......................................................................................................................... 432
17.5 Register Descriptions .............................................................................................................. 434
18 Quadrature Encoder Interface (QEI) ............................................................................... 463
18.1 Block Diagram ........................................................................................................................ 463
18.2 Functional Description ............................................................................................................. 464
18.3 Initialization and Configuration ................................................................................................. 466
18.4 Register Map .......................................................................................................................... 466
18.5 Register Descriptions .............................................................................................................. 467
19 Pin Diagram ...................................................................................................................... 480
20 Signal Tables .................................................................................................................... 481
21 Operating Characteristics ............................................................................................... 496
22 Electrical Characteristics ................................................................................................ 497
22.1 DC Characteristics .................................................................................................................. 497
22.1.1 Maximum Ratings ................................................................................................................... 497
22.1.2 Recommended DC Operating Conditions .................................................................................. 497
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 498
22.1.4 Power Specifications ............................................................................................................... 498
22.1.5 Flash Memory Characteristics .................................................................................................. 500
22.2 AC Characteristics ................................................................................................................... 500
22.2.1 Load Conditions ...................................................................................................................... 500
22.2.2 Clocks .................................................................................................................................... 500
22.2.3 Analog Comparator ................................................................................................................. 501
22.2.4 I2C ......................................................................................................................................... 501
22.2.5 Hibernation Module ................................................................................................................. 502
22.2.6 Synchronous Serial Interface (SSI) ........................................................................................... 503
22.2.7 JTAG and Boundary Scan ........................................................................................................ 504
22.2.8 General-Purpose I/O ............................................................................................................... 506
22.2.9 Reset ..................................................................................................................................... 506
23 Package Information ........................................................................................................ 509
A Serial Flash Loader .......................................................................................................... 511
A.1 Serial Flash Loader ................................................................................................................. 511
A.2 Interfaces ............................................................................................................................... 511
A.2.1 UART ..................................................................................................................................... 511
A.2.2 SSI ......................................................................................................................................... 511
A.3 Packet Handling ...................................................................................................................... 512
A.3.1 Packet Format ........................................................................................................................ 512
A.3.2 Sending Packets ..................................................................................................................... 512
A.3.3 Receiving Packets ................................................................................................................... 512
A.4 Commands ............................................................................................................................. 513
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 513
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 513
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 513
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A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 514
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 514
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 514
B Register Quick Reference ............................................................................................... 516
C Ordering and Contact Information ................................................................................. 535
C.1 Ordering Information ................................................................................................................ 535
C.2 Kits ......................................................................................................................................... 535
C.3 Company Information .............................................................................................................. 535
C.4 Support Information ................................................................................................................. 536
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LM3S2950 Microcontroller
List of Figures
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram ............................................................... 29
Figure 2-1. CPU Block Diagram ......................................................................................................... 37
Figure 2-2. TPIU Block Diagram ........................................................................................................ 38
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 48
Figure 5-2. Test Access Port State Machine ....................................................................................... 51
Figure 5-3. IDCODE Register Format ................................................................................................. 56
Figure 5-4. BYPASS Register Format ................................................................................................ 57
Figure 5-5. Boundary Scan Register Format ....................................................................................... 57
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 59
Figure 7-1. Hibernation Module Block Diagram ................................................................................. 118
Figure 8-1. Flash Block Diagram ...................................................................................................... 136
Figure 9-1. GPIO Port Block Diagram ............................................................................................... 161
Figure 9-2. GPIODATA Write Example ............................................................................................. 162
Figure 9-3. GPIODATA Read Example ............................................................................................. 162
Figure 10-1. GPTM Module Block Diagram ........................................................................................ 202
Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 206
Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 207
Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 208
Figure 11-1. WDT Module Block Diagram .......................................................................................... 237
Figure 12-1. UART Module Block Diagram ......................................................................................... 261
Figure 12-2. UART Character Frame ................................................................................................. 262
Figure 12-3. IrDA Data Modulation ..................................................................................................... 264
Figure 13-1. SSI Module Block Diagram ............................................................................................. 301
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 303
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 304
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 305
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 305
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 306
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 307
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 307
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 308
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 309
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 310
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 310
Figure 14-1. I2C Block Diagram ......................................................................................................... 338
Figure 14-2. I2C Bus Configuration .................................................................................................... 339
Figure 14-3. START and STOP Conditions ......................................................................................... 339
Figure 14-4. Complete Data Transfer with a 7-Bit Address ................................................................... 340
Figure 14-5. R/S Bit in First Byte ........................................................................................................ 340
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 340
Figure 14-7. Master Single SEND ...................................................................................................... 343
Figure 14-8. Master Single RECEIVE ................................................................................................. 344
Figure 14-9. Master Burst SEND ....................................................................................................... 345
Figure 14-10. Master Burst RECEIVE .................................................................................................. 346
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 347
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Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 348
Figure 14-13. Slave Command Sequence ............................................................................................ 349
Figure 15-1. CAN Module Block Diagram ........................................................................................... 374
Figure 15-2. CAN Bit Time ................................................................................................................ 381
Figure 16-1. Analog Comparator Module Block Diagram ..................................................................... 415
Figure 16-2. Structure of Comparator Unit .......................................................................................... 416
Figure 16-3. Comparator Internal Reference Structure ........................................................................ 417
Figure 17-1. PWM Module Block Diagram .......................................................................................... 427
Figure 17-2. PWM Count-Down Mode ................................................................................................ 428
Figure 17-3. PWM Count-Up/Down Mode .......................................................................................... 429
Figure 17-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 429
Figure 17-5. PWM Dead-Band Generator ........................................................................................... 430
Figure 18-1. QEI Block Diagram ........................................................................................................ 463
Figure 18-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 465
Figure 19-1. Pin Connection Diagram ................................................................................................ 480
Figure 22-1. Load Conditions ............................................................................................................ 500
Figure 22-2. I2C Timing ..................................................................................................................... 502
Figure 22-3. Hibernation Module Timing ............................................................................................. 503
Figure 22-4. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 503
Figure 22-5. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 504
Figure 22-6. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 504
Figure 22-7. JTAG Test Clock Input Timing ......................................................................................... 505
Figure 22-8. JTAG Test Access Port (TAP) Timing .............................................................................. 506
Figure 22-9. JTAG TRST Timing ........................................................................................................ 506
Figure 22-10. External Reset Timing (RST) .......................................................................................... 507
Figure 22-11. Power-On Reset Timing ................................................................................................. 507
Figure 22-12. Brown-Out Reset Timing ................................................................................................ 507
Figure 22-13. Software Reset Timing ................................................................................................... 508
Figure 22-14. Watchdog Reset Timing ................................................................................................. 508
Figure 23-1. 100-Pin LQFP Package .................................................................................................. 509
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LM3S2950 Microcontroller
List of Tables
Table 1. Documentation Conventions ............................................................................................ 20
Table 3-1. Memory Map ................................................................................................................... 42
Table 4-1. Exception Types .............................................................................................................. 44
Table 4-2. Interrupts ........................................................................................................................ 45
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 49
Table 5-2. JTAG Instruction Register Commands ............................................................................... 54
Table 6-1. System Control Register Map ........................................................................................... 64
Table 7-1. Hibernation Module Register Map ................................................................................... 122
Table 8-1. Flash Protection Policy Combinations ............................................................................. 138
Table 8-2. Flash Resident Registers ............................................................................................... 139
Table 8-3. Flash Register Map ........................................................................................................ 139
Table 9-1. GPIO Pad Configuration Examples ................................................................................. 163
Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 164
Table 9-3. GPIO Register Map ....................................................................................................... 165
Table 10-1. Available CCP Pins ........................................................................................................ 202
Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 205
Table 10-3. Timers Register Map ...................................................................................................... 211
Table 11-1. Watchdog Timer Register Map ........................................................................................ 238
Table 12-1. UART Register Map ....................................................................................................... 266
Table 13-1. SSI Register Map .......................................................................................................... 312
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 341
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 350
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 355
Table 15-1. Transmit Message Object Bit Settings ............................................................................. 377
Table 15-2. Receive Message Object Bit Settings .............................................................................. 379
Table 15-3. CAN Protocol Ranges .................................................................................................... 381
Table 15-4. CAN Register Map ......................................................................................................... 384
Table 16-1. Comparator 0 Operating Modes ...................................................................................... 416
Table 16-2. Comparator 1 Operating Modes ...................................................................................... 416
Table 16-3. Comparator 2 Operating Modes ...................................................................................... 417
Table 16-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 417
Table 16-5. Analog Comparators Register Map ................................................................................. 419
Table 17-1. PWM Register Map ........................................................................................................ 432
Table 18-1. QEI Register Map .......................................................................................................... 466
Table 20-1. Signals by Pin Number ................................................................................................... 481
Table 20-2. Signals by Signal Name ................................................................................................. 485
Table 20-3. Signals by Function, Except for GPIO ............................................................................. 490
Table 20-4. GPIO Pins and Alternate Functions ................................................................................. 494
Table 21-1. Temperature Characteristics ........................................................................................... 496
Table 21-2. Thermal Characteristics ................................................................................................. 496
Table 22-1. Maximum Ratings .......................................................................................................... 497
Table 22-2. Recommended DC Operating Conditions ........................................................................ 497
Table 22-3. LDO Regulator Characteristics ....................................................................................... 498
Table 22-4. Detailed Power Specifications ........................................................................................ 499
Table 22-5. Flash Memory Characteristics ........................................................................................ 500
Table 22-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 500
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Table of Contents
Table 22-7. Clock Characteristics ..................................................................................................... 500
Table 22-8. Crystal Characteristics ................................................................................................... 501
Table 22-9. Analog Comparator Characteristics ................................................................................. 501
Table 22-10. Analog Comparator Voltage Reference Characteristics .................................................... 501
Table 22-11. I2C Characteristics ......................................................................................................... 501
Table 22-12. Hibernation Module Characteristics ................................................................................. 502
Table 22-13. SSI Characteristics ........................................................................................................ 503
Table 22-14. JTAG Characteristics ..................................................................................................... 504
Table 22-15. GPIO Characteristics ..................................................................................................... 506
Table 22-16. Reset Characteristics ..................................................................................................... 506
Table C-1. Part Ordering Information ............................................................................................... 535
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LM3S2950 Microcontroller
List of Registers
System Control .............................................................................................................................. 58
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 66
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 68
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 69
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 70
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 71
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 72
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 73
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 74
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 78
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 79
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 81
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 82
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 84
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 85
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 87
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 89
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 91
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 92
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 94
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 96
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 98
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 101
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 104
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 107
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 109
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 111
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 113
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 114
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 116
Hibernation Module ..................................................................................................................... 117
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 124
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 125
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 126
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 127
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 128
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 130
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 131
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 132
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 133
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 134
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 135
Internal Memory ........................................................................................................................... 136
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 141
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 142
Preliminary
13November 30, 2007
Table of Contents
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 143
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 145
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 146
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 147
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 148
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 149
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 150
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 151
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 152
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 153
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 154
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 155
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 156
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 157
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 158
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 159
General-Purpose Input/Outputs (GPIOs) ................................................................................... 160
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 167
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 168
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 169
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 170
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 171
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 172
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 173
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 174
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 175
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 176
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 178
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 179
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 180
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 181
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 182
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 183
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 184
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 185
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 186
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 187
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 189
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 190
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 191
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 192
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 193
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 194
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 195
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 196
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 197
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 198
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 199
Preliminary
November 30, 200714
LM3S2950 Microcontroller
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 200
General-Purpose Timers ............................................................................................................. 201
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 213
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 214
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 216
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 218
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 221
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 223
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 224
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 225
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 227
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 228
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 229
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 230
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 231
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 232
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 233
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 234
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 235
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 236
Watchdog Timer ........................................................................................................................... 237
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 240
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 241
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 242
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 243
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 244
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 245
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 246
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 247
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 248
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 249
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 250
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 251
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 252
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 253
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 254
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 255
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 256
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 257
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 258
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 259
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 260
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 268
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 270
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 272
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 274
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 275
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 276
Preliminary
15November 30, 2007
Table of Contents
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 277
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 279
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 281
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 283
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 285
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 286
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 287
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 289
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 290
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 291
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 292
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 293
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 294
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 295
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 296
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 297
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 298
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 299
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 300
Synchronous Serial Interface (SSI) ............................................................................................ 301
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 313
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 315
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 317
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 318
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 320
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 321
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 323
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 324
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 325
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 326
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 327
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 328
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 329
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 330
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 331
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 332
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 333
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 334
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 335
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 336
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 337
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 338
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 352
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 353
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 357
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 358
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 359
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 360
Preliminary
November 30, 200716
LM3S2950 Microcontroller
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 361
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 362
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 363
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 365
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 366
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 368
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 369
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 370
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 371
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 372
Controller Area Network (CAN) Module ..................................................................................... 373
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 387
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 389
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 392
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 393
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 395
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 396
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 398
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 399
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 399
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 400
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 400
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 403
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 403
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 404
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 404
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 405
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 405
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 406
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 406
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 407
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 407
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 409
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 409
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 409
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 409
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 409
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 409
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 409
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 409
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 410
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 410
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 411
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 411
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 412
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 412
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 413
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 413
Preliminary
17November 30, 2007
Table of Contents
Analog Comparators ................................................................................................................... 414
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 420
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 421
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 422
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 423
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 424
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 424
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 424
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 425
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 425
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 425
Pulse Width Modulator (PWM) .................................................................................................... 427
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 435
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 436
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 437
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 438
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 439
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 440
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 441
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 442
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 443
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 444
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 444
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 444
Register 13: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 446
Register 14: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084 ...................................................... 446
Register 15: PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4 ...................................................... 446
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 448
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 448
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 448
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 449
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 449
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 449
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 450
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 450
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 450
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 451
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 451
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 451
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 452
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 452
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 452
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 453
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 453
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 453
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 454
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 454
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 454
Preliminary
November 30, 200718
LM3S2950 Microcontroller
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 457
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 457
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 457
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 460
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 460
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 460
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 461
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 461
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 461
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 462
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 462
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 462
Quadrature Encoder Interface (QEI) .......................................................................................... 463
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 468
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 470
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 471
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 472
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 473
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 474
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 475
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 476
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 477
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 478
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 479
Preliminary
19November 30, 2007
About This Document
About This Document
This data sheet provides reference information for the LM3S2950 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 20.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 42.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
November 30, 200720
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
LM3S2950 Microcontroller
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
21November 30, 2007
Architectural Overview
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
®
The LM3S2950 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S2950 microcontroller features
a Battery-backed Hibernation module to efficiently power down the LM3S2950 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S2950 microcontroller perfectly for
battery applications.
In addition, the LM3S2950 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S2950 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S2950 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
November 30, 200722
Preliminary
LM3S2950 Microcontroller
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 36 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 256 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 64 KB single-cycle SRAM
■ General-Purpose Timers
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
23November 30, 2007
Preliminary
Architectural Overview
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Controller Area Network (CAN)
– Supports CAN protocol version 2.0 part A/B
– Bit rates up to 1Mb/s
– 32 message objects, each with its own identifier mask
– Maskable interrupt
– Disable automatic retransmission mode for TTCAN
– Programmable loop-back mode for self-test operation
■ Synchronous Serial Interface (SSI)
– Two SSI modules, each with the following features:
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Preliminary
November 30, 200724
LM3S2950 Microcontroller
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ Analog Comparators
– Three independent integrated analog comparators
– Configurable for output to: drive an output pin or generate an interrupt
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM
generator, and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
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25November 30, 2007
Architectural Overview
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
PWM comparator output signals
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
■ QEI
– Hardware position integrator tracks the encoder position
– Velocity capture using built-in timer
– Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
■ GPIOs
– 10-60 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
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Preliminary
LM3S2950 Microcontroller
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
Preliminary
27November 30, 2007
Architectural Overview
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 29 represents the full set of features in the Stellaris®2000 series of devices;
not all features may be available on the LM3S2950 microcontroller.
Preliminary
November 30, 200728
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram
LM3S2950 Microcontroller
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S2950 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 535.
29November 30, 2007
Preliminary
Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 36)
All members of the Stellaris®product family, including the LM3S2950 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 36 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S2950 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 36 interrupts.
“Interrupts” on page 44 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S2950 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
November 30, 200730
Preliminary
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