TEXAS INSTRUMENTS LM3S2432 Technical data
PRELIMINARY
LM3S2432 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S2432-1972
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Preliminary
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LM3S2432 Microcontroller
Table of Contents
About This Document .................................................................................................................... 19
Audience .............................................................................................................................................. 19
About This Manual ................................................................................................................................ 19
Related Documents ............................................................................................................................... 19
Documentation Conventions .................................................................................................................. 19
1 Architectural Overview ...................................................................................................... 21
1.1 Product Features ...................................................................................................................... 21
1.2 Target Applications .................................................................................................................... 27
1.3 High-Level Block Diagram ......................................................................................................... 27
1.4 Functional Overview .................................................................................................................. 28
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 29
1.4.2 Motor Control Peripherals .......................................................................................................... 29
1.4.3 Analog Peripherals .................................................................................................................... 30
1.4.4 Serial Communications Peripherals ............................................................................................ 31
1.4.5 System Peripherals ................................................................................................................... 32
1.4.6 Memory Peripherals .................................................................................................................. 33
1.4.7 Additional Features ................................................................................................................... 33
1.4.8 Hardware Details ...................................................................................................................... 34
2 ARM Cortex-M3 Processor Core ...................................................................................... 35
2.1 Block Diagram .......................................................................................................................... 36
2.2 Functional Description ............................................................................................................... 36
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 36
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 37
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 37
2.2.4 ROM Table ............................................................................................................................... 37
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 37
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 37
3 Memory Map ....................................................................................................................... 41
4 Interrupts ............................................................................................................................ 43
5 JTAG Interface .................................................................................................................... 45
5.1 Block Diagram .......................................................................................................................... 46
5.2 Functional Description ............................................................................................................... 46
5.2.1 JTAG Interface Pins .................................................................................................................. 47
5.2.2 JTAG TAP Controller ................................................................................................................. 48
5.2.3 Shift Registers .......................................................................................................................... 49
5.2.4 Operational Considerations ........................................................................................................ 49
5.3 Initialization and Configuration ................................................................................................... 52
5.4 Register Descriptions ................................................................................................................ 52
5.4.1 Instruction Register (IR) ............................................................................................................. 52
5.4.2 Data Registers .......................................................................................................................... 54
6 System Control ................................................................................................................... 56
6.1 Functional Description ............................................................................................................... 56
6.1.1 Device Identification .................................................................................................................. 56
6.1.2 Reset Control ............................................................................................................................ 56
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Table of Contents
6.1.3 Power Control ........................................................................................................................... 59
6.1.4 Clock Control ............................................................................................................................ 59
6.1.5 System Control ......................................................................................................................... 61
6.2 Initialization and Configuration ................................................................................................... 61
6.3 Register Map ............................................................................................................................ 62
6.4 Register Descriptions ................................................................................................................ 63
7 Internal Memory ............................................................................................................... 112
7.1 Block Diagram ........................................................................................................................ 112
7.2 Functional Description ............................................................................................................. 112
7.2.1 SRAM Memory ........................................................................................................................ 112
7.2.2 Flash Memory ......................................................................................................................... 113
7.3 Flash Memory Initialization and Configuration ........................................................................... 114
7.3.1 Flash Programming ................................................................................................................. 114
7.3.2 Nonvolatile Register Programming ........................................................................................... 115
7.4 Register Map .......................................................................................................................... 115
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 116
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 123
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 136
8.1 Functional Description ............................................................................................................. 136
8.1.1 Data Control ........................................................................................................................... 137
8.1.2 Interrupt Control ...................................................................................................................... 138
8.1.3 Mode Control .......................................................................................................................... 139
8.1.4 Commit Control ....................................................................................................................... 139
8.1.5 Pad Control ............................................................................................................................. 139
8.1.6 Identification ........................................................................................................................... 139
8.2 Initialization and Configuration ................................................................................................. 139
8.3 Register Map .......................................................................................................................... 141
8.4 Register Descriptions .............................................................................................................. 142
9 General-Purpose Timers ................................................................................................. 177
9.1 Block Diagram ........................................................................................................................ 177
9.2 Functional Description ............................................................................................................. 178
9.2.1 GPTM Reset Conditions .......................................................................................................... 178
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 179
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 180
9.3 Initialization and Configuration ................................................................................................. 184
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 184
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 185
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 185
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 186
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 186
9.3.6 16-Bit PWM Mode ................................................................................................................... 187
9.4 Register Map .......................................................................................................................... 187
9.5 Register Descriptions .............................................................................................................. 188
10 Watchdog Timer ............................................................................................................... 213
10.1 Block Diagram ........................................................................................................................ 213
10.2 Functional Description ............................................................................................................. 213
10.3 Initialization and Configuration ................................................................................................. 214
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10.4 Register Map .......................................................................................................................... 214
10.5 Register Descriptions .............................................................................................................. 215
11 Analog-to-Digital Converter (ADC) ................................................................................. 236
11.1 Block Diagram ........................................................................................................................ 237
11.2 Functional Description ............................................................................................................. 237
11.2.1 Sample Sequencers ................................................................................................................ 237
11.2.2 Module Control ........................................................................................................................ 238
11.2.3 Hardware Sample Averaging Circuit ......................................................................................... 239
11.2.4 Analog-to-Digital Converter ...................................................................................................... 239
11.2.5 Test Modes ............................................................................................................................. 239
11.2.6 Internal Temperature Sensor .................................................................................................... 239
11.3 Initialization and Configuration ................................................................................................. 240
11.3.1 Module Initialization ................................................................................................................. 240
11.3.2 Sample Sequencer Configuration ............................................................................................. 240
11.4 Register Map .......................................................................................................................... 241
11.5 Register Descriptions .............................................................................................................. 242
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 269
12.1 Block Diagram ........................................................................................................................ 270
12.2 Functional Description ............................................................................................................. 270
12.2.1 Transmit/Receive Logic ........................................................................................................... 270
12.2.2 Baud-Rate Generation ............................................................................................................. 271
12.2.3 Data Transmission .................................................................................................................. 272
12.2.4 Serial IR (SIR) ......................................................................................................................... 272
12.2.5 FIFO Operation ....................................................................................................................... 273
12.2.6 Interrupts ................................................................................................................................ 273
12.2.7 Loopback Operation ................................................................................................................ 274
12.2.8 IrDA SIR block ........................................................................................................................ 274
12.3 Initialization and Configuration ................................................................................................. 274
12.4 Register Map .......................................................................................................................... 275
12.5 Register Descriptions .............................................................................................................. 276
13 Synchronous Serial Interface (SSI) ................................................................................ 310
13.1 Block Diagram ........................................................................................................................ 310
13.2 Functional Description ............................................................................................................. 310
13.2.1 Bit Rate Generation ................................................................................................................. 311
13.2.2 FIFO Operation ....................................................................................................................... 311
13.2.3 Interrupts ................................................................................................................................ 311
13.2.4 Frame Formats ....................................................................................................................... 312
13.3 Initialization and Configuration ................................................................................................. 319
13.4 Register Map .......................................................................................................................... 320
13.5 Register Descriptions .............................................................................................................. 321
14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 347
14.1 Block Diagram ........................................................................................................................ 347
14.2 Functional Description ............................................................................................................. 347
14.2.1 I2C Bus Functional Overview .................................................................................................... 348
14.2.2 Available Speed Modes ........................................................................................................... 350
14.2.3 Interrupts ................................................................................................................................ 351
14.2.4 Loopback Operation ................................................................................................................ 351
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5November 30, 2007
Table of Contents
14.2.5 Command Sequence Flow Charts ............................................................................................ 352
14.3 Initialization and Configuration ................................................................................................. 358
14.4 I2C Register Map ..................................................................................................................... 359
14.5 Register Descriptions (I2C Master) ........................................................................................... 360
14.6 Register Descriptions (I2C Slave) ............................................................................................. 373
15 Controller Area Network (CAN) Module ......................................................................... 382
15.1 Controller Area Network Overview ............................................................................................ 382
15.2 Controller Area Network Features ............................................................................................ 382
15.3 Controller Area Network Block Diagram .................................................................................... 383
15.4 Controller Area Network Functional Description ......................................................................... 384
15.4.1 Initialization ............................................................................................................................. 384
15.4.2 Operation ............................................................................................................................... 385
15.4.3 Transmitting Message Objects ................................................................................................. 385
15.4.4 Configuring a Transmit Message Object .................................................................................... 385
15.4.5 Updating a Transmit Message Object ....................................................................................... 386
15.4.6 Accepting Received Message Objects ...................................................................................... 386
15.4.7 Receiving a Data Frame .......................................................................................................... 387
15.4.8 Receiving a Remote Frame ...................................................................................................... 387
15.4.9 Receive/Transmit Priority ......................................................................................................... 387
15.4.10 Configuring a Receive Message Object .................................................................................... 387
15.4.11 Handling of Received Message Objects .................................................................................... 388
15.4.12 Handling of Interrupts .............................................................................................................. 388
15.4.13 Bit Timing Configuration Error Considerations ........................................................................... 389
15.4.14 Bit Time and Bit Rate ............................................................................................................... 389
15.4.15 Calculating the Bit Timing Parameters ...................................................................................... 391
15.5 Controller Area Network Register Map ...................................................................................... 393
15.6 Register Descriptions .............................................................................................................. 395
16 Analog Comparators ....................................................................................................... 423
16.1 Block Diagram ........................................................................................................................ 423
16.2 Functional Description ............................................................................................................. 424
16.2.1 Internal Reference Programming .............................................................................................. 425
16.3 Initialization and Configuration ................................................................................................. 426
16.4 Register Map .......................................................................................................................... 426
16.5 Register Descriptions .............................................................................................................. 427
17 Pulse Width Modulator (PWM) ........................................................................................ 435
17.1 Block Diagram ........................................................................................................................ 435
17.2 Functional Description ............................................................................................................. 435
17.2.1 PWM Timer ............................................................................................................................. 435
17.2.2 PWM Comparators .................................................................................................................. 436
17.2.3 PWM Signal Generator ............................................................................................................ 437
17.2.4 Dead-Band Generator ............................................................................................................. 438
17.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 438
17.2.6 Synchronization Methods ......................................................................................................... 438
17.2.7 Fault Conditions ...................................................................................................................... 439
17.2.8 Output Control Block ............................................................................................................... 439
17.3 Initialization and Configuration ................................................................................................. 439
17.4 Register Map .......................................................................................................................... 440
17.5 Register Descriptions .............................................................................................................. 441
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LM3S2432 Microcontroller
18 Pin Diagram ...................................................................................................................... 470
19 Signal Tables .................................................................................................................... 471
20 Operating Characteristics ............................................................................................... 483
21 Electrical Characteristics ................................................................................................ 484
21.1 DC Characteristics .................................................................................................................. 484
21.1.1 Maximum Ratings ................................................................................................................... 484
21.1.2 Recommended DC Operating Conditions .................................................................................. 484
21.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 485
21.1.4 Power Specifications ............................................................................................................... 485
21.1.5 Flash Memory Characteristics .................................................................................................. 486
21.2 AC Characteristics ................................................................................................................... 487
21.2.1 Load Conditions ...................................................................................................................... 487
21.2.2 Clocks .................................................................................................................................... 487
21.2.3 Analog-to-Digital Converter ...................................................................................................... 488
21.2.4 Analog Comparator ................................................................................................................. 488
21.2.5 I2C ......................................................................................................................................... 489
21.2.6 Synchronous Serial Interface (SSI) ........................................................................................... 489
21.2.7 JTAG and Boundary Scan ........................................................................................................ 491
21.2.8 General-Purpose I/O ............................................................................................................... 492
21.2.9 Reset ..................................................................................................................................... 493
22 Package Information ........................................................................................................ 495
A Serial Flash Loader .......................................................................................................... 497
A.1 Serial Flash Loader ................................................................................................................. 497
A.2 Interfaces ............................................................................................................................... 497
A.2.1 UART ..................................................................................................................................... 497
A.2.2 SSI ......................................................................................................................................... 497
A.3 Packet Handling ...................................................................................................................... 498
A.3.1 Packet Format ........................................................................................................................ 498
A.3.2 Sending Packets ..................................................................................................................... 498
A.3.3 Receiving Packets ................................................................................................................... 498
A.4 Commands ............................................................................................................................. 499
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 499
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 499
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 499
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 500
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 500
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 500
B Register Quick Reference ............................................................................................... 502
C Ordering and Contact Information ................................................................................. 519
C.1 Ordering Information ................................................................................................................ 519
C.2 Kits ......................................................................................................................................... 519
C.3 Company Information .............................................................................................................. 519
C.4 Support Information ................................................................................................................. 520
Preliminary
7November 30, 2007
Table of Contents
List of Figures
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram ............................................................... 28
Figure 2-1. CPU Block Diagram ......................................................................................................... 36
Figure 2-2. TPIU Block Diagram ........................................................................................................ 37
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 46
Figure 5-2. Test Access Port State Machine ....................................................................................... 49
Figure 5-3. IDCODE Register Format ................................................................................................. 54
Figure 5-4. BYPASS Register Format ................................................................................................ 55
Figure 5-5. Boundary Scan Register Format ....................................................................................... 55
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 57
Figure 7-1. Flash Block Diagram ...................................................................................................... 112
Figure 8-1. GPIO Port Block Diagram ............................................................................................... 137
Figure 8-2. GPIODATA Write Example ............................................................................................. 138
Figure 8-3. GPIODATA Read Example ............................................................................................. 138
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 178
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 182
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 183
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 184
Figure 10-1. WDT Module Block Diagram .......................................................................................... 213
Figure 11-1. ADC Module Block Diagram ........................................................................................... 237
Figure 11-2. Internal Temperature Sensor Characteristic ..................................................................... 240
Figure 12-1. UART Module Block Diagram ......................................................................................... 270
Figure 12-2. UART Character Frame ................................................................................................. 271
Figure 12-3. IrDA Data Modulation ..................................................................................................... 273
Figure 13-1. SSI Module Block Diagram ............................................................................................. 310
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 312
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 313
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 314
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 314
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 315
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 316
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 316
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 317
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 318
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 319
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 319
Figure 14-1. I2C Block Diagram ......................................................................................................... 347
Figure 14-2. I2C Bus Configuration .................................................................................................... 348
Figure 14-3. START and STOP Conditions ......................................................................................... 348
Figure 14-4. Complete Data Transfer with a 7-Bit Address ................................................................... 349
Figure 14-5. R/S Bit in First Byte ........................................................................................................ 349
Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 349
Figure 14-7. Master Single SEND ...................................................................................................... 352
Figure 14-8. Master Single RECEIVE ................................................................................................. 353
Figure 14-9. Master Burst SEND ....................................................................................................... 354
Figure 14-10. Master Burst RECEIVE .................................................................................................. 355
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LM3S2432 Microcontroller
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 356
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 357
Figure 14-13. Slave Command Sequence ............................................................................................ 358
Figure 15-1. CAN Module Block Diagram ........................................................................................... 383
Figure 15-2. CAN Bit Time ................................................................................................................ 390
Figure 16-1. Analog Comparator Module Block Diagram ..................................................................... 423
Figure 16-2. Structure of Comparator Unit .......................................................................................... 424
Figure 16-3. Comparator Internal Reference Structure ........................................................................ 425
Figure 17-1. PWM Module Block Diagram .......................................................................................... 435
Figure 17-2. PWM Count-Down Mode ................................................................................................ 436
Figure 17-3. PWM Count-Up/Down Mode .......................................................................................... 437
Figure 17-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 437
Figure 17-5. PWM Dead-Band Generator ........................................................................................... 438
Figure 18-1. Pin Connection Diagram ................................................................................................ 470
Figure 21-1. Load Conditions ............................................................................................................ 487
Figure 21-2. I2C Timing ..................................................................................................................... 489
Figure 21-3. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 490
Figure 21-4. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 490
Figure 21-5. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 491
Figure 21-6. JTAG Test Clock Input Timing ......................................................................................... 492
Figure 21-7. JTAG Test Access Port (TAP) Timing .............................................................................. 492
Figure 21-8. JTAG TRST Timing ........................................................................................................ 492
Figure 21-9. External Reset Timing (RST) .......................................................................................... 493
Figure 21-10. Power-On Reset Timing ................................................................................................. 494
Figure 21-11. Brown-Out Reset Timing ................................................................................................ 494
Figure 21-12. Software Reset Timing ................................................................................................... 494
Figure 21-13. Watchdog Reset Timing ................................................................................................. 494
Figure 22-1. 100-Pin LQFP Package .................................................................................................. 495
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9November 30, 2007
Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 19
Table 3-1. Memory Map ................................................................................................................... 41
Table 4-1. Exception Types .............................................................................................................. 43
Table 4-2. Interrupts ........................................................................................................................ 44
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 47
Table 5-2. JTAG Instruction Register Commands ............................................................................... 52
Table 6-1. System Control Register Map ........................................................................................... 62
Table 7-1. Flash Protection Policy Combinations ............................................................................. 114
Table 7-2. Flash Resident Registers ............................................................................................... 115
Table 7-3. Flash Register Map ........................................................................................................ 115
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 140
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 140
Table 8-3. GPIO Register Map ....................................................................................................... 141
Table 9-1. Available CCP Pins ........................................................................................................ 178
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 181
Table 9-3. Timers Register Map ...................................................................................................... 187
Table 10-1. Watchdog Timer Register Map ........................................................................................ 214
Table 11-1. Samples and FIFO Depth of Sequencers ........................................................................ 237
Table 11-2. ADC Register Map ......................................................................................................... 241
Table 12-1. UART Register Map ....................................................................................................... 275
Table 13-1. SSI Register Map .......................................................................................................... 320
Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 350
Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 359
Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 364
Table 15-1. Transmit Message Object Bit Settings ............................................................................. 386
Table 15-2. Receive Message Object Bit Settings .............................................................................. 388
Table 15-3. CAN Protocol Ranges .................................................................................................... 390
Table 15-4. CAN Register Map ......................................................................................................... 393
Table 16-1. Comparator 0 Operating Modes ...................................................................................... 424
Table 16-2. Comparator 1 Operating Modes ..................................................................................... 425
Table 16-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 425
Table 16-4. Analog Comparators Register Map ................................................................................. 427
Table 17-1. PWM Register Map ........................................................................................................ 440
Table 19-1. Signals by Pin Number ................................................................................................... 471
Table 19-2. Signals by Signal Name ................................................................................................. 475
Table 19-3. Signals by Function, Except for GPIO ............................................................................. 479
Table 19-4. GPIO Pins and Alternate Functions ................................................................................. 481
Table 20-1. Temperature Characteristics ........................................................................................... 483
Table 20-2. Thermal Characteristics ................................................................................................. 483
Table 21-1. Maximum Ratings .......................................................................................................... 484
Table 21-2. Recommended DC Operating Conditions ........................................................................ 484
Table 21-3. LDO Regulator Characteristics ....................................................................................... 485
Table 21-4. Detailed Power Specifications ........................................................................................ 486
Table 21-5. Flash Memory Characteristics ........................................................................................ 486
Table 21-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 487
Table 21-7. Clock Characteristics ..................................................................................................... 487
Preliminary
November 30, 200710
LM3S2432 Microcontroller
Table 21-8. Crystal Characteristics ................................................................................................... 487
Table 21-9. ADC Characteristics ....................................................................................................... 488
Table 21-10. Analog Comparator Characteristics ................................................................................. 488
Table 21-11. Analog Comparator Voltage Reference Characteristics .................................................... 488
Table 21-12. I2C Characteristics ......................................................................................................... 489
Table 21-13. SSI Characteristics ........................................................................................................ 489
Table 21-14. JTAG Characteristics ..................................................................................................... 491
Table 21-15. GPIO Characteristics ..................................................................................................... 493
Table 21-16. Reset Characteristics ..................................................................................................... 493
Table C-1. Part Ordering Information ............................................................................................... 519
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Table of Contents
List of Registers
System Control .............................................................................................................................. 56
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 64
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 66
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 67
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 68
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 69
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 70
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 71
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 72
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 76
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 77
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 79
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 80
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 82
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 83
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 85
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 87
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 89
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 90
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 92
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 94
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 96
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 98
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 100
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 102
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 104
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 106
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 108
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 109
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 111
Internal Memory ........................................................................................................................... 112
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 117
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 118
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 119
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 121
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 122
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 123
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 124
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 125
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 126
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 127
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 128
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 129
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 130
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 131
Preliminary
November 30, 200712
LM3S2432 Microcontroller
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 132
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 133
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 134
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 135
General-Purpose Input/Outputs (GPIOs) ................................................................................... 136
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 143
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 144
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 145
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 146
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 147
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 148
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 149
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 150
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 151
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 152
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 154
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 155
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 156
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 157
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 158
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 159
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 160
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 161
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 162
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 163
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 165
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 166
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 167
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 168
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 169
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 170
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 171
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 172
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 173
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 174
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 175
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 176
General-Purpose Timers ............................................................................................................. 177
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 189
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 190
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 192
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 194
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 197
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 199
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 200
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 201
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 203
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 204
Preliminary
13November 30, 2007
Table of Contents
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 205
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 206
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 207
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 208
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 209
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 210
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 211
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 212
Watchdog Timer ........................................................................................................................... 213
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 216
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 217
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 218
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 219
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 220
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 221
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 222
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 223
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 224
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 225
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 226
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 227
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 228
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 229
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 230
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 231
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 232
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 233
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 234
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 235
Analog-to-Digital Converter (ADC) ............................................................................................. 236
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 243
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 244
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 245
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 246
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 247
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 248
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 251
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 252
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 253
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 254
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 255
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 257
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 260
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 260
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 260
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 260
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 261
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 261
Preliminary
November 30, 200714
LM3S2432 Microcontroller
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 261
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 261
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 262
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 262
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 263
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 263
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 265
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 266
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 267
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 269
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 277
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 279
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 281
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 283
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 284
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 285
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 286
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 288
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 290
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 292
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 294
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 295
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 296
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 298
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 299
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 300
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 301
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 302
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 303
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 304
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 305
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 306
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 307
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 308
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 309
Synchronous Serial Interface (SSI) ............................................................................................ 310
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 322
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 324
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 326
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 327
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 329
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 330
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 332
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 333
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 334
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 335
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 336
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 337
Preliminary
15November 30, 2007
Table of Contents
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 338
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 339
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 340
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 341
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 342
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 343
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 344
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 345
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 346
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 347
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 361
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 362
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 366
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 367
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 368
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 369
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 370
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 371
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 372
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 374
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 375
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 377
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 378
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 379
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 380
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 381
Controller Area Network (CAN) Module ..................................................................................... 382
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 396
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 398
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 401
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 402
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 404
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 405
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 407
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 408
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 408
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 409
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 409
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 412
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 412
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 413
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 413
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 414
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 414
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 415
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 415
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 416
Preliminary
November 30, 200716
LM3S2432 Microcontroller
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 416
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 418
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 418
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 418
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 418
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 418
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 418
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 418
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 418
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 419
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 419
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 420
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 420
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 421
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 421
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 422
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 422
Analog Comparators ................................................................................................................... 423
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 428
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 429
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 430
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 431
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 432
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 432
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 433
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 433
Pulse Width Modulator (PWM) .................................................................................................... 435
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 442
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 443
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 444
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 445
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 446
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 447
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 448
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 449
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 450
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 451
Register 11: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 453
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 455
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 456
Register 14: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 457
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 458
Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 459
Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 460
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 461
Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 464
Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 467
Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 468
Preliminary
17November 30, 2007
Table of Contents
Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 469
Preliminary
November 30, 200718
About This Document
This data sheet provides reference information for the LM3S2432 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
LM3S2432 Microcontroller
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 19.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 41.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
19November 30, 2007
About This Document
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
November 30, 200720
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris
LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris
family with Bosch CAN networking technology, the golden standard in short-haul industrial networks.
The Stellaris®LM3S2000 series also marks the first integration of CAN capabilities with the
revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines both a 10/100 Ethernet
Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated
connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC
and PHY available in an ARM architecture MCU. The Stellaris®LM3S8000 series combines Bosch
Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and
Physical (PHY) layer.
LM3S2432 Microcontroller
®
The LM3S2432 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S2432 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S2432 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S2432 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
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Architectural Overview
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 30 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 96 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 32 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
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November 30, 200722
LM3S2432 Microcontroller
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Controller Area Network (CAN)
– Supports CAN protocol version 2.0 part A/B
– Bit rates up to 1Mb/s
– 32 message objects, each with its own identifier mask
– Maskable interrupt
– Disable automatic retransmission mode for TTCAN
– Programmable loop-back mode for self-test operation
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
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23November 30, 2007
Architectural Overview
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Three 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 250 thousand samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ I2C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
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Preliminary
LM3S2432 Microcontroller
– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
■ PWM
– One PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator,
and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ GPIOs
– 5-34 GPIOs, depending on configuration
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Architectural Overview
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
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November 30, 200726
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
LM3S2432 Microcontroller
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 28 represents the full set of features in the Stellaris®2000 series of devices;
not all features may be available on the LM3S2432 microcontroller.
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Architectural Overview
Figure 1-1. Stellaris®2000 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S2432 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 519.
November 30, 200728
Preliminary
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 35)
All members of the Stellaris®product family, including the LM3S2432 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 35 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
LM3S2432 Microcontroller
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S2432 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 30 interrupts.
“Interrupts” on page 43 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S2432 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
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Preliminary
Architectural Overview
On the LM3S2432, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 435)
The LM3S2432 PWM module consists of one PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 183)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S2432 microcontroller offers an Analog-to-Digital Converter
(ADC).
For support of analog signals, the LM3S2432 microcontroller offers two analog comparators.
1.4.3.1 ADC (see page 236)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S2432 ADC module features 10-bit conversion resolution and supports three input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 423)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S2432 microcontroller provides two independent integrated analog comparators that can
be configured to drive an output or generate an interrupt or ADC event.
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
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