TEXAS INSTRUMENTS DIT4096 Technical data
D
I
T
4
0
9
6
SBOS225B – DECEMBER 2001 – REVISED JUNE 2003
96kHz Digital Audio Transmitter
DIT4096
FEATURES
● COMPLIANT WITH AES-3, IEC-60958, AND EIAJ
CP1201 INTERFACE STANDARDS
● SUPPORTS SAMPLING RATES UP TO 96kHz
● SUPPORTS MONO-MODE OPERATION
● ON-CHIP DIFFERENTIAL LINE DRIVER
● FLEXIBLE AUDIO SERIAL INTERFACE:
-Master or Slave Mode Operation
-Supports I
Data Formats
● SOFTWARE MODE VIA SERIAL CONTROL
INTERFACE:
-Block Sized Buffer for Channel Status Data
-Auto Increment Mode for Block Sized Write and
Read Operations
● HARDWARE MODE ALLOWS OPERATION WITH-
OUT A MICROCONTROLLER
● CRC CODE GENERATION FOR PROFESSIONAL
MODE
● MASTER CLOCK RATE: 256fS, 384fS, or 512f
● +5V CORE SUPPLY (VDD)
● +2.7V TO VDD LOGIC I/O SUPPLY (VIO)
● PACKAGE: TSSOP-28
2
S, Left-Justified, and Right-Justified
S
APPLICATIONS
● DIGITAL MIXING CONSOLES
● DIGITAL MICROPHONES
● DIGITAL AUDIO WORKSTATIONS
● BROADCAST STUDIO EQUIPMENT
● EFFECTS PROCESSORS
●
SURROUND-SOUND DECODERS AND ENCODERS
● A/V RECEIVERS
● DVD, CD, DAT, AND MD PLAYERS
● AUDIO TEST EQUIPMENT
DESCRIPTION
The DIT4096 is a digital audio transmitter designed for use
in both professional and consumer audio applications. Transmit data rates up to 96kHz are supported. The DIT4096
supports both software and hardware operation, which makes
it suitable for applications with or without a microcontroller. A
flexible serial audio interface is provided, supporting standard audio data formats and easy interfacing to audio DSP
serial ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage, VDD..............................................................+6.5V
Input Current ................................................................................... ±10mA
Digital Input Voltage .......................................................... –0.2V to +5.5V
Digital Output Voltage ............................................ –0.2V to (V
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature .....................................................–55°C to +125°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR re-flow, 10s) ........................................ +235°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
V
..............................................................+6.5V
IO
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
+ 0.2V)
DD
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE-LEAD DESIGNATOR
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
DIT4096 TSSOP-28 PW –40°C to +85°C DIT4096IPW DIT4096IPW Rails, 50
(1)
"" " " "DIT4096IPWR Tape and Reel, 2000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
SPECIFIED
RANGE MARKING NUMBER MEDIA, QUANTITY
2
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DIT4096
SBOS225A
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, VDD = +5V, and VIO = +3.3V unless otherwise noted.
DIT4096IPW
PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL CHARACTERISTICS
Applies to All Digital I/O Except TX+ and TX–
High-Level Input Voltage, V
Low-Level Input Voltage, V
High-Level Output Voltage, V
Low-Level Output Voltage, V
Input Leakage Current 110µA
IH
IL
OH
OL
IO = –4mA 0.8 • V
IO = +4mA 0 0.1 • V
OUTPUT DRIVER CHARACTERISTICS
Applies Only to TX+ and TX–
High-Level Output Voltage, V
Low-Level Output Voltage, V
OH
OL
IO = –30mA VDD – 0.7 VDD – 0.4 V
IO = +30mA 0 0.4 0.7 V
SWITCHING CHARACTERISTICS
Master Clock and Reset
Master Clock (MCLK) Frequency 25 MHz
Master Clock (MCLK) Duty Cycle 40 60 %
Reset (RST) Active Low Pulse Width 500 ns
Serial Control Port Timing
CCLK Frequency
Stereo Mode f
Mono Mode f
Serial Control Data Setup Time, t
Serial Control Data Hold Time, t
CS Falling to CCLK Rising, t
CCLK Falling to CS Rising, t
CCLK Falling to CDOUT Data Valid, t
CS Rising to CDOUT High Impedance, t
Audio Serial Interface Timing
SDS
SDH
CSCR
CFCS
CFDO
CSZ
= Sampling Frequency 128 • f
S
= Sampling Frequency 64 • f
S
SYNC Frequency (or Frame Rate) 97.6525 kHz
SYNC Clock Period t
SYNC High/Low Pulse Width, t
SCLK Frequency 12.5 MHz
SCLK Clock Period, t
SCLK High/Low Pulse Width, t
SYNC Edge to SCLK Edge, t
Audio Data Setup Time, t
Audio Data Hold Time, t
C, U, and V Input Timing
C, U, V Data Setup Time, t
C, U, V Data Hold Time, t
SYNCP
SYNCHL
SCLKP
SCLKHL
SYSK
ADS
ADH
CUVS
CUVH
POWER-SUPPLY
Operating Voltage
V
DD
V
IO
Supply Current
, Quiescent VDD = +5V 25 µA
I
DD
I
, Power-Down Mode VDD = +5V 2 µA
DD
I
, Dynamic (at 96kHz operation) VDD = +5V 22 mA
DD
I
, Quiescent VIO = +3.3V 13 µA
IO
I
, Power-Down Mode VIO = +3.3V 13 µA
IO
I
, Dynamic (at 96kHz operation) VIO = +3.3V 2 mA
IO
I
, Quiescent VIO = +5V 280 µA
IO
I
, Power-Down Mode VIO = +5V 280 µA
IO
I
, Dynamic (at 98kHz operation) VIO = +5V 6.5 mA
IO
Power Dissipation
PD, Quiescent V
PD, Power-Down Mode V
PD, Dynamic (at 96kHz operation) V
= +5V 100 µW
DD
= +5V 100 µW
DD
= +5V 150 mW
DD
TEMPERATURE RANGE
Operating Range –40 +85 °C
Storage Range –55 +125 °C
0.7 • V
IO
0 0.2 • V
IO
25 ns
V
IO
IO
IO
DD
S
S
15 ns
20 ns
20 ns
25 ns
10 ns
10.24 µs
5.12 µs
80 ns
32 ns
30 ns
30 ns
30 ns
20 ns
20 ns
+4.5 +5 +5.5 V
+2.7 V
DD
V
V
V
V
V
MHz
MHz
V
DIT4096
SBOS225A
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3
PIN CONFIGURATION: Software Mode (MODE = 0)
PIN CONFIGURATION: Hardware Mode (MODE = 1)
Top View TSSOP
NC
CDOUT
CCLK
CDIN
CS
MCLK
V
DGND
RXP
NC
SCLK
SYNC
SDATA
NC
1
2
3
4
5
6
7
IO
DIT4096
8
9
10
11
12
13
14
MODE
28
U
27
NC
26
BLS
25
NC
24
NC
23
INT
22
NC
21
NC
20
V
19
DD
TX+
18
TX–
17
DGND
16
RST
15
Top View TSSOP
CSS
COPY/C
CLK1
CLK0
MCLK
V
DGND
FMT0
FMT1
SCLK
SYNC
SDATA
M/S
1
2
L
3
4
5
6
7
IO
DIT4096
8
9
10
11
12
13
14
MODE
28
U
27
V
26
BLS
25
BLSM
24
EMPH
23
AUDIO
22
MONO
21
MDAT
20
V
19
DD
TX+
18
TX–
17
DGND
16
RST
15
PIN DESCRIPTIONS: Software Mode
PIN NAME PIN DESCRIPTION
1 NC No Connection
2 CDOUT Control Port Data Output, Tri-State
3 CCLK Control Port Data Clock Input
4 CDIN Control Port Serial Data Input
5
6 MCLK Master Clock Input
7V
8 DGND Digital Ground
9 RXP AES-3 Encoded Data Input
10 NC No Connection
11 SCLK Audio Serial Port Data Clock I/O
12 SYNC Audio Serial Port Frame SYNC Clock I/O
13 SDATA Audio Serial Port Data Input
14 NC No Connection
15
16 DGND Digital Ground
17 TX– Transmitter Line Driver Output
18 TX+ Transmitter Line Driver Output
19 V
20 NC No Connection
21 NC No Connection
22
23 NC No Connection
24 NC No Connection
25 BLS Block Start I/O
26 NC No Connection
27 U User Data Input
28 MODE Control Mode Input. Set MODE = 0 for
CS
RST
DD
INT
Control Port Chip Select Input, Active LOW
IO
Digital I/O Power Supply, +2.7V to V
Nominal
Reset Input, Active LOW
Digital Core Power Supply, +5V Nominal
Open Drain Interrupt Output, Active LOW.
Requires 10kΩ pull-up resistor to V
Software Mode operation.
PIN DESCRIPTIONS: Hardware Mode
PIN NAME PIN DESCRIPTION
1 CSS Channel Status Data Mode Input
2 COPY/C Copy Protect Input or Channel Status Se-
3 L Generation Status Input
4 CLK1 Master Clock Rate Selection Input
5 CLK0 Master Clock Rate Selection Input
DD
6 MCLK Master Clock Input
7V
IO
8 DGND Digital Ground
9 FMT0 Audio Data Format Control Input
10 FMT1 Audio Data Format Control Input
11 SCLK Audio Serial Port Data Clock I/O
12 SYNC Audio Serial Port Frame SYNC Clock I/O
13 SDATA Audio Serial Port Data Input
14
15
M/S
RST
16 DGND Digital Ground
17 TX– Transmitter Line Driver Output
18 TX+ Transmitter Line Driver Output
19 V
DD
20 MDAT Mono Mode Channel Data Selection Input
21 MONO Mono Mode Enable Input, Active HIGH
.
IO
22
23
AUDIO
EMPH
24 BLSM Block Start Mode Control Input
25 BLS Block Start I/O
26 V Validity Data Input
27 U User Data Input
28 MODE Control Mode Input. Set MODE = 1 for
rial Data Input
Digital I/O Power Supply, +2.7V to V
Nominal
Audio Serial Port Master/Slave Control Input
Reset Input, Active LOW
Digital Core Power-Supply, +5V Nominal
Audio Data Valid Control Input, Active LOW
Pre-Emphasis Status Input, Active LOW
Hardware Mode Operation.
DD
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DIT4096
SBOS225A
GENERAL DESCRIPTION
The DIT4096 is a complete digital audio transmitter, suitable
for both professional and consumer audio applications. Sampling rates up to 96kHz are supported. The DIT4096 complies with the requirements for the AES-3, IEC-60958, and
EIAJ CP1201 interface standards.
Figures 1 and 2 show the block diagrams for the DIT4096
when used in Software and Hardware control modes. The
MODE input (pin 28) determines the control model used to
configure the DIT4096 internal functions. In Software mode,
a serial control port is used to write and read on-chip control
registers and status buffers. In Hardware mode, dedicated
control pins are provided for configuration and status inputs.
The DIT4096 includes an audio serial port, which is used to
interface to standard digital audio sources, such as
RXP
U
SYNC
SCLK
SDATA
Audio
Serial
Port
Analog-to-Digital (A/D) converters, Digital Signal Processors
(DSPs), and audio decoders. Support for Left-Justified, RightJustified, and I
2
S data formats is provided.
The AES-3 encoder creates a multiplexed bit stream, containing audio, status, and user data. See Figure 3 for the
multiplexed data format. The data is then Bi-Phase Mark
encoded and output to a differential line driver. The line driver
outputs are connected to the transmission medium, be it
cable or fiber optics. In the case of twisted-pair or coaxial
cable, a transformer is commonly used to couple the driver
outputs to the transmission line. This provides both isolation
and improved common-mode rejection. For optical transmission, the TX+ (pin 18) driver output is connected to an optical
transmitter module. See the Applications Information section
of this data sheet for details regarding output driver circuit
configurations.
TX+
TX–
AES-3 Encoder
Line
Driver
RST
Control Port
BLS
INT
FIGURE 1. Software Mode Block Diagram.
SYNC
SCLK
SDATA
M/S
FMT0
FMT1
RST
CSS
COPY/C
L
AUDIO
EMPH
U
V
Reset
Logic
Audio
Serial
Port
Reset
Logic
Serial Control Interface,
Control Registers,
and Channel Status
Data Buffers
AES-3 Encoder
CUV
Data Buffer
Clock
Generator
Driver
Clock
Generator
Line
MCLK
TX+
TX–
MCLK
CLK0
CLK1
BLSM
BLS
MONO
MDAT
FIGURE 2. Hardware Mode Block Diagram.
DIT4096
SBOS225A
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5
Frame 191 Frame 0 Frame 1
Channel AX XYYZ Channel A Channel A Channel BChannel BChannel B
Bits: 0 3 4 7 8
Preamble Aux Data LSB MSB V U C P
FIGURE 3. AES-3 Frame Format.
Start of Channel Status Block
One Sub-Frame
27 28 293031
Audio Data
Validity Data
User Data
Channel Status Data
Parity Bit
MASTER CLOCK
The DIT4096 requires a master clock for operation. This
clock must be supplied at the MCLK input (pin 6). The
maximum master clock frequency that may be supplied to
MCLK is 25MHz. Table I shows master clock rates for
common input sampling frequencies.
SAMPLING
FREQUENCY (kHz)
22.05 5.6448 8.4672 11.2896
24 6.144 9.216 12.288
32 8.192 12.288 16.384
44.1 11.2896 16.9344 22.5792
48 12.288 18.432 24.576
88.2 22.5792 n/a n/a
96 24.576 n/a n/a
TABLE I. Master Clock Frequencies for Common Sampling Rates.
For Software mode, the master clock frequency selection is
programmed using the CLK0 and CLK1 bits in Control
Register 02
H
CLK1 (pin 4) inputs are used to select the master clock
frequency. Table II shows the available MCLK frequency
selections.
MASTER CLOCK FREQUENCY (MHz)
256 • f
S
384 • f
S
512 • f
S
. For Hardware mode, the CLK0 (pin 5) and
RESET AND POWER-DOWN OPERATION
The DIT4096 includes a reset input,
used to force a reset sequence. When the DIT4096 is first
powered up, the user must assert
the reset sequence. The
mum of 500ns. The
RST
RST
input is then forced high to enable
normal operation. For software mode, the reset sequence will
force all internal registers to their default settings. In addition,
the reset sequence will force all channel status bits to 0 in
Software mode.
While the
RST
input is low, the transmitter outputs,
TX– (pin 17) and TX+ (pin 18), are forced to ground.
Upon setting
RST
high, the TX– and TX+ outputs will remain
low until the rising edge of the SYNC clock is detected at
pin 12. Once this occurs, the TX– and TX+ outputs will
become active and be driven by the output of the AES-3
encoder.
In Software mode, the DIT4096 also includes software reset
and power-down bits, located in control register 02
software reset bit,
RST
, and the software power-down bit,
PDN, are both active high.
RST
(pin 15), which is
RST
low, in order to start
input must be low for a mini-
. The
H
CONTROL BITS OR INPUT PINS
CLK1 CLK0
0 0 Unused
0 1 256 • f
1 0 384 • f
1 1 512 • f
MASTER CLOCK (MCLK) SELECTION
S
S
S
TABLE II. Master Clock Rate Selection for Software and
Hardware Modes.
6
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AUDIO SERIAL PORT
The audio serial port is a 3-wire interface used to connect the
DIT4096 to an audio source, such as an A/D converter or
DSP. The port supports sampling frequencies up to 96kHz.
The port signals include SDATA (pin 13), SYNC (pin 12), and
SCLK (pin 11). The SDATA pin is the serial data input for the
port. The SCLK pin may be either an input or output, and is
used to clock serial data into the port. The SYNC pin may be
DIT4096
SBOS225A
either an input or output, and provides the frame synchronization clock for the port. The SYNC pin is also used as a data
latch clock for the channel status, user, and validity data
inputs in Hardware mode, and the user data input in Software
mode.
SLAVE OR MASTER MODE OPERATION
The audio serial port supports both Slave and Master mode
operation. In Slave mode, both SYNC and SCLK are configured as inputs. The audio source device must generate both
the SYNC and SCLK clocks in Slave mode. In Master mode,
both SYNC and SCLK are configured as outputs. The audio
serial port generates the SYNC and SCLK clocks in Master
mode, deriving both from the master clock (MCLK) input.
In Software mode, Master/Slave mode selection is performed using the
Slave mode). In Hardware mode, the
used to select the audio serial port mode. This is shown in
Table III.
CONTROL BITS OR INPUT PIN
TABLE III. Master/Slave Mode Selection for Software or
M/S
bit in Control Register 03H (defaults to
M/S
0
1
Hardware Mode.
M/S
input (pin 14) is
MASTER/SLAVE MODE SELECTION
Slave Mode; both SYNC and SCLK
are inputs.
Master Mode; both SYNC and SCLK
are outputs.
SYNC AND SCLK FREQUENCIES
The SYNC clock rate is the same as the sampling frequency,
or f
. This holds true for both Slave and Master modes. The
S
DIT4096 supports SYNC frequencies up to 96kHz.
The SCLK frequency in Slave mode must provide at least
one clock cycle for each data bit that is input at SDATA. The
maximum SCLK frequency is 128 • f
f
= 96kHz. The SCLK frequency in Master mode is set by
S
, or 12.288MHz for
S
the DIT4096 itself. For Software mode operation, the SCLK
rate may be programmed to either 64 • f
the SCLKR bit in Control Register 03
the SCLK frequency is fixed at 64 • f
or 128 • fS, using
S
. In Hardware mode,
H
for Master mode.
S
AUDIO DATA FORMATS
The DIT4096 supports standard audio data formats, including Philips I
Software mode provides the most flexible format selection,
while Hardware mode supports a limited subset of the
Software mode formats. Linear PCM audio data at the
SDATA input is typically presented in Binary Two’s Complement, MSB first format. Encoded or non-audio data may be
provided as required by the encoding scheme in use. Figure
4 shows the common data formats used by the audio serial
port.
2
S, Left-Justified, and Right-Justified data.
SYNC
(ISYNC = 0)
SYNC
(ISYNC = 1)
SDATA
SDATA
SDATA
SCLK
(ISCLK = 0)
SCLK
(ISCLK = 1)
SYNC
SCLK
SDATA
MSB LSB
MSB LSB
t
SYSK
t
SYSKHL
t
ADS
t
SYNCHL
t
SCLKHL
t
SCLKP
t
ADH
MSB LSB
MSB LSB
MSB LSB
Right ChannelLeft Channel
t
SYNCHL
MSB LSB
Right Justified
Left Justified
0 SCLK Delay
Left Justified
1 SCLK Delay (I
2
S)
FIGURE 4. Audio Data Formats and Timing.
DIT4096
SBOS225A
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7
For Software mode, Control Register 03
EMPH
is used to set the
H
audio data format selection. Data word length may be set to
16, 18, 20, or 24 bits using the WLEN0 and WLEN1 bits.
Several format parameters, including SCLK sampling edge,
data delay from the start of frame, and SYNC polarity may be
programmed using this register. Table IV shows examples of
register bit settings for three standard audio formats. SCLK
sampling edges and SYNC polarity may differ from one
system implementation to the next. Consult the audio source
device data sheet or technical reference for details regarding
the output data formatting.
For Hardware mode, the FMT0 (pin 9) and FMT1 (pin 10)
inputs are utilized to select one of four audio data formats.
Refer to Table V for the available format selections.
falling edge of SYNC when the ISYNC bit is set to 1. If BLS
is high when it is sampled, then a block start condition is
indicated. When BLS is configured as an output and the
ISYNC bit is set to 0, BLS will go high at every 192nd falling
edge of SYNC for Stereo mode, or every 384th falling edge
of SYNC for Mono mode. BLS will then go low on the
following falling edge. If the ISYNC bit is set to 1, then BLS
transitions on the rising edge of SYNC.
Hardware mode operation is similar to Software mode operation, with the exception that there are only a limited number
of data formats available for the audio serial port. For Leftand Right-Justified formats, BLS behaves as it would in
Software mode with ISYNC = 0. For the I
2
S data format, BLS
behaves as it would in Software mode with ISYNC = 1.
INPUT PINS
FMT1 FMT0
0 0 24-Bit Left-Justified
0 1 24-Bit I
1 0 24-Bit Right-Justified
1 1 16-Bit Right-Justified
FORMAT SELECTIONS
2
S
TABLE V. Audio Data Format Selection for Hardware Mode.
AES-3 ENCODER OPERATION
The AES-3 encoder performs the multiplexing of audio,
channel status, user, and validity data. It also performs BiPhase Mark encoding of the multiplexed data stream. This
section describes how channel status, user, and validity data
are input to the encoder function.
BLOCK START INPUT/OUTPUT
The block start is used to indicate the start of a channel status
data block, which starts with Frame 0 for the AES-3 data
stream. For the DIT4096, the block start signal, BLS
(pin 25), may be either an input or output. In Software mode,
the direction of BLS is set using the BLSM bit in control register
01
(defaults to input). In Hardware mode, the direction of BLS
H
is set by the BLSM input (pin 24). If BLSM = 0, the BLS pin is
an input. If BLSM = 1, the BLS pin is an output.
For Software mode operation, the block start signal is synchronized to the audio serial port frame sync clock, SYNC
(pin 12). When BLS is configured as an input pin, it is
sampled on the rising edge of SYNC when the ISYNC bit in
control register 03
is set to 0. Otherwise, it is sampled on the
H
CHANNEL STATUS DATA INPUT
Channel status data input is determined by the control mode
in use. In Software mode, the channel status data buffer is
accessed through the serial control port. Buffer operations
are described in detail in the section of this data sheet
entitled Channel Status Buffer Operation (Software Mode
Only). In Hardware mode, channel status data input is
accomplished by one of two user-selectable methods.
THE CSS INPUT
In Hardware mode, the state of the CSS input (pin 1)
determines the function of dedicated channel status inputs.
When CSS = 0, the COPY (pin 2), L (pin 3),
and
(pin 23) inputs are used to set associated
channel status data bits. The COPY and L inputs are used to
setup copy protection for consumer operation, or indicate
that the transmitter is operating in professional mode, without
copy protection. The
AUDIO
input is utilized to indicate
whether the data being transmitted is PCM audio data, or
non-audio data. The EMPH
input is used to indicate whether
the PCM audio data has been pre-emphasized using the
50/15µs standard. See Table VI for the available options for
these dedicated channel status inputs.
When CSS = 1, the channel status data is input in a serial
fashion at the C input (pin 2). Data is clocked on the rising
and falling edges of the SYNC input (pin 12). All channel
status data bits can be written in this mode, allowing greater
flexibility than the previous Hardware mode case with
CSS = 0. See Figure 5 for the C input timing diagram.
AUDIO
(pin 22),
CONTROL REGISTER 03
AUDIO DATA
FORMATS
2
Phillips I
S 0 Left-Justified 1 1 SCLK Delay 0 Rising Edge 1 Inverted
Left-Justified 0 Left-Justified 0 0 SCLK Delay 0 Rising Edge 0 Noninverted
Right-Justified 1 Right-Justified 0 0 SCLK Delay 0 Rising Edge 0 Noninverted
Bit Name Function Bit Name Function Bit Name Function Bit Name Function
JUS Justification DELAY SCLK Delay ISCLK Sampling Edge ISYNC Phase
BIT SETTINGS
H
TABLE IV. Audio Data Format Selection in Software Mode.
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DIT4096
SBOS225A
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