Texas Instruments DAC5573IPWRG4, DAC5573 Datasheet
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FEATURES DESCRIPTION
APPLICATIONS
Resistor
Network
8
18
Data
Buffer A
DAC
Register A
Data
Buffer D
DAC
Register D
DAC A
DAC D
Buffer
Control
Register
Control
Power−Down
Control Logic
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
REF
LA0 A1 A2 A3GND
I2C Block
SCL
SDA
LDAC
V
REF
H
IOV
DD
V
DD
DAC5573
SLAS401 – NOVEMBER 2003
QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT,
I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER
• Micropower Operation: 500 µA at 3 V V
DD
The DAC5573 is a low-power, quad channel, 8-bit
• Fast Update Rate: 188 kSPS
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing. The
• Power-On Reset to Zero
DAC5573 utilizes an I2C-compatible two-wire serial
• 2.7-V to 5.5-V Analog Power Supply
interface supporting high-speed interface mode with
• 8-Bit Monotonic
address support of up to sixteen DAC5573s for a total
• I2C™ Interface up to 3.4 Mbps
of 64 channels on the bus.
• Data Transmit Capability
The DAC5573 requires an external reference voltage
• Rail-to-Rail Output Buffer Amplifier
to set the output range of the DAC. The DAC5573
incorporates a power-on-reset circuit that ensures
• Double-Buffered Input Register
that the DAC output powers up at zero volts and
• Address Support for up to Sixteen DAC5573s
remains there until a valid write takes place in the
• Synchronous Update for up to 64 Channels
device. The DAC5573 contains a power-down fea-
• Voltage Translators for all Digital Inputs
ture, accessed via the internal control register, that
reduces the current consumption of the device to 200
• Operation From –40 ° C to 105 ° C
nA at 5 V.
• Small 16 Lead TSSOP Package
The low power consumption of this part in normal
operation makes it ideally suited to portable battery
operated equipment. The power consumption is less
• Process Control
than 3 mW at V
DD
= 5 V reducing to 1 µW in
• Data Acquisition Systems
power-down mode.
• Closed-Loop Servo Control
The DAC5573 is available in a 16-lead TSSOP
• PC Peripherals
package.
• Portable Instrumentation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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3
A3
A2
A1
1
2
3
4
5
6
7
8
16
15
14
1
12
11
10
9
V
OUT
A
V
OUT
B
V
REF
H
V
DD
V
REF
L
GND
V
OUT
C
V
OUT
D
A0
IOV
DD
SDA
SCL
LDAC
DAC5573
ABSOLUTE MAXIMUM RATINGS
(1)
DAC5573
SLAS401 – NOVEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE SPECIFICATION PACKAGE ORDERING TRANSPORT MEDIA
DRAWING TEMPERATURE MARKING NUMBER
NUMBER RANGE
DAC5573 16-TSSOP PW –40 °C TO +105 °C D5573I DAC5573IPW 90 Piece Tube
DAC5573IPWR 2000 Piece Tape and Reel
PW PACKAGE
PIN DESCRIPTIONS
(TOPVIEW)
PIN NAME DESCRIPTION
1 V
OUT
A Analog output voltage from DAC A
2 V
OUT
B Analog output voltage from DAC B
3 V
REF
H Positive reference voltage input
4 V
DD
Analog voltage supply input
5 V
REF
L Negative reference voltage input
Ground reference point for all circuitry on the
6 GND
part
7 V
OUT
C Analog output voltage from DAC C
8 V
OUT
D Analog output voltage from DAC D
9 LDAC H/W synchronous V
OUT
update
10 SCL Serial clock input
11 SDA Serial data input
12 IOV
DD
I/O voltage supply input
13 A0 Device address select - I2C
14 A1 Device address select - I2C
15 A2 Device address select - Extended
16 A3 Device address select - Extended
V
DD
to GND –0.3 V to +6 V
Digital input voltage to GND –0.3 V to V
DD
+ 0.3 V
V
OUT
to GND –0.3 V to V
DD
+ 0.3 V
Operating temperature range –40 °C to +105 °C
Storage temperature range –65 °C to +150 °C
Junction temperature range (TJmax) +150 °C
Power dissipation: Thermal impedance (R
ΘJA
) 161 °C/W
Thermal impedance (R
ΘJC
) 29 °C/W
Lead temperature, soldering: Vapor phase (60s) 215 °C
Infrared (15s) 220 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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ELECTRICAL CHARACTERISTICS
DAC5573
SLAS401 – NOVEMBER 2003
V
DD
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
(1) (2)
Resolution 8 Bits
Relative accuracy ± 0.25 ± 0.5 LSB
Differential nonlinearity Specified monotonic by design ± 0.1 ± 0.25 LSB
Zero-scale error 5 20 mV
Full-scale error -0.15 ± 1.0 % of FSR
Gain error ± 1.0 % of FSR
Zero code error drift ± 7 µV/ °C
Gain temperature coefficient ± 3 ppm of FSR/ °C
OUTPUT CHARACTERISTICS
(3)
Output voltage range 0 V
REF
H V
Output voltage settling time (full scale) RL= ∞ ; 0 pF < CL< 200 pF 6 8 µs
RL= ∞ ; CL= 500 pF 12 µs
Slew rate 1 V/ µs
dc crosstalk (channel-to-channel) 0.0025 LSB
ac crosstalk (channel-to-channel) 1 kHz Sine Wave -100 dB
Capacitive load stability RL= ∞ 470 pF
RL= 2 k Ω 1000 pF
Digital-to-analog glitch impulse 1 LSB change around major 12 nV-s
carry
Digital feedthrough 0.3 nV-s
dc output impedance 1 Ω
Short-circuit current VDD= 5 V 50 mA
VDD= 3 V 20 mA
Power-up time Coming out of power-down 2.5 µs
mode, VDD= +5 V
Coming out of power-down 5 µs
mode, VDD= +3 V
REFERENCE INPUT
V
REF
H Input range 0 V
DD
V
V
REF
L Input range V
REF
L<V
REF
H 0 GND VDD/2 V
Reference input impedance 25 k Ω
Reference current V
REF
=V
DD
= +5 V 185 260 µA
V
REF
=V
DD
= +3 V 122 200
LOGIC INPUTS
(3)
Input current ± 1 µA
V
IN_L
, Input low voltage 0.3xIOV
DD
V
V
IN_H
, Input high voltage 0.7xIOV
DD
V
Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD, IOV
DD
2.7 5.5 V
IDD(normal operation), including reference current Excluding load current
IDD@ VDD=+3.6V to +5.5V VIH= IOV
DD
and VIL=GND 600 900 µA
IDD@ V
DD
=+2.7V to +3.6V VIH= IOV
DD
and VIL=GND 500 750 µA
IDD(all power-down modes)
(1) Linearity tested using a reduced code range of 3 to 253; output unloaded.
(2) V
REF
H = V
DD
- 0.1, V
REF
L = GND
(3) Specified by design and characterization, not production tested.
3
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TIMING CHARACTERISTICS
DAC5573
SLAS401 – NOVEMBER 2003
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; CL= 200 pF to GND; all specifications -40 ° C to +105 ° C, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
IDD@ VDD=+3.6V to +5.5V VIH= IOV
DD
and VIL=GND 0.2 1 µA
IDD@ V
DD
=+2.7V to +3.6V VIH= IOV
DD
and VIL=GND 0.05 1 µA
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, VDD= +5 V 93%
TEMPERATURE RANGE
Specified performance -40 +105 °C
V
DD
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications –40 ° C to +105 ° C, unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Standard mode 100 kHz
Fast mode 400 kHz
f
SCL
SCL clock frequency
High-Speed mode, CB= 100 pF max 3.4 MHz
High-speed mode, CB= 400 pF max 1.7 MHz
Standard mode 4.7 µs
Bus free time between a STOP and
t
BUF
START condition
Fast mode 1.3 µs
Standard mode 4.0 µs
Hold time (repeated) START
tHD; t
STA
Fast mode 600 ns
condition
High-speed mode 160 ns
Standard mode 4.7 µs
Fast mode 1.3 µs
t
LOW
LOW period of the SCL clock
High-speed mode, CB= 100 pF max 160 ns
High-speed mode, CB= 400 pF max 320 ns
Standard mode 4.0 µs
Fast mode 600 ns
t
HIGH
HIGH period of the SCL clock
High-Speed Mode, CB= 100 pF max 60 ns
High-speed mode, CB= 400 pF max 120 ns
Standard mode 4.7 µs
Setup time for a repeated START
tSU; t
STA
Fast mode 600 ns
condition
High-speed mode 160 ns
Standard mode 250 ns
tSU; t
DAT
Data setup time Fast mode 100 ns
High-speed mode 10 ns
Standard mode 0 3.45 µs
Fast mode 0 0.9 µs
tHD; t
DAT
Data hold time
High-speed mode, CB= 100 pF max 0 70 ns
High-speed mode, CB= 400 pF max 0 150 ns
Standard mode 1000 ns
Fast mode 20 + 0.1C
B
300 ns
t
RCL
Rise time of SCL signal
High-speed mode, CB= 100 pF max 10 40 ns
High-speed mode, CB= 400 pF max 20 80 ns
Standard mode 1000 ns
Rise time of SCL signal after a
Fast mode 20 + 0.1C
B
300 ns
t
RCL1
repeated START condition and after
High-speed mode, CB= 100 pF max 10 80 ns
an acknowledge BIT
High-speed mode, CB= 400 pF max 20 160 ns
4
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DAC5573
SLAS401 – NOVEMBER 2003
TIMING CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V, RL= 2 k Ω to GND; all specifications –40 ° C to +105 ° C, unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Standard mode 300 ns
Fast mode 20 + 0.1C
B
300 ns
t
FCL
Fall time of SCL signal
High-speed mode, CB= 100 pF max 10 40 ns
High-speed mode, CB= 400 pF max 20 80 ns
Standard mode 1000 ns
Fast mode 20 + 0.1C
B
300 ns
t
RDA
Rise time of SDA signal
High-speed mode, CB= 100 pF max 10 80 ns
High-speed mode, CB= 400 pF max 20 160 ns
Standard mode 300 ns
Fast mode 20 + 0.1C
B
300 ns
t
FDA
Fall time of SDA signal
High-speed mode, CB= 100 pF max 10 80 ns
High-speed mode, CB= 400 pF max 20 160 ns
Standard mode 4.0 µs
Setup time for STOP
tSU; t
STO
Fast mode 600 ns
condition
High-speed mode 160 ns
C
B
Capacitive load for SDA and SCL 400 pF
Fast mode 50 ns
Pulse width of spike
t
SP
suppressed
High-speed mode 10 ns
Standard mode
Noise margin at the HIGH level for
V
NH
each connected device Fast mode 0.2 V
DD
V
(including hysteresis)
High-speed mode
Standard mode
Noise margin at the LOW level for
V
NL
each connected device Fast mode 0.1 V
DD
V
(including hysteresis)
High-speed mode
5
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TYPICAL CHARACTERISTICS
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
Channel AChannel A VDD = 5 V
255
LE − LSBDLE − LSB
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
Channel B VDD = 5 V
255
LE − LSBDLE − LSB
−1
−0.5
0
0.5
1
LE − LSB
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
DLE − LSB
255
Channel D
VDD = 5 V
−1
−0.5
0
0.5
1
LE − LSB
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
DLE − LSB
255
Channel C VDD = 5 V
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
255
LE − LSBDLE − LSB
Channel A
VDD = 2.7 V
−1
−0.5
0
0.5
1
LE − LSB
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
DLE − LSB
255
Channel B
VDD = 2.7 V
DAC5573
SLAS401 – NOVEMBER 2003
At TA= +25 ° C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 1. Figure 2.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 3. Figure 4.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 5. Figure 6.
6
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−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
255
LE − LSBDLE − LSB
Channel D
VDD = 2.7 V
−1
−0.5
0
0.5
1
−0.5
−0.25
0
0.25
0.5
0 32 64 96 128 160 192 224
Digital Input Code
255
LE − LSBDLE − LSB
Channel C
VDD = 2.7 V
0
3
6
9
−40 −10 20 50 80
VDD = 5 V
CH A
CH D
CH C
CH B
TA − Free-Air Temperature − °C
Zero-Scale Error − mV
−2
0
2
4
−40 −10 20 50 80
CH A
CH D
CH C
CH B
T
A
− Free-Air Temperature − °C
Zero-Scale Error − mV
VDD = 2.7 V
−4
−3
−2
−1
−40 −10 20 50 80
CH A
CH D
CH C
CH B
T
A
− Free-Air Temperature − °C
Full-Scale Error − mV
VDD = 5 V
−2
−1.75
−1.5
−1.25
−1
−40 −10 20 50 80
CH A
CH D
CH C
CH B
T
A
− Free-Air Temperature − °C
Full-Scale Error − mV
VDD = 2.7 V
DAC5573
SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 7. Figure 8.
ZERO-SCALE ERROR ZERO-SCALE ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 9. Figure 10.
FULL-SCALE ERROR FULL-SCALE ERROR
vs TEMPERATURE vs TEMPERATURE
Figure 11. Figure 12.
7
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0.000
0.025
0.050
0.075
0.100
0.125
0.150
0 1 2 3 4 5
I
SINK
− Sink Current − mA
V
OUT
− Output Voltage − V
VDD = 2.7 V
VDD = 5.5 V
DAC Loaded With 00
H
Typical For All Channels
5.30
5.35
5.40
5.45
5.50
0 1 2 3 4 5
I
SOURCE
− Source Current − mA
V
OUT
− Output Voltage − V
DAC Loaded With FF
H
VDD = 5.5 V
Typical For All Channels
2.3
2.4
2.5
2.6
2.7
0 1 2 3 4 5
I
SOURCE
− Source Current − mA
V
OUT
− Output Voltage − V
DAC Loaded With FF
H
VDD = 2.7 V
Typical For All Channels
Digital Input Code
0
100
200
300
400
500
600
700
800
0 32 64 96 128 160 192 224
I
DD
− Supply Current − µA
VDD = 2.7 V
VDD = 5.5 V
All Channels Powered, No Load
255
TA - Free-Air Temperature - °C
0
100
200
300
400
500
600
700
-40 -10 20 50 80 110
I
DD
- Supply Current - µA
VDD = 2.7 V
VDD = 5.5 V
All Channels Powered, No Load
VDD - Supply Voltage - V
200
250
300
350
400
450
500
550
600
650
700
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
I
DD
- Supply Current - µA
All DACs Powered, No Load
DAC5573
SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
SINK CURRENT CAPABILITY SOURCE CURRENT CAPABILITY
AT NEGATIVE RAIL AT POSITIVE RAIL
Figure 13. Figure 14.
SOURCE CURRENT CAPABILITY SUPPLY CURRENT
AT POSITIVE RAIL vs DIGITAL INPUT CODE
Figure 15. Figure 16.
SUPPLY CURRENT SUPPLY CURRENT
vs TEMPERATURE vs SUPPLY VOLTAGE
Figure 17. Figure 18.
8
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IDD - Current Consumption - µA
0
500
1000
1500
2000
500 520 540 560 580 600 620 640 660 680 700 720 740
VDD = 5 V
Frequency
V
Logic
− Logic Input Voltage − V
200
400
600
800
1000
1200
0 1 2 3 4 5
I
DD
− Supply Current − µA
TA = 25°C
A0 Input (All Other Inputs = GND)
VDD = 2.7 V
VDD = 5.5 V
−1
0
1
2
3
4
5
6
Time (2 µs/div)
V
OUT
− Output Voltage − V
VDD = 5 V
Powerup to Code 250
IDD - Current Consumption - µA
0
500
1000
1500
2000
400 420 440 460 480 500 520 540 560 580 600 620
VDD = 2.7 V
Frequency
0
1
2
3
4
5
Time (25 µs/div)
V
OUT
- Output Voltage - V
VDD = 5 V
Output Loaded with
200 pF to GND
10% to 90% FSR
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Time (25 µs/div)
V
OUT
- Output Voltage - V
VDD = 2.7 V
Output Loaded with
200 pF to GND
10% to 90% FSR
DAC5573
SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
SUPPLY CURRENT HISTOGRAM
vs LOGIC INPUT VOLTAGE OF CURRENT CONSUMPTION
Figure 19. Figure 20.
HISTOGRAM EXITING
OF CURRENT CONSUMPTION POWER-DOWN MODE
Figure 21. Figure 22.
LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME
Figure 23. Figure 24.
9
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0
4
8
12
16
20
24
0 32 64 96 128 160 192 224
Digital Input Code
Output Error (mV)
255
Channel A Output
Channel D Output
Channel B Output
Channel C Output
VDD = 5 V, TA = 25°C
−6
−2
2
6
10
14
18
0 32 64 96 128 160 192 224 255
Channel A Output
VDD = 2.7 V, TA = 25°C
Channel D Output
Channel C Output
Channel B Output
Digital Input Code
Output Error (mV)
†
Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral
DAC5573
SLAS401 – NOVEMBER 2003
TYPICAL CHARACTERISTICS (continued)
At TA= +25 ° C, unless otherwise noted.
ABSOLUTE ERROR
†
ABSOLUTE ERROR
†
Figure 25. Figure 26.
linearity.
10
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