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DAC38RF86EVM
User Manual
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Texas Instruments DAC38RF8xEVM Series, DAC38RF82EVM, DAC38RF80EVM, DAC38RF86EVM, DAC38RF89EVM User Manual

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User's Guide
SLAU671A–October 2016–Revised March 2017

DAC38RF8xEVM

SLASEF4). Throughout this document, italics are used to refer to names of controls on graphical user
interfaces (GUI).
Contents
1 Introduction ................................................................................................................... 2
1.1 Required Hardware and Software ................................................................................ 2
1.2 Hardware Description .............................................................................................. 2
2 Quick Start.................................................................................................................... 5
2.1 TSW14J56 and DAC38RF8xEVM................................................................................ 5
3 Generating Configuration Files for Custom Boards.................................................................... 15
3.1 Status Log.......................................................................................................... 15
3.2 Low Level View.................................................................................................... 15
Appendix A ....................................................................................................................... 17
Appendix B ....................................................................................................................... 18
List of Figures
1 DAC38RF8xEVM Block Diagram.......................................................................................... 2
2 Shunt Pin 1 and Pin 2 of JP10 Jumper Enabling External Clock Mode.............................................. 5
3 DAC38RF83 EVM Setup for External Clock Mode...................................................................... 6
4 DAC38RF8xEVM GUI Quick Start Page Configured for External Clock Mode ..................................... 7
5 DAC38RF8xEVM GUI External Clock Select Checkbox ............................................................. 7
6 Open Pin 1 and Pin 2 of JP10 Jumper to Enable On-Chip PLL Clock Mode........................................ 8
7 DAC38RF83 EVM Setup for On-Chip PLL Mode ....................................................................... 9
8 DAC38RF8xEVM GUI Quick Start Page Configured for On-Chip PLL Mode...................................... 10
9 Load Firmware to the TSW14J56........................................................................................ 11
10 Complex, Single Tone Generation at 100 kHz in HSDC Pro......................................................... 11
11 DAC A Digital Control Tab of the DAC38RF8x GUI ................................................................... 12
12 DAC A Output at 1960 MHz and 2140 MHz, Mixer Gain Off, Dummy Date Enabled............................. 13
13 1×20 MHz LTE, TM3.1, Center Frequency = 1960 MHz, DAC Coarse Gain = 10, External Clock............. 13
14 1×20 MHz LTE, TM3.1, Center Frequency = 2140 MHz, DAC Coarse Gain = 10, External Clock............. 14
15 DAC Output Power vs Frequency (Fsampling = 8847.36 Msps) .................................................... 14
16 DAC38RF8xEVM GUI Status Log ....................................................................................... 15
17 DAC38RF8xEVM GUI Low Level View ................................................................................. 16
18 DAC Output Circuit Schematic ........................................................................................... 17
19 TCM3-452X-1+ Frequency Response................................................................................... 17
20 Clock Input Path Circuit Diagram ........................................................................................ 18
21 NCR2-113+ Frequency Response....................................................................................... 18
SLAU671A–October 2016–Revised March 2017
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DAC38RF8xEVM
1
1:2 Power
Splitter
DA38RF8x
LMK04828
Clock
Divider
(/4)
IOUTA+
IOUTA>
IOUTB>
IOUTB+
Sysref
Reference
Clock
SMA
SMA J1
SMA
SMA
NCR2-113+
2:1
TCM3-452X-1+
2:1
NB7V33M
FMC Connector
Sysref
Reference
Clock
1.8 V
1.8 V
+ CLKTX>
SMA
+ CLKIN >
TCM2-43X+
2:1
Introduction

1 Introduction

1.1 Required Hardware and Software

The following hardware and software are required to evaluate the DAC38RF8x device:
1. DAC38RF8xEVM: Main circuit board containing the DAC to be evaluated
2. DAC38RF8xEVM Graphical User Interface (GUI): Software that controls the DAC EVM:
http://www.ti.com/tool/TSW14J56EVM
3. TSW14J56 EVM: Hardware that generates digital patterns for the DAC:
http://www.ti.com/tool/TSW14J56EVM
4. HSDC Pro software: Software interface that controls the TSW14J56 EVM. Version 4.50 or higher is
recommended: http://www.ti.com/tool/dataconverterpro-sw

1.2 Hardware Description

Figure 1 illustrates the EVM block diagram.
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DAC38RF8xEVM
Figure 1. DAC38RF8xEVM Block Diagram
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Introduction
Table 1. DAC38RF8xEVM Component Description
Part Description
DAC38RF8x 9 Gsps dual-channel DAC with JESD204B interface FMC Connector Interface to connect DAC evaluation board to pattern generators (for example, TSW14J56) LMK04828 JESD204B-compliant clock generator. Used to generate SYSREF and device clock to pattern generator. Also
NB7V33M 10 GHz divide by 4 clock divider TCM3-452X-1+ 2:1 impedance ratio transformer. Used for (1) impedance matching to 50-Ω load, (2) differential to single-ended
TCM2-43X+ 2:1 impedance ratio transformer. Used to convert CLKTX from differential to single ended. CLKTX is divided by 3 or 4
NCR2-113+ 2:1 impedance ratio transformer. Used to convert single-ended input clock to differential for the DAC.
generates SYSREF and PLL reference clock to DAC38RF8x.
conversion, (3) DC biasing of DAC output.
output of the DAC sampling clock.
Table 2. Jumpers on DAC38RF8xEVM
Jumper Default Position Description
JP1 Shunt pin 2-3 shunt pin1-2: Put some DAC internal blocks in sleep mode.
JP2 Shunt pin 2-3 shunt pin1-2- Enable DAC output.
JP3 Open Open: Disables power to the on-board 122.88 MHz VCXO (Y1). Leave open
JP8 Open Open: Enables VDDDIG1 supply (U37).
JP9 Open Open: Enables VEE18N supply (U19).
JP10 Shunt pin 1-2 Closed: Enable external clock mode
J11 Open Not used J22 Open Provides access to externally monitor ATEST pin J23 Shunt pin 1-2, 3-4, 5-6, 7-8 Connects DAC SPI interface to FT2232H (U4) spi interface.
Shunt pin2-3: Take DAC out of sleep mode
Shunt pin2-3-disable DAC output
when VCXO is not used Closed: Enables power to the on-board 122.88 MHz VCXO
Closed: disables VDDDIG1 supply (U37)
Closed: disables VEE18N supply (U19)
Open: Enable on-chip PLL clock mode
1.2.1 Clocking Modes
The DAC38RF8xEVM may be configured into one of five clocking modes. These clocking modes are:
1. Direct External clock mode with high amplitude clock
2. Direct External clock mode with low amplitude clock (less than 7 dBm)
3. On-chip PLL clock mode
4. On-board VCXO clock mode
5. LMF = 413 or 823, 12-bits clock mode
1.2.1.1 Direct External Clock Mode With High Amplitude Clock (CMODE1)
This mode is intended for use with signal generators that can output 16 dBm or higher. Examples are Keysight E8257D or R&S SMA100. To use this mode, the only modification from the default EVM configuration is to connect a shunt between pin 1 and 2 of jumper JP10. Then, provide a 16-dBm clock to SMA J1. This is shown in Figure 2. By default, the EVM is configured to use the single-ended clock input of the DAC in this mode. For best spurious performance, also install C1, C333, and C334 on the EVM to switch to differential clock input of DAC. Refer to the schematics and BOM of the EVM for the component values (SLAC734).
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Introduction
1.2.1.2 Direct External Clock Mode With Low Amplitude Clock (CMODE2)
The purpose of this mode is for use with monolithic clock synthesizers like the LMX259x. Clock power in the range of 3 dBm to 7 dBm is recommended in this mode. Note that when using the LMX2592 with the frequency doubler enabled, an external filter is required to attenuate the sub-harmonic at half the clock frequency to –50 dBc or better. To configure the EVM in this mode from the default configuration:
1. Install SMA J27
2. Remove C2, C3, R215, R211
3. Install R323, R324, C449, C450 (refer to the schematics and BOM of the EVM for the component
values (SLAC734)
4. Connect the positive and negative output of clock synthesizer to SMA J27 and SMA J1, respectively
5. Remove jumper JP10
6. Use a second signal generator to provide a clock to SMA J4 and set the amplitude to 6 dBm. The
frequency of this clock is one-fourth of the sampling rate (or Fs/4). This clock is used to provide the reference clock of the FPGA and SYSREF.
7. Connect SMA J24 to the reference input of the clock synthesizer. The frequency at SMA J24 is set
from the EVM GUI in a later step.
1.2.1.3 On-Chip PLL Clock Mode (CMODE3)
This mode is for evaluating the DAC performance with a low-frequency reference clock and the internal PLL/VCO as the sampling clock. To use this mode, connect a clock at 6 dBm to SMA J4 and remove the shunt connecting pin1 and 2 of jumper JP10. Keep all other hardware settings in the default configuration. The frequency of the clock at SMA J4 is determined from the EVM GUI in a later step.
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1.2.1.4 On-Board VCXO Clock Mode (CMODE4)
This mode allows the DAC to be evaluated without providing any external clock. The on-board VCXO running at a fixed 122.88-MHz frequency can be used to provide a reference clock to the LMK04828 PLL. The high-frequency clock generated by the LMK04828 PLL is subsequently divided down and used to source reference clock and SYSREF to the DAC internal PLL and the FPGA on TSW14J56 EVM. To use this mode, connect a shunt between pins 1 and 2 of jumper JP3. Keep all other hardware settings in the default configuration.
1.2.1.5 LMF = 413 or 823, 12-Bits Clock Mode(CMODE5)
This mode is used to generate the required clocks for evaluating the DAC in 12-bits mode, LMF = 413 or 823 only. Two signal generators with their 10-MHz reference connected together are required in this mode. The setup involves:
1. Provide an external sampling clock to SMA J1
2. Provide a second clock to SMA J4 with an amplitude of 6 dBm. The frequency of this clock will be
determined by the EVM GUI in a later step. Connect the reference of the two signal generators together.
3. Remove the shunt on pins 1 and 2 of jumper JP10
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2 Quick Start

The following examples use an external clock and the on-chip PLL to evaluate the performance of the DAC38RF8xEVM. The frequency of the clock is arbitrarily selected as 6144 Msps but the procedure outlined is applicable to any external clock frequency and any supported on-chip PLL frequency.
The external clock path includes a balun for single-ended to differential conversion. Appendix B shows the insertion loss, amplitude, and phase un-balance of this balun.

2.1 TSW14J56 and DAC38RF8xEVM

This section covers details on the TSW14J56 and DAC38RF8xEVM.
1. Make sure both boards are not powered and not connected to the USB port of the PC.
2. Connect the FMC connector of TSW14J56 EVM (J4) to FMC connector of DAC38RF8xEVM (J20).
2.1.1 TSW14J56
1. Connect a 5-V power supply to connector J11 (+5 V IN).
2. Connect a USB cable to the USB connector (J9).
3. Flip the power switch (SW6) to the “ON” position.
2.1.2 DAC38RF8xEVM Configuration With Direct External Clock(CMODE1)
Skip this section if the on-chip PLL is used as the DAC clock source.
Quick Start
NOTE: Shunt pin 1 and pin 2 of the 2-pin jumper labeled JP10 to enable external clock mode. This
is shown in Figure 2. Other hardware changes may be required depending on the external clocking mode. These changes are described in Section 1.2.1.
Figure 2. Shunt Pin 1 and Pin 2 of JP10 Jumper Enabling External Clock Mode
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Quick Start
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Figure 3. DAC38RF83 EVM Setup for External Clock Mode
1. Connect a 5-V power supply to connector J21 (+5V_IN).
2. Connect a USB cable to the USB connector (J16).
3. Provide a 16-dBm, 6144-MHz, external DAC sampling clock to the clock balun input at J1.
4. Connect a spectrum analyzer to the DAC output SMA connector:
• For DAC38RF83: Connect spectrum analyzer to J6 (DAC A output) or J2 (DAC B output).
• For DAC38RF80: Connect a spectrum analyzer to J7 (DAC A output) or J2 (DAC B output).
2.1.3 DAC38RF8x Graphical User Interface (GUI)
Follow these steps to use the DAC38RF8x GUI:
1. Start the DAC38RF8xEVM GUI, then navigate to the quick start page as shown in Figure 4.
2. Verify that the green USB Status indicator on the top right corner is lit. If it is not lit, click the
Reconnect FTDI? button and check the USB Status indicator again.
3. From the Quick Start tab, in the SELECT DEVICE drop down menu, choose from the list of available
devices. The device list is automatically populated based on the type of EVM connected.
4. On the Quick Start tab, toggle the DAC RESETB Pin button and then click on the Load Default
button. The software automatically configures the DAC to its default state.
5. Enter the desired DAC clock frequency (6144 MHz in this example) and specify the desired number of
DACs (Dual DAC), number of IQ pairs (1 IQ pair), number of lanes (4 lanes), and interpolation (16x) as shown in Figure 4.
6. Note the messages displayed for information about the SerDes rate, maximum allowed sample rate for
the selected mode, and the HSDC Pro ini file to select (see the section on HSDC Pro for more information). If the DAC clock frequency entered is not supported for the selected mode, the DAC clock frequency box blinks.
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DAC38RF8xEVM
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Quick Start
Figure 4. DAC38RF8xEVM GUI Quick Start Page Configured for External Clock Mode
7. Click on the CONFIGURE DAC button to load the DAC configuration data.
NOTE: When using CMODE2 and after configuring the DAC in the preceding step 6, navigate to
DAC38RF8x>>Clocking tab and de-select the External Clock Select checkbox.
Figure 5. DAC38RF8xEVM GUI External Clock Select Checkbox
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Quick Start
8. Click on the Reset DAC JESD Core button and the Trigger LMK04828 SYSREF button.
2.1.4 DAC38RF8xEVM Configuration With On-Chip PLL(CMODE3)
Skip this section if using an external clock such as the DAC clock source.
NOTE: The 2-pin jumper labeled JP10 must be open to enable on-chip PLL clock mode. This is
shown in Figure 6. Other hardware changes may be required depending on the on-chip PLL clocking mode selected. These changes are described in Section 1.2.1.
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Figure 6. Open Pin 1 and Pin 2 of JP10 Jumper to Enable On-Chip PLL Clock Mode
8
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SLAU671A–October 2016–Revised March 2017
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