Texas Instruments DAC3484, DAC3482 User Manual

User's Guide

SLAU336–March 2011

DAC3484/DAC3482 EVM

Contents

1 Introduction .................................................................................................................. 2

1.1 Overview ............................................................................................................ 2

1.2 EVM Block Diagram ............................................................................................... 2

2 Software Control ............................................................................................................ 3

2.1 Installation Instructions ............................................................................................ 3

2.2 Software Operation ................................................................................................ 3

3 Basic Test Procedure ....................................................................................................... 8

3.1 Test Block Diagram ................................................................................................ 8

3.2 Test Set-Up Connection ........................................................................................... 9

3.3 TSW3100 Quick Start Operation ................................................................................. 9

3.4 DAC348x Software Quick Start Guide ......................................................................... 10

4 Optional Configuration .................................................................................................... 12

4.1 Configuring and Testing the DAC3484 Transformer Coupled Output ..................................... 12

4.2 Using the DAC3482 or Configuring DAC3484 in DAC3482 mode ......................................... 15

List of Figures

1 DAC3484/DAC3482 EVM Block Diagram ............................................................................... 2

2 Input Control Options....................................................................................................... 3

3 PLL Configuration........................................................................................................... 4

4 Digital Block Options ....................................................................................................... 5

5 Output Control Options..................................................................................................... 6

6 CDCE62005 Tab Configured for 4x Interpolation....................................................................... 7

7 Test Set-up Block Diagram................................................................................................ 8

8 TSW3100 CommsSignalPattern (WCDMA) Programming GUI..................................................... 10

9 DAC3484 + TRF3703-15 WCDMA Output ............................................................................ 11

10 DAC3484 + TRF3703-15 WCDMA Output ............................................................................ 12

11 Locations of DAC348x to Transformer Output Jumper Locations .................................................. 13

12 DAC3484 Transformer Coupled Output at 60MHz IF ................................................................ 14

13 DAC3484 Transformer Coupled Output at 30MHz IF ................................................................ 15

14 Locations of the DAC3482 to TRF3703-15 Interface Jumpers...................................................... 16

15 TSW3100 GUI Configuration for Generating a WCDMA Signal for DAC3482.................................... 17

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19.2MHz TCXO

CDCE62005

DAC348X

DATA DATA _CLK FRAME SYNC PARITY

(LVDS DC Coupled)

DAC_CLK

(LVPECLAC Coupled)

OSTR_CLK

(LVPECLAC Coupled)

J20 RF

J19 LO

FPGA CLK

TSW3100 LVPECL DC coupled

TRF3703-15

Default TRF3703-15

Output

J10

Ext. CLK Output

6 V Only

Power

Supply

Circuits

J21 RF

J22 LO

TRF3703-15

Default TRF3703-15

Output

J11

Ext. CLK Input

1.5 Vrms Single Ended

1.25GHz Max Primary Reference (LVPECLAC coupled )

19.2 MHz Reference

LVCMOS Level Secondary Reference for CDCE62005 PLL Mode

PRI

SEC

J23 RF

J24 LO

TRF3703-15

Optional DAC Output

Optional TRF3703-15 Output for DAC3482 Dual DAC Mode

Introduction

1 Introduction

1.1 Overview

This document is intended to serve as a basic user’s guide for the DAC3484/2 EVM Revision D. The EVM provides a basic platform to evaluate the DAC3484 and DAC3482, which are a family of 1.25GSPS, up to 16x interpolation, 16-bit high speed digital-to-analog converters. The DAC3484 is a quad-channel DAC, and the DAC3482 is a dual-channel DAC.

The EVM includes the CDCE62005 clocking source which provides the clocks required for the DAC and the pattern generator. The on-board TRF3703-15 modulators provide on-board IF-to-RF upconversion for basic transmitter evaluation. This EVM is ideally suited for mating with the TSW3100 pattern generation card for evaluating WCDMA, LTE, or other high performance modulation schemes.

1.2 EVM Block Diagram

Figure 1 shows the configuration of the EVM with the TSW3100 used for pattern generation.

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Figure 1. DAC3484/DAC3482 EVM Block Diagram

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2 Software Control

2.1 Installation Instructions

• Open the folder named DAC348x_Installer_vxpx (xpx represents the latest version)

• Run Setup.exe

• Follow the on-screen instructions

• Once installed, launch by clicking on the DAC348x_GUI_vxpx program in Start>Texas Instruments DACs

• When plugging in the USB cable for the first time, you will be prompted to install the USB drivers. – When a pop-up screen opens, select “Continue Downloading”.

– Follow the on screen instructions to install the USB drivers – If needed, you can access the drivers directly in the install directory

2.2 Software Operation

The software allows programming control of the DAC device and the CDC device. The front panel provides a tab for full programming of each device. The GUI tabs provide more convenient and simplified interface to the most used registers of each device.

Each device, including the DAC3484, DAC3482, and DAC34H84, has its own custom control interface. Select the device option from the top left-hand corner. The DAC3484 EVM Software Control is described in this section.

Software Control

2.2.1 Input Control Options

Figure 2. Input Control Options

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Software Control

• FIFO: allows the configuration of the FIFO and FIFO sync sources.

• LVDS delay: provides internal delay of either the LVDS DATA or LVDS DATACLK to help meet the input setup/hold time.

• Data Routing: provides flexible routing of the A, B, C, and D sample input data to the appropriate digital path.

Note: the DAC3482 does not support this mode

• SIF Control: provides control of the Serial Interface (3-wires or 4-wires) and Serial Interface Sync (SIF Sync).

• Input Format: provides control of the input data format (i.e., 2’s complement or offset binary).

• Parity: provides configuration of the parity input.

• PLL Settings: provides configuration of the on-chip PLL circuitry.

• Temperature Sensor: provides temperature monitoring of DAC3484/2 die temperature.

2.2.1.1 LVDS Delay Settings

The TSW3100 pattern generator sends out LVDS DATA and DATACLK as edge-aligned signal. The following options can be implemented to meet the minimum setup and hold time of DAC348x data latching:

• Set the on-chip LVDS DATACLOCK delay. Typical setting of 160ps or more will help meet the timing requirement for most of the TSW3100 + DAC348x EVM setup. This LVDS DATACLOCK delay does not account for additional PCB trace-to-trace delay variation, only the internal DATACLK delay.

• Modify the external LVDS DATACLK PCB trace delay: Additional trace length on the bottom side of the PCB can be added to the LVDS DATACLK PCB trace length. Set SJP9, SJP10, SJP11, and SJP12 to 2-3 position for approximately 220ps of trace delay.

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2.2.1.2 PLL Settings

Follow the steps below to configure the PLL.

• Enable PLL

• Uncheck PLL reset and PLL sleep

• Set M and N ratio such that F

• Set the prescaler such that the F

• Set VCO Bias Tune to “1”

• Charge Pump setting – If stability (P×M) is less than 120, then set to “Single

– If stability (P×M) is greater than 120, then set to “Double” or install external loop filter

• Adjust the Freq. Tune (coarse tune) accordingly.

Figure 3. PLL Configuration

= (M)/(N)×Fref

DAC

×prescaler is within 3.3GHz and 4.0GHz

DAC

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2.2.2 Digital Block Options

Software Control

Figure 4. Digital Block Options

● Interpolation: allows control of the data rate versus DAC sampling rate ratio (i.e. data rate ×

interpolation = DAC sampling rate).

● Digital Mixer: allows control of the coarse mixer function.

Note: If fine mixer (NCO) is used, the “Enable Mixer” button must be checked, and the coarse mixer must be bypassed. See NCO section for detail.

● Inverse sinx/x filter: allows compensation of the sinx/x attenuation of the DAC output.

Note: If inverse sinx/x filter is used, the input data digital full-scale must be backed off accordingly to avoid digital saturation.

● Clock Receiver Sleep: allows the DAC clock receiver to be in sleep mode. The DAC has minimum

power consumption in this mode.

● Clock Divider Sync: allows the syncing of the internal divided-down clocks using either Frame,

Sync, or OSTR signal. Enable the divider sync as part of the initialization procedure or resynchronization procedure.

● Group Delay: allows adjustment of group delay for each I/Q channel. This is useful for wideband

sideband suppression.

● Offset Adjustment: allows adjustment of DC offset to minimize the LO feed-through of the modulator

output. This section requires sync for proper operation. The sync options are listed below:

O REGWR: auto-sync from SIF register write. O OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with

OSTR set as sync source O SYNC: sync from the external LVDS SYNC signal. O SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.

● QMC Adjustment: allows adjustment of the gain and phase of the I/Q channel to minimize sideband power of the modulator output.

O REGWR: auto-sync from SIF register write. O OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with

OSTR set as sync source O SYNC: sync from the external LVDS SYNC signal. O SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.

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Software Control

● NCO: allows fine mixing of the I/Q signal. The procedure to adjust the NCO mixing frequency are listed below:

1. Enter the DAC sampling frequency in Fsample.

2. Enter the desired mixing frequency in both NCO freq_AB and NCO freq_CD.

3. Press Update freq

4. Sync the NCO block from the following options:

● REGWR: auto-sync from SIF register write. Writing to either Phase OffsetAB or Phase OffsetCD can create a sync event.

● OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with OSTR set as sync source. Refer to the datasheet for OSTR period requirement.

● SYNC: sync from the external SYNC signal

● SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync

event.

2.2.3 Output Control Options

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Figure 5. Output Control Options

● Output Options: allows the configuration of reference, output polarity, and output delay

● Data Routing: provides flexible routing of the A, B, C, and D digital path to the desired output

channels. Note: The DAC3482 does not support this mode.

● DAC Gain: configures the full-scale DAC current and DAC3484/DAC3482 mode. With Rbiaj resistor set at 1.28kΩ:

O DAC Gain = 15 for 30mA full-scale current. O DAC Gain = 10 for 20mA full-scale current (default). O DAC3484 = QDAC O DAC3482 = DDAC

● This allows the DAC3484 to be configured as DAC3482 (see Using DAC3484 as DAC3482 section for detail)

● DAC Sel = Enable inner outputs of Ch. B and Ch. C as the DAC3482 output.

● DAC Sel = Enable outer outputs of Ch. A and Ch. D as the DAC3482 output. Outer

channels are grounded for the DAC3482 device.

● Output Shutoff On: allows outputs to shut-off when DACCLK GONE, DATACLK GONE, or FIFO COLLISION alarm event occurs.

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