TEXAS INSTRUMENTS DAC3283 Technical data

DAC3283

www.ti.com

Dual-Channel, 16-Bit, 800 MSPS, Digital-to-Analog Converter (DAC)

Check for Samples: DAC3283

1

FEATURES

• Dual, 16-Bit, 800 MSPS DACs

• 8-Bit Input LVDS Data Bus
– Byte-Wide Interleaved Data Load
– 8 Sample Input FIFO
– Optional Data Pattern Checker

• Multi-DAC Synchronization

• Selectable 2x-4x Interpolation Filters
– Stop-Band Attenuation > 85 dB

• Fs/2 and ± Fs/4 Coarse Mixer

• Digital Quadrature Modulator Correction
– Gain, Phase and Offset Correction

• Temperature Sensor

• 3- or 4-Wire Serial Control Interface

• On-Chip 1.2-V Reference

• Differential Scalable Output: 2 to 20 mA

• Single-Carrier TM1 WCDMA ACLR: 82 dBc at
f

= 122.88 MHz

OUT

• Low Power: 1.3 W at 800 MSPS

• Space Saving Package: 48-pin 7×7mm QFN

SLAS693A –MARCH 2010–REVISED APRIL 2010

APPLICATIONS

• Cellular Base Stations

• Diversity Transmit

• Wideband Communications

• Digital Synthesis

DESCRIPTION

The DAC3283 is a dual-channel 16-bit 800 MSPS
digital-to-analog converter (DAC) with an 8-bit LVDS
input data bus with on-chip termination, optional
2x-4x interpolation filters, digital IQ compensation and
internal voltage reference. The DAC3283 offers
superior linearity, noise and crosstalk performance.

Input data can be interpolated by 2x or 4x through
on-chip interpolating FIR filters with over 85 dB of
stop-band attenuation. Multiple DAC3283 devices can
be fully synchronized.

The DAC3283 allows either a complex or real output.
An optional coarse mixer in complex mode provides
frequency upconversion and the dual DAC output
produces a complex Hilbert Transform pair. The
digital IQ compensation feature allows optimization of
phase, gain and offset to maximize sideband rejection
and minimize LO feed-through of an external
quadrature modulator performing the final single
sideband RF up-conversion.

The DAC3283 is characterized for operation over the
entire industrial temperature range of –40°C to 85°C
and is available in a 48-pin 7×7mm QFN package.

ORDERING INFORMATION

T

A

–40°C to 85°C RGZ/64QFN Quad Flatpack No-Lead Tape and Reel

(1) Thermal Pad Size: 5,6 mm × 5,6 mm
(2) MSL Peak Temperature: Level-3-260C-168 HR
(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

ORDER CODE PACKAGE DRAWING/TYPE

DAC3283IRGZT 250
DAC3283IRGZR 2000

(1) (2) (3)

TRANSPORT MEDIA QUANTITY

Copyright © 2010, Texas Instruments Incorporated

100100

Pattern

Test

De-interleave

8 Sample FIFO

16

16

100

x2

x2

Coarse Mixer

Fs/4, -Fs/4, Fs/2

QMC

Phase and Gain

1.2 V

Reference

16-b
DAC

16-b
DAC

ControlInterface

Temp

Sensor

ClockDistribution

A

gain

B

gain

FrameStrobe

EXTIO

BIASJ

IOUTA1

IOUTA2

IOUTB1

IOUTB2

DACCLKP

DACCLKN

DATACLKP

DATACLKN

D7P

D7N

D0P

D0N

FRAMEP

FRAMEN

OSTRP

OSTRN

QMC

A-offset

QMC

B-offset

ALARM_SDO

SDIO

SDENB

SCLK

TXENABLE

AVDD33

CLKVDD18

DIGVDD18

VFUSE

DACVDD18

GND

LVPECL

LVDS

LVPECL

LVDS

LVDS

FIR1FIR0

59 taps 23 taps

100

LVDS

x2

x2

Programmable Delay

(0-3T)

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): DAC3283

37

38

39

40

41

42

43

44

45

46

47

48

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

35

34

33

32

31

30

29

28

27

26

25

DAC3283

RGZPackage

48-QFN 7x7mm

(TopView )

36

GND

DACCLKN

D5P

D5N

D4P

D4N

DATACLKP

DATACLKN

FRAMEP

FRAMEN

D3P

D3N

D2P

D2N

D1P

D1N

D0P

D0N

TXENABLE

SDIO

SCLK

SDENB

AVDD33

AVDD33

IOUTB1

IOUTB2

VFUSE

BIASJ

EXTIO

AVDD33

IOUTA2

IOUTA1

AVDD33

AVDD33

D6N

D6P

D7N

D7P

DIGVDD18

OSTRN

OSTRP

DACCLKP

DACVDD18

CLKVDD18 DACVDD18

CLKVDD18

ALARM_SDO

DIGVDD18

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

DAC3283

RGZ PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

AVDD33 I

37, 40, 42, Analog supply voltage. (3.3 V)

45, 48

ALARM_SDO 34 O

BIASJ 43 O Full-scale output current bias. For 20mA full-scale output current, connect a 960Ω resistor to GND.
CLKVDD18 1, 35 I

D[7..0]P 15, 21, 23, I

D[7..0]N 16, 22, 24, I D7N is most significant data bit (MSB) – pin 10

DACCLKP 3 I Positive external LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
DACCLKN 4 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)

DACVDD18 2, 36 I

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 3

9, 11, 13,

25, 27

10, 12, 14,

26, 28

I/O DESCRIPTION

1.8V CMOS output for ALARM condition. The ALARM output functionality is defined through the
CONFIG6 register. Default polarity is active low, but can be changed to active high via CONFIG0
alarm_pol control bit. Optionally, it can be used as the uni-directional data output in 4-pin serial
interface mode (CONFIG 23 sif4_ena = '1').

Internal clock buffer supply voltage. (1.8 V) It is recommended to isolate this supply from DACVDD18
and DIGVDD18.

LVDS positive input data bits 0 through 7. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two
data transfers per DATACKP/N clock cycle. Dual channel 16-bit data is transferred byte-wide on this
single 8-bit data bus using FRAMEP/N as a frame strobe indicator.

The order of the bus can be reversed via CONFIG19 rev bit.
LVDS negative input data bits 0 through 15. (See D[7:0]P description above)

DAC core supply voltage. (1.8 V) It is recommended to isolate this supply from CLKVDD18 and
DIGVDD18.

D7P is most significant data bit (MSB) – pin 9
D0P is least significant data bit (LSB) – pin 27

D0N is least significant data bit (LSB) – pin 28

Product Folder Link(s): DAC3283

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

DATACLKP 17 I Input data D[7:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate) with two data

DATACLKN 18 I LVDS negative input data clock. (See DATACLKP description)
DIGVDD18 8, 29 I

EXTIO 44 I/O = '1'. Used as internal reference output when CONFIG25 extref_ena = '0' (default). Requires a 0.1µF

FRAMEP 19 I

FRAMEN 20 I LVDS frame indicator negative input. (See the FRAMEN description)
GND I Pin 5 and the Thermal Pad located on the bottom of the QFN package is ground for all supplies.

IOUTA1 38 O full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input

IOUTA2 39 O IOUTA1 described above. An input data value of 0x0000 results in a 0 mA sink and the most positive

IOUTB1 47 O B-Channel DAC current output. Refer to IOUTA1 description above.
IOUTB2 46 O B-Channel DAC complementary current output. Refer to IOUTA2 description above.

OSTRP 6 I DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it

OSTRN 7 I LVPECL output strobe negative input. (See the OSTRP description)
SCLK 32 I 1.8V CMOS serial interface clock. Internal pull-down.
SDENB 33 I 1.8V CMOS active low serial data enable, always an input to the DAC3283. Internal pull-up.

SDIO 31 I/O

TXENABLE 30 I When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.

VFUSE 41 I

5, Thermal

Pad

I/O DESCRIPTION

LVDS positive input data clock. This positive/negative pair has an internal 100 Ω termination resistor.
transfers input per DATACLKP/N clock cycle.

Digital supply voltage. (1.8V) It is recommended to isolate this supply from CLKVDD18 and
DACVDD18.

Used as external reference input when internal reference is disabled through CONFIG25 extref_ena
decoupling capacitor to AGND when used as reference output.

LVDS frame indicator positive input. This positive/negative pair has an internal 100Ω termination
resistor. This signal is captured with the rising edge of DATACLKP/N and used to indicate the
beginning of the frame. It is also used as a reset signal by the FIFO. The FRAMEP/N signal should be
edge-aligned with D[7:0]P/N.

A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin.

A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the
voltage on the IOUTA2 pin.

LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of
can be left floating.

1.8V CMOS serial interface data. Bi-directional in 3-pin mode (default). In 4-pin interface mode, the
SDIO pin is an input only. Internal pull-down.

1.8V CMOS active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
Internal pull-down.

Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to

DACVDD18 pins for normal operation.

4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): DAC3283

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

DACDVDD18
DIGVDD18

Supply voltage range CLKVDD18

VFUSE
AVDD33
CLKVDD18 to DIGDVDD18 –0.5 to 0.5 V
DACVDD18 TO DIGVDD18 –0.5 to 0.5 V

D[7..0]P ,D[7..0]N, DATACLKP, DATACLKN, FRAMEP, FRAMEN
Terminal voltage
range

DACCLKP, DACCLKN, OSTRP, OSTRN

ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE

IOUTA1/B1, IOUTA2/B2

EXTIO, BIASJ
Peak input current (any input) 20 mA
Peak total input current (all inputs) –30 mA
Operating free-air temperature range, TA: DAC3283 –40 to 85 °C
Storage temperature range –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to GND.

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(1)

VALUE UNIT

–0.5 to 2.3 V
–0.5 to 2.3 V
–0.5 to 2.3 V
–0.5 to 2.3 V

–0.5 to 4 V

(2)

–0.5 to DIGVDD18 + 0.5 V

–0.5 to CLKVDD18 + 0.5 V

(2)

–0.5 to DIGCLKVDD18 + 0.5 V

–1.0 to AVDD33 + 0.5 V
–0.5 to AVDD33 + 0.5 V

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

THERMAL CONDUCTIVITY 48ld QFN UNIT

T

Maximum junction temperature

J

Theta junction-to-ambient (still air) 30

q

JA

Theta junction-to-ambient (150 lfm) 24

q

Theta junction-to-board 8 °C/W

JB

q

Theta junction-to-pad 1.3 °C/W

Jp

(1) Air flow or heat sinking reduces qJAand may be required for sustained operation at 85° under maximum operating conditions.
(2) It is strongly recommended to solder the device thermal pad to the board ground plane.

(1) (2)

125 °C

°C/W

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s): DAC3283

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS — DC SPECIFICATIONS

(1)

www.ti.com

over operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RESOLUTION 16 Bits
DC ACCURACY

DNL Differential nonlinearity ±2
INL Integral nonlinearity ±4

1 LSB = IOUTFS/2

ANALOG OUTPUT

Coarse gain linearity ±0.04 LSB
Offset error Mid code offset ±0.01 %FSR

Gain error

With external reference ±2 %FSR

With internal reference ±2 %FSR
Gain mismatch With internal reference –2 2 %FSR
Minimum full scale output current 2 mA
Maximum full scale output current 20 mA
Output compliance range

(2)

Nominal full-scale current, IOUTFS = 16 x IBIAS

current.

IOUTFS = 20 mA AVDD –0.5V AVDD +0.5V V
Output resistance 300 kΩ
Output capacitance 5 pF

REFERENCE OUTPUT

V

ref

Reference output voltage 1.14 1.2 1.26 V
Reference output current

(3)

REFERENCE INPUT

V

EXTIO

Input voltage range 0.1 1.2 1.25 V
Input resistance 1 MΩ

External reference mode

Small signal bandwidth 472 kHz
Input capacitance 100 pF

TEMPERATURE COEFFICIENTS

Offset drift With external reference ±1

Gain drift With internal reference

Reference voltage drift ±8 ppm/°C

POWER SUPPLY

AVDD33 3.0 3.3 3.6 V
DACVDD18, DIGVDD18, CLKVDD18 1.7 1.8 1.9 V

I

(AVDD33)

I

(DIGDVDD)

I

(DACVDD18)

I

(CLKVDD18)

Analog supply current 149 mA
Digital supply current 340 mA
DAC supply current 55 mA

Mode 1 (below)

Clock supply current 37 mA

Mode 1: f

4x interpolation, Fs/4 mixer on, QMC on

Mode 2: f

2x interpolation, Mixer off, QMC on

P Power dissipation

Mode 3: Sleep mode

f

= 800MSPS, 4x interpolation, Fs/4 mixer on, 750 mW

DAC

CONFIG24 sleepa, sleepb set = 1

Mode 4: Power-Down mode

No clock, static data pattern,

CONFIG23 clkpath_sleep_a, clkpath_sleepb set = 1

CONFIG24 clkrecv_sleep, sleepa, sleepb set = 1

PSRR Power supply rejection ratio DC tested ±0.2 %FSR/V
T Operating range –40 25 85 °C

(1) Measured differential across IOUTA1 and IOUTA2 with 25 Ω each to AVDD.
(2) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,

resulting in reduced reliability of the DAC3283 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(3) Use an external buffer amplifier with high impedance input to drive any external load.

= 800MSPS,

DAC

= 491.52MSPS,

DAC

16

LSB

100 nA

ppm of

FSR/°C
±15
±30

ppm of

FSR/°C

1300 1450 mW

1000 mW

7 18 mW

6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): DAC3283

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS — AC SPECIFICATIONS

Over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG OUTPUT

f

DAC

t

s(DAC)

t

pd

t

r(IOUT)

t

f(IOUT)

Power-up
time

AC PERFORMANCE

SFDR f

IMD3 f

NSD dBc/Hz

WCDMA

(3)

(1) Measured single-ended into 50Ω load.
(2) 4:1 transformer output termination, 50Ω doubly terminated load
(3) Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at f

(1)

1x Interpolation 312.5

Maximum DAC output update rate 2x Interpolation 625 MSPS

4x Interpolation 800
Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10.4 ns
Output propagation delay DAC outputs are updated on the falling edge of DAC 2

clock. Does not include digital latency (see below).

ns

Output rise time 10% to 90% 220 ps
Output fall time 90% to 10% 220 ps

IOUT current settling to 1% of IOUTFS. Measured
DAC wake-up time from SDENB rising edge; Register CONFIG24, 90

toggle sleepa from 1 to 0.

IOUT current settling to less than 1% of IOUTFS.

µs

DAC sleep time Measured from SDENB rising edge; Register 90

CONFIG24, toggle sleepa from 0 to 1.

1x Interpolation 59

Digital latency clock

2x Interpolation 139

4x Interpolation 290

DAC

cycles

QMC 24

(2)

f
Spurious free dynamic range (0 to
f

/2)Tone at 0 dBFS

DAC

Third-order two-tone
intermodulation distortion

Each tone at –12 dBFS
Noise spectral density tone at

0dBFS
Adjacent channel leakage ratio,

single carrier
Alternate channel leakage ratio,

single carrier
Channel isolation f

= 800 MSPS, f

DAC

= 800 MSPS, f

DAC

f

= 800 MSPS, f

DAC

f

= 800 MSPS, f

DAC

= 800 MSPS, f

DAC

f

= 800 MSPS, f

DAC

f

= 800 MSPS, f

DAC

f

= 800 MSPS, f

DAC

f

= 737.28 MSPS, f

DAC

f

= 737.28 MSPS, f

DAC

f

= 737.28 MSPS, f

DAC

f

= 737.28 MSPS, f

DAC

= 800 MSPS, f

DAC

= 20.1 MHz 85

OUT

= 50.1 MHz 76 dBc

OUT

= 70.1 MHz 72

OUT

= 30 ± 0.5 MHz 93

OUT

= 50 ± 0.5 MHz 90 dBc

OUT

= 100 ± 0.5 MHz 86

OUT

= 10.1 MHz 162

OUT

= 80.1 MHz 160

OUT

= 30.72MHz 85

OUT

= 153.6MHz 81

OUT

= 30.72MHz 91

OUT

= 153.6MHz 85

OUT

= 10MHz 84 dBc

OUT

, PAR = 12dB. TESTMODEL 1, 10 ms

OUT

dBc

dBc

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s): DAC3283

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

www.ti.com

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVDS INTERFACE:D[7:0]P/N, DATACLKP/N, FRAMEP/N

f

DATA

f

BUS

V
V
V
Z
C

A,B+
A,B–
COM
T

L

Input data rate 312.5 MSPS
Byte-wide LVDS data transfer rate 1250 MSPS

Logic high differential input voltage threshold 150 400 mV
Logic low differential input voltage threshold –150 –400 mV
Input common mode 0.9 1.2 1.5 V
Internal termination 85 110 135 Ω
LVDS Input capacitance 2 pF

TIMING LVDS INPUTS: DATACLKP/N DOUBLE EDGE LATCHING – See Figure 40

t

s(DATA)

t

h(DATA)

t

(FRAME)

t

_align

Setup time, D[7:0]P/N and FRAMEP/N, valid FRAMEP/N latched on rising edge of
to either edge of DATACLKP/N DATACLKP/N only

Hold time, D[7:0]P/N and FRAMEP/N, valid FRAMEP/N latched on rising edge of
after either edge of DATACLKP/N DATACLKP/N only

FRAMEP/N pulse width f
Maximum offset between DATACLKP/N and FIFO bypass mode only f

DACCLKP/N rising edges DACCLK frequency in MHz –0.55

CLOCK INPUT (DACCLKP/N)

Duty cycle 40% 60%
Differential voltage

(2)

DACCLKP/N Input Frequency 800 MHz

OUTPUT STROBE (OSTRP/N)

f

OSTR

Frequency any positive integer f

Duty cycle 40% 60%
Differential voltage 0.4 1.0 V

TIMING OSTRP/N INPUT: DACCLKP/N RISING EDGE LATCHING

t

s(OSTR)

t

h(OSTR)

Setup time, OSTRP/N valid to rising edge of
DACCLKP/N

Hold time, OSTRP/N valid after rising edge
of DACCLKP/N

CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, TXENABLE

V

IH

V

IL

I

IH

I

IL

High-level input voltage 1.25 V
Low-level input voltage 0.54 V
High-level input current –40 40 mA
Low-level input current –40 40 mA

CI CMOS input capacitance 2 pF

V

OH

V

OL

ALARM_SDO, SDIO

ALARM_SDO, SDIO

SERIAL PORT TIMING – See Figure 32 and Figure 33

t

s(SDENB)

t

s(SDIO)

t

h(SDIO)

t

(SCLK)

Setup time, SDENB to rising edge of SCLK 20 ns
Setup time, SDIO valid to rising edge of

SCLK
Hold time, SDIO valid to rising edge of SCLK 5 ns

Period of SCLK

(1)

Byte-wide DDR format
DATACLK frequency = 625 MHz

–25 ps

375 ps

is DATACLK frequency in MHz 1/2f

DATACLK

is 1/2f

DACCLK

DATACLK

DACCLK

0.4 1.0 V

f

= f

OSTR

frequency in MHz

/ (n × 8 × Interp) where n is

DACCLK

DACCLK

is DACCLK

f

DACCLK

x interp)

/ (8

200 ps

200 ps

I

= –100 mA V

load

I

= –2mA V

load

I

= 100 mA 0.2 V

load

I

= 2 mA 0.5 V

load

DIGVDD18

–0.2

0.8 x

DIGVDD18

10 ns

Register CONFIG5 read (temperature
sensor read)

1 ms

All other registers 100 ns

ns
ns

(1) See LVDS INPUTS section for terminology.
(2) Driving the clock input with a differential voltage lower than 1V will result in degraded performance.

8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): DAC3283

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

(SCLKH)

t

(SCLKL)

t

d(Data)

Register CONFIG5 read (temperature

High time of SCLK

Low time of SCLK

Data output delay after falling edge of SCLK 10 ns

sensor read)
All other registers 40 ns
Register CONFIG5 read (temperature

sensor read)
All other registers 40 ns

0.4 ms

0.4 ms

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Link(s): DAC3283

-5

-4

-3

-2

-1

0

1

2

3

4

5

Error-LSB

0 10000 20000 30000 40000 50000 60000 70000

Code

0 10000 20000 30000 40000 50000 60000 70000

Code

-5

-4

-3

-2

-1

0

1

2

3

4

5

Error-LSB

50

55

60

65

70

75

80

85

90

95

100

0 50 100 150 200 250 300 350

f -MHz

OUT

0dBFS

-6dBFS

-12dBFS

f = 800 MSPS, 4x Interpolation,
IOUTFS = 20 mA

DAC

SecondHarmonic-dBc

0dBFS

-6dBFS

-12dBFS

f = 800 MSPS,4x Interpolation,
IOUTFS = 20 mA

DAC

50

55

60

65

70

75

80

85

90

95

100

SFDR-SpuriousFreeDynamicRange-dBc

0 50 100 150 200 250 300 350

f -MHz

OUT

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

Figure 1. INTEGRAL NON-LINEARITY Figure 2. DIFFERENTIAL NON-LINEARITY

www.ti.com

TYPICAL CHARACTERISTICS

Figure 3. SPURIOUS FREE DYNAMIC RANGE vs INPUT SCALE Figure 4. SECOND HARMONIC vs INPUT SCALE

10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): DAC3283

0 20 40 60 80 100 120

1xinterpolation

2xinterpolation

4xinterpolation

f -MHz

OUT

50

55

60

65

70

75

80

85

90

95

100

SFDR-SpuriousFreeDynamicRange-dBc

f = 312.5 MSPS, 0 dBFS,
IOUTFS = 20 mA

DAC

50

55

60

65

70

75

80

85

90

95

100

105

0 50 100 150 200 250 300 350

f -MHz

OUT

0dBFS

-6dBFS

-12dBFS

ThirdHarmonic-dBc

f = 800 MSPS, 4x Interpolation,
IOUTFS = 20 mA

DAC

20mA

10mA

2mA

50

55

60

65

70

75

80

85

90

95

100

SFDR-SpuriousFreeDynamicRange-dBc

0 50 100 150 200 250 300 350

f -MHz

OUT

f = 800 MSPS,4x Interpolation,
0 dBFS

DAC

f =200MSPS

DAC

f =400MSPS

DAC

f =800MSPS

DAC

50

55

60

65

70

75

80

85

90

95

100

SFDR-SpuriousFreeDynamicRange-dBc

0 50 100 150 200 250 300 350

f -MHz

OUT

4x Interpolation, 0 dBFS

IOUTFS = 20 mA

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

TYPICAL CHARACTERISTICS (continued)

Figure 5. THIRD HARMONIC vs INPUT SCALE Figure 6. SPURIOUS FREE DYNAMIC RANGE vs

INTERPOLATION

Figure 7. SPURIOUS FREE DYNAMIC RANGE vs f

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11

DAC

Figure 8. SPURIOUS FREE DYNAMIC RANGE vs IOUTFS

Product Folder Link(s): DAC3283

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Power-dBm

10 60 110 160 210

f-Frequency-MHz

2xInterpolation,
f =500MSPS,

f =50MHz

DAC

OUT

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Power-dBm

10 60 110 160 210

f-Frequency-MHz

2xInterpolation,
f =500MSPS,

f =100MHz

DAC

OUT

50

55

60

65

70

75

80

85

90

95

100

IMD3-dBc

0 50 100 150 200 250 300 350

f -MHz

OUT

0dBFS

-6dBFS

-12dBFS

f = 800 MSPS, 4x Interpolation,
Tonesat f ±0.5 MHz,
IOUTFS = 20 mA

DAC

OUT

10 60 110 160 210 260 310 360

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

10

Power-dBm

f-Frequency-MHz

4xInterpolation,0dBFS
f =800MSPS,

f =150MHz

DAC

OUT

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

TYPICAL CHARACTERISTICS (continued)

Figure 9. SINGLE TONE SPECTRAL PLOT Figure 10. SINGLE TONE SPECTRAL PLOT

www.ti.com

12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 11. SINGLE TONE SPECTRAL PLOT Figure 12. IMD3 vs INPUT SCALE

Product Folder Link(s): DAC3283

65

70

75

80

85

90

95

100

0 20 40 60 80 100 120 140 160

1xinterpolation

2xinterpolation

4xinterpolation

IMD3-dBc

f -MHz

OUT

f = 312.5 MSPS,
Tonesat f ±0.5 MHz,
0 dBFS, IOUTFS = 20 mA

DAC

OUT

f =200MSPS

DAC

f =400MSPS

DAC

f =800MSPS

DAC

50

55

60

65

70

75

80

85

90

95

100

IMD3-dBc

0 50 100 150 200 250 300 350

f -MHz

OUT

4x Interpolation,
Tonesat f ±0.5 MHz,

0 dBFS, IOUTFS = 20 mA

OUT

130

135

140

145

150

155

160

165

170

0 50 100 150 200 250 300 350

f -MHz

OUT

NSD-dBc/Hz

0dBFS

-6dBFS

-12dBFS

f = 800 MSPS, 4x Interpolation,
IOUTFS = 20 mA

DAC

50

55

60

65

70

75

80

85

90

95

100

105

20mA

10mA

2mA

0 50 100 150 200 250 300 350

f -MHz

OUT

IMD3-dBc

f = 800 MSPS, 4x Interpolation,
Tonesat f ±0.5 Mhz, 0 dBFS

DAC

OUT

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

TYPICAL CHARACTERISTICS (continued)

Figure 13. IMD3 vs INTERPOLATION Figure 14. IMD3 vs f

DAC

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13

Figure 15. IMD3 vs IOUTFS Figure 16. NSD vs INPUT SCALE

Product Folder Link(s): DAC3283

140

145

150

155

160

165

170

0 20 40 60 80 100 120 140 160

f -MHz

OUT

1xinterpolation

2xinterpolation

4xinterpolation

NSD-dBc/Hz

f = 312.5 MSPS, 0 dBFS,
IOUTFS = 20 mA

DAC

130

135

140

145

150

155

160

165

170

f =200MSPS

DAC

f =400MSPS

DAC

f =800MSPS

DAC

0 50 100 150 200 250 300 350

f -MHz

OUT

NSD-dBc/Hz

4x interpolation, 0 dBFS,
IOUTFS = 20 mA

60

65

70

75

80

85

0 50 100 150 200 250 300

ACLR,0dBFS

ACLR-6dBFS

Aternate,0dBFS

Alternate,-6dBFS

f -MHz

OUT

ACLR-dBc

f = 737.28 MSPS, 4x Interpolation,
IOUTFS = 20 mA

DAC

65

70

75

80

85

90

95

100

0 50 100 150 200 250 300

Adjacent0dBFS

Adjacent-6dBFS

Alternate0dBFS

Alternate-6dBFS

f -MHz

OUT

ACLR-dBc

f = 737.28 MSPS, 4x Interpolation,
IOUTFS = 20 mA

DAC

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

TYPICAL CHARACTERISTICS (continued)

Figure 17. NSD vs INTERPOLATION Figure 18. NSD vs f

www.ti.com

DAC

Figure 19. SINGLE CARRIER WCDMA ACLR vs INPUT SCALE Figure 20. FOUR CARRIER WCDMA ACLR vs INPUT SCALE

14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): DAC3283

A

Re f -1 2 .3 d Bm

*

*

*

CL RW R

RB W 3 0 k Hz

VB W 3 0 0 kH z

SW T 1 0 sAt t 1 0 d B*

1 R M

NO R

*

Ce nt er 7 0 MH z Spa n 2 5. 5 M Hz2. 55 MH z/

-1 20

-1 10

-1 00

-9 0

-8 0

-7 0

-6 0

-5 0

-4 0

-3 0

-2 0

Tx C h an n e l W -C D M A 3G P P FW D

Ba n d wi d th 3 .8 4 M Hz

P o w e r - 7 . 7 1 d B m

Ad j a ce n t Ch a nn e l

Ba n d wi d th 3 .8 4 M Hz

L o w e r - 8 2 . 2 0 d B

Sp a c in g 5 MH z

U p p e r - 8 2 . 0 7 d B

Al t e rn a te C h an n e l

Ba n d wi d th 3 .8 4 M Hz

L o w e r - 8 6 . 1 1 d B

Sp a c in g 10 MH z

U p p e r - 8 5 . 8 6 d B

4xInterpolation,0dBFS
f =737.28MSPS,

f =70MHz

DAC

OUT

A

Re f -1 2 .8 d Bm

*

*

*

CL RW R

RB W 30 k Hz

VB W 30 0 kH z

SW T 10 sAt t 1 0 d B*

1 R M

NO R

*

Ce nt er 1 53 .6 MH z Sp an 2 5 .5 M Hz2. 55 MH z/

-1 20

-1 10

-1 00

-9 0

-8 0

-7 0

-6 0

-5 0

-4 0

-3 0

-2 0

Tx C h an n e l W - CD M A 3G P P FW D

Ba n d wi d th 3 .8 4 M Hz

P o w e r - 8 . 0 7 d B m

Ad j a ce n t Ch a nn e l

Ba n d wi d th 3 .8 4 M Hz

L o w e r - 8 0 . 6 9 d B

Sp a c in g 5 MH z

U p p e r - 8 1 . 0 0 d B

Al t e rn a te C h an n e l

Ba n d wi d th 3 .8 4 M Hz

L o w e r - 8 4 . 0 7 d B

Sp a c in g 10 MH z

U p p e r - 8 4 . 1 6 d B

4xInterpolation,0dBFS
f =737.28MSPS,

f =153.6MHz

DAC

OUT

A

Re f -1 7. 9 d Bm

*

*

*

CL RW R

RB W 3 0 k Hz

VB W 3 00 kH z

SW T 1 0 sAt t 10 dB*

1 RM

NO R

*

Ce nt er 1 53 .6 M Hz Sp an 3 5 M Hz3. 5 M Hz /

-1 20

-1 10

-1 00

-9 0

-8 0

-7 0

-6 0

-5 0

-4 0

-3 0

-2 0

Tx C h an n e l W - CD M A 3G P P FW D

Ba n d wi d th 1 0 M Hz

P o w e r - 8 . 8 9 d B m

Ad j a ce n t Ch a nn e l

Ba n d wi d th 1 0 M Hz

L o w e r - 7 8 . 2 1 d B

Sp a c in g 1 0. 5 M Hz

U p p e r - 7 8 . 1 2 d B

4xInterpolation,0dBFS
f =737.28MSPS,

f =153.6MHz

DAC

OUT

A

Re f -1 7 .4 d Bm

*

*

*

CL RW R

RB W 3 0 k Hz

VB W 3 0 0 kH z

SW T 1 0 sAt t 1 0 dB*

1 R M

NO R

*

Ce nt er 7 0 MH z Sp an 3 5 M Hz3. 5 M Hz /

-1 20

-1 10

-1 00

-9 0

-8 0

-7 0

-6 0

-5 0

-4 0

-3 0

-2 0

Tx C h an n e l W - CD M A 3G P P F WD

Ba n d wi d th 1 0 M H z

P o w e r - 8 . 5 0 d B m

Ad j a ce n t Ch a nn e l

Ba n d wi d th 1 0 M H z

L o w e r - 7 9 . 6 4 d B

Sp a c in g 1 0. 5 M H z

U p p e r - 8 0 . 0 5 d B

4xInterpolation,0dBFS
f =737.28MSPS,

f =70MHz

DAC

OUT

A

Re f -1 9 d Bm

*

*

*

CL RW R

RB W 3 0 k Hz

VB W 3 0 0 kH z

SW T 1 0 sAtt 1 0 dB*

1 R M

NO R

*

Ce nt er 7 0 MH z Sp a n 65 MH z6. 5 M Hz /

-1 20

-1 10

-1 00

-9 0

-8 0

-7 0

-6 0

-5 0

-4 0

-3 0

Tx C h an n e l W - CD M A 3G P P F WD

Ba n dw i d th 2 0 M H z

P o w e r - 7 . 3 8 d B m

Ad j ac e n t C h a nn e l

Ba n dw i d th 2 0 M H z

L o w e r - 7 7 . 2 8 d B

Sp a ci n g 2 0. 5 M H z

U p p e r - 7 7 . 0 7 d B

4xInterpolation,0dBFS
f =737.28MSPS,

f =70MHz

DAC

OUT

A

Re f -1 9. 6 d Bm

*

*

*

CL RW R

RB W 3 0 k Hz

VB W 3 00 kH z

SW T 1 0 sAt t 1 0 dB*

1 RM

NO R

*

Ce nt er 1 53 .6 M Hz Sp an 6 5 M Hz6. 5 M Hz /

-1 20

-1 10

-1 00

-9 0

-8 0

-7 0

-6 0

-5 0

-4 0

-3 0

Tx C h an n e l W -C D MA 3 G P P F W D

Ba n dw i d th 2 0 M Hz

P o w e r - 8 . 0 2 d B m

Ad j ac e n t Ch a nn e l

Ba n dw i d th 2 0 M Hz

L o w e r - 7 3 . 4 1 d B

Sp a ci n g 2 0. 5 M Hz

U p p e r - 7 3 . 5 4 d B

2xInterpolation,0dBFS
f =492.52MSPS,

f =153.6MHz

DAC

OUT

DAC3283

www.ti.com

SLAS693A –MARCH 2010–REVISED APRIL 2010

TYPICAL CHARACTERISTICS (continued)

Figure 21. SINGLE CARRIER W-CDMA TEST MODEL 1 Figure 22. SINGLE CARRIER W-CDMA TEST MODEL 1

Figure 23. 10MHZ SINGLE CARRIER LTE Figure 24. 10MHZ SINGLE CARRIER LTE

Figure 25. 20MHZ SINGLE CARRIER LTE Figure 26. 20MHZ SINGLE CARRIER LTE

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Link(s): DAC3283

2x

1x

4x

QMC

Mixer

0

200

400

600

800

1000

1200

f -MSPS

DAC

0 100 200 300 400 500 600 700 800 900

Power-mW

0

50

100

150

200

250

300

350

2x

0 100 200 300 400 500 600 700 800 900

DVDD18-mA

f -MSPS

DAC

1x

4x

QMC

Mixer

0

10

20

30

40

50

60

70

80

0 100 200 300 400 500 600 700 800 900

DACVDD18-mA

f -MSPS

DAC

MixerOn

MixerOff

0

5

10

15

20

25

30

35

40

0 100 200 300 400 500 600 700 800 900

CLKVDD18-mA

f -MSPS

DAC

DAC3283

SLAS693A –MARCH 2010–REVISED APRIL 2010

TYPICAL CHARACTERISTICS (continued)

Figure 27. POWER vs f

DAC

Figure 28. DVDD18 vs f

www.ti.com

DAC

16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 29. DACVDD18 vs f

DAC

Product Folder Link(s): DAC3283

Figure 30. CLKVDD18 vs f

DAC