Texas Instruments CY74FCT841CTSOCT, CY74FCT841CTSOC, CY74FCT841CTQCT, CY74FCT841CTQC, CY74FCT841BTPC Datasheet

10-Bit Latch

CY54/74FCT841T

SCCS035 - September 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

Features

• Function,pinout,anddrivecompatiblewithFCT,F,and
AM29841 logic

• FCT-C speed at 5.5 ns max. (Com’l)
FCT-B speed at 6.5 ns max. (Com’l)

• Reduced V

OH

(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for significantly improved
noise characteristics

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Sink current 64 mA (Com’l),

32 mA (Mil)

Source current 32 mA (Com’l),

12 mA (Mil)

• High-speed parallel latches

• Buffered common latch enable input

Functional Description

The FCT841T bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and provide
extra data width for wider address/data paths or buses
carrying parity. The FCT841T is a buffered10-bit wide version
of the FCT373 function.

The FCT841T high-performance interface is designed for
high-capacitance load drive capability while providing
low-capacitance bus loading at both inputs and outputs.
Outputs are designed for low-capacitance bus loading in the
high impedance state and are designed with a power-off
disable feature to allow for live insertion of boards.

Logic Block Diagram

Pin Configurations

D

Y

0

OE

D

0

LE

Q

Y

1

D

1

Y

2

D

2

Y

3

D

3

Y

4

D

4

Y

5

D

5

Y

N- 1

D

N- 1

Y

N

D

N

DQQDQQDQQDQQDQQDQQDQ

Q

LE LE LE LE LE LE LE

D

Y

Q

LE

D

LE

OE

10

10

1
2
3
4
5
6
7
8
9
10
11
12

16

17

18

19

20

24
23
22
21

13

14

V

CC

15

DIP/QSOP/SOIC

Top View

OE

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

Y

8

GND

D

0

D

9

Y

0

Y

9

LE

Functional Block Diagram

LE

CY54/74FCT841T

2

Maximum Ratings

[2, 3]

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–65°C to +135°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Notes:

1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care, NC = No Change, Z = High Impedance.

2. Unless otherwise noted, these limits are over the operating free-air temperature range.

3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

CC

or ground.

4. T

A

is the “instant on” case temperature.

Pin Description

Name I/O Description

D I The latch data inputs.
LE I The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the

HIGH-to-LOW transition.
Y O The three-state latch outputs.
OE I The output enable control. When the OE is LOW, the outputs are enabled. When OE is HIGH, the outputs

Y

1

are in the high impedance (off) state.

Function Table

[1]

Inputs Internal Outputs

FunctionOE LE D O Y

H
H
H

X
H
H

X
L
H

X
L
H

Z
Z
Z

High Z

H L X NC Z Latched (High Z)

L
L

H
H

L
H

L
H

L
H

Transparent

L L X NC NC Latched

Operating Range

Range Range

Ambient

Temperature V

CC

Commercial All –40°C to +85°C 5V ± 5%
Military

[4]

All –55°C to +125°C 5V ± 10%

CY54/74FCT841T

3

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

[5]

Max. Unit

V

OH

Output HIGH Voltage VCC= Min., IOH= −32 mA Com’l 2.0 V

VCC= Min., IOH= −15 mA Com’l 2.4 3.3 V
VCC= Min., IOH= −12 mA Mil 2.4 3.3 V

V

OL

Output LOW Voltage VCC= Min., IOL= 64 mA Com’l 0.3 0.55 V

VCC= Min., IOL= 32 mA Mil 0.3 0.55 V

V

IH

Input HIGH Voltage 2.0 V

V

IL

Input LOW Voltage 0.8 V

V

H

Hysteresis

[6]

All inputs 0.2 V

V

IK

Input Clamp Diode Voltage VCC= Min., IIN= −18 mA −0.7 −1.2 V

I

I

Input HIGH Current VCC= Max., VIN= V

CC

5 µA

I

IH

Input HIGH Current VCC= Max., VIN= 2.7V ±1 µA

I

IL

Input LOW Current VCC= Max., VIN= 0.5V ±1 µA

I

OZH

Off State HIGH-Level Output
Current

VCC= Max., V

OUT

= 2.7V 10 µA

I

OZL

Off State LOW-Level
Output Current

VCC = Max., V

OUT

= 0.5V −10 µA

I

OS

Output Short Circuit Current

[7]

VCC= Max., V

OUT

= 0.0V −60 −120 −225 mA

I

OFF

Power-Off Disable VCC= 0V, V

OUT

= 4.5V ±1 µA

Capacitance

[6]

Parameter Description Typ.

[5]

Max. Unit

C

IN

Input Capacitance 5 10 pF

C

OUT

Output Capacitance 9 12 pF

Notes:

5. Typical values are at V

CC

=5.0V, TA=+25˚C ambient.

6. This parameter is specified but not tested.

7. Not more than one output should be shorted at a time. Durationof short should not exceedone second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I

OS

tests should be performed last.