Texas Instruments CY74FCT540CTQCT, CY74FCT540CTQC, CY74FCT541TSOCT, CY74FCT541TSOC, CY74FCT541CTSOCT Datasheet

8-Bit Buffers/Line Drivers

CY54/74FCT540T

CY54/74FCT541T

SCCS029 - May 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

Features

• Function, pinout, and drive compatible with FCT and

F logic

• FCT-C speed at 4.1 ns max. (Com’l)

FCT-A speed at 4.8 ns max. (Com’l)

• Reduced V

OH

(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-off disable feature

• ESD > 2000V

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• Sink current 64 mA (Com’l), 48 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)

• Extended commercial range of −40˚C to +85˚C

Functional Description

The FCT540T inverting buffer/line driver and the FCT541T
non-invertingbuffer/linedriverare designed to be employedas
memory address drivers, clock drivers, and bus-oriented
transmitters/receivers. The devices provide speed and drive
capabilities equivalent to their fastest bipolar logic
counterparts while reducing power dissipation. The input and
output voltage levels allow direct interface with TTL, NMOS,
and CMOS devices without external components.

The outputs are designed with a power-off disable feature to
allow for liv e insertion of boards.

Logic Block Diagram—FCT540T

Pin Configurations

1
2
3
4
5
6
7
8
9
10

11

12

16

17

18

19

20

13

14

V

CC

15

CERDIP/SOIC/QSOP

Top View

GND

O

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

OE

B

OE

A

O

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

OE

B

OE

A

FCT540T

1
2
3
4
5
6
7
8
9
10

11

12

16

17

18

19

20

13

14

V

CC

15

CERDIP/DIP/SOIC/QSOP

Top View

GND

O

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

OE

B

OE

A

O

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

OE

B

OE

A

Logic Block Diagram—FCT541T

FCT541T

CY54/74FCT540T

CY54/74FCT541T

2

Maximum Ratings

[2, 3]

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied.............................................–65°C to +135°C

Supply Voltage to Ground Potential............... –0.5V to +7.0V

DC Input Voltage ........................................... –0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Function Table FCT540T

[1]

Inputs

OutputOE

A

OE

B

D

L
L

H

L
L

H

L
H
X

H

L

Z

Function Table FCT541T

[1]

Inputs

OutputOE

A

OE

B

D

L
L

H

L
L

H

L
H
X

L
H
Z

Operating Range

Range Range

Ambient

Temperature V

CC

Commercial T, AT, CT –40°C to +85°C 5V ± 5%
Military

[4]

All –55°C to +125°C 5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

[5]

Max. Unit

V

OH

Output HIGH Voltage VCC= Min., IOH= –32 mA Com’l 2.0 V

VCC= Min., IOH= –15 mA Com’l 2.4 3.3 V
VCC= Min., IOH= –12 mA Mil 2.4 3.3 V

V

OL

Output LOW Voltage VCC= Min., IOL= 64 mA Com’l 0.3 0.55 V

VCC= Min., IOL= 48 mA Mil 0.3 0.55 V

V

IH

Input HIGH Voltage 2.0 V

V

IL

Input LOW Voltage 0.8 V

V

H

Hysteresis

[6]

All inputs 0.2 V

V

IK

Input Clamp Diode Voltage VCC= Min., IIN= –18 mA –0.7 –1.2 V

I

I

Input HIGH Current VCC= Max., VIN= V

CC

5 µA

I

IH

Input HIGH Current VCC= Max., VIN= 2.7V ±1 µA

I

IL

Input LOW Current VCC= Max., VIN= 0.5V ±1 µA

I

OZH

Off State HIGH-Level Output
Current

VCC= Max., V

OUT

= 2.7V 10 µA

I

OZL

Off State LOW-Level
Output Current

VCC= Max., V

OUT

= 0.5V –10 µA

I

OS

Output Short Circuit Current

[7]

VCC= Max,. V

OUT

= 0.0V –60 –120 –225 mA

I

OFF

Power-Off Disable VCC= 0V, V

OUT

= 4.5V ±1 µA

Notes:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance

2. Unless otherwise noted, these limits are over the operating free-air temperature range.

3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

CC

or ground.

4. T

A

is the “instant on” case temperature.

5. Typical values are at V

CC

=5.0V, TA=+25˚C ambient.

6. This parameter is specified but not tested.

7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parametric
tests, I

OS

tests should be performed last.

CY54/74FCT540T

CY54/74FCT541T

3

Capacitance

[6]

Parameter Description Test Conditions Typ.

[5]

Max. Unit

C

IN

Input Capacitance 5 10 pF

C

OUT

Output Capacitance 9 12 pF

Power Supply Characteristics

Parameter Description Test Conditions Typ.

[5]

Max. Unit

I

CC

Quiescent Power Supply Current VCC=Max., VIN≤ 0.2V, VIN≥ VCC–0.2V 0.1 0.2 mA

∆I

CC

Quiescent Power Supply Current
(TTL inputs)

VCC= Max., VIN= 3.4V, f1= 0, Outputs Open

[8]

0.5 2.0 mA

I

CCD

Dynamic Power Supply Current

[9]

VCC= Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f

1

= 10 MHz,

OEA=OEB=GND, orOEA=GND, OEB=V

CC,

VIN≤ 0.2V or VIN≥ VCC–0.2V

0.06 0.12 mA/MHz

I

C

Total Power Supply Current

[10]

VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f

1

=10 MHz,

OEA=OEB=GND, orOEA=GND, OEB=V

CC,

VIN≤0.2V or VIN≥VCC–0.2V

0.7 1.4 mA

VCC= Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f

1

=10 MHz,

OEA=OEB=GND, orOEA=GND, OEB=V

CC,

VIN= 3.4V or VIN= GND

1.0 2.4 mA

VCC= Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f

1

= 2.5 MHz,

OEA=OEB=GND, orOEA=GND, OEB=V

CC,

VIN≤ 0.2V or VIN≥ VCC–0.2V

1.3 2.6

[11]

mA

VCC= Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f

1

=2.5 MHz,

OEA=OEB=GND, orOEA=GND, OEB=V

CC,

VIN= 3.4V or VIN= GND

3.3 10.6

[11]

mA

Notes:

8. Per TTL driven input (V

IN

=3.4V); all other inputs at VCC or GND.

9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

10. I

C

=I

QUIESCENT

+ I

INPUTS

+ I

DYNAMIC

IC=ICC+∆ICCDHNT+I

CCD(f0

/2 + f1N1)

I

CC

= Quiescent Current with CMOS input levels

∆I

CC

= Power Supply Current for a TTL HIGH input (VIN=3.4V)

D

H

= Duty Cycle for TTL inputs HIGH

N

T

= Number of TTL inputs at D

H

I

CCD

= Dynamic Current caused by an input transition pair (HLH or LHL)

f

0

= Clock frequency for registered devices, otherwise zero

f

1

= Input signal frequency

N

1

= Number of inputs changing at f

1

All currents are in milliamps and all frequencies are in megahertz.

11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.

CY54/74FCT540T

CY54/74FCT541T

4

Switching Characteristics Over the Operating Range

[12]

Parameter Description

FCT540T/FCT541T FCT540AT/FCT541AT

Unit Fig. No.

[13]

Commercial Commercial

Min. Max. Min. Max.

t

PLH

t

PHL

Propagation Delay
Data to Output (FCT540)

1.5 8.5 1.5 4.8 ns 1, 2

t

PLH

t

PHL

Propagation Delay
Data to Output (FCT541)

1.5 8.0 1.5 4.8 ns 1, 3

t

PZH

t

PZL

Output Enable Time 1.5 10.0 1.5 6.2 ns 1, 7, 8

t

PHZ

t

PLZ

Output Disable Time 1.5 9.5 1.5 5.6 ns 1, 7, 8

Parameter Description

FCT540CT/FCT541CT

FCT540DT/

FCT541DT

Unit

Fig.

No.

[13]

Military Commercial Commercial

Min. Max. Min. Max. Min. Max.

t

PLH

t

PHL

Propagation Delay
Data to Output (FCT540)

1.5 4.7 1.5 4.1 1.5 3.8 ns 1, 2

t

PLH

t

PHL

Propagation Delay
Data to Output (FCT541)

1.5 4.6 1.5 4.1 1.5 3.8 ns 1, 3

t

PZH

t

PZL

Output Enable Time 1.5 6.5 1.5 5.8 1.5 5.2 ns 1, 7, 8

t

PHZ

t

PLZ

Output Disable Time 1.5 5.7 1.5 5.2 1.5 5.0 ns 1, 7, 8

Shaded areas contain preliminary information.

Notes:

12. Minimum limits are specified but not tested on Propagation Delays.

13. See “Parameter Measurement Information” in the General Information section.

CY54/74FCT540T

CY54/74FCT541T

5

Document #: 38-00260-B

Ordering Information—FCT540T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

4.1 CY74FCT540CTQCT Q5 20-Lead (150-Mil) QSOP Commercial

4.7 CY54FCT540CTDMB D6 20-Lead (300-Mil) CerDIP Military

Ordering Information—FCT541T

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

4.1 CY74FCT541CTQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT541CTSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC

4.6 CY54FCT541CTDMB D6 20-Lead (300-Mil) CerDIP Military

4.8 CY74FCT541ATPC P5 20-Lead (300-Mil) Molded DIP Commercial
CY74FCT541ATQCT Q5 20-Lead (150-Mil) QSOP
CY74FCT541ATSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC

8.0 CY74FCT541TSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC Commercial

Package Diagrams

20-Lead (300-Mil) CerDIP D6

MIL-STD-1835 D-8 Config.A

CY54/74FCT540T

CY54/74FCT541T

6

Package Diagrams (continued)

20-Lead (300-Mil) Molded DIP

P5

20-Lead Quarter Size Outline

Q5

CY54/74FCT540T

CY54/74FCT541T

7

Package Diagrams (continued)

20-Lead (300-Mil) Molded SOIC

S5

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Copyright  2000, Texas Instruments Incorporated