Texas Instruments CY74FCT2543TQCT, CY74FCT2543TQC, CY74FCT2543CTSOCT, CY74FCT2543CTSOC, CY74FCT2543CTQCT Datasheet

8-Bit Latched Transceive

r

CY74FCT2543T

SCCS042 - September 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

Features

• Function and pinout compatible with FCT and F logic

• FCT-C speed at 5.3 ns max.

FCT-A speed at 6.5 ns max.

• 25Ωoutputseriesresistorstoreducetransmissionline

reflection noise

• Reduced V

OH

(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• Sink current 12 mA
Source current 15 mA

• Separation controls for data flow in each direction

• Back to back latches for storage

• ESD > 2000V

• Extended commercial temp. range of –40˚C to +85˚C

Functional Description

The FCT2543T Octal Latched Tranceiver contains two sets of
eight D-type latches. Separate Latch Enable (

LEAB, LEBA)

and Output Enable (

OEAB, OEBA) permits each latch set to
have independent control of inputting and outputting in either
direction of data flow. For data flow from A to B, for example,
the A-to-B Enable (

CEAB) input must be LOW to enter data
from A or to take data from B, as indicated in the truth table.
With

CEAB LOW, a LOW signal on the A-to-B Latch Enable

(

LEAB) input makes the A-to-B latches transparent; a subse-

quent LOW-to-HIGH transition of the

LEAB signal puts the A
latches in the storage mode and their output no longer change
with the A inputs. With

CEAB and OEAB both LOW, the
three-state B output buffersare active and reflect data present
at the output of the A latches. Control of data from B to A is
similar,but uses

CEAB, LEAB, and OEAB inputs. On-chip ter­mination resistors have been added to the outputs to reduce
system noise caused by reflections. The FCT2543T can be
used to replace the FCT543T to reduce noise in an existing
design.

The outputs are designed with a power-off disable feature to
allow for liv e insertion of boards.

FCT2543T–1

LE

D

Q

LE

DQ

Detail A

Detail A x 7

A

0

A

2

A

1

A

3

A

4

A

6

A

5

A

7

B

0

B

2

B

1

B

3

B

4

B

6

B

5

B

7

OEBA

CEBA

LEBA

OEAB

CEAB

LEAB

FunctionalBlock Diagram Pin Configurations

1
2
3
4
5
6
7
8
9
10
11
12

16

17

18

19

20

24
23
22
21

13

14

V

CC

FCT2543T–3

15

SOIC/QSOP

Top View

LEBA

A

1

A

2

A

3

A

4

A

5

A

6

A

7

CEAB

B

1

B

2

B

3

B

4

B

5

B

6

B

7

OEAB

CEBAOEBA

A

0

GND

B

0

LEAB

CY74FCT2543T

2

Maximum Ratings

[4,5]

(Above which theuseful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .....................................−65°C to +150°C

Ambient Temperature with

Power Applied..................................................−65°C to +135°C

Supply Voltage to Ground Potential..................−0.5V to +7.0V

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Pin Description

Name Description

OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Enable Input (Active LOW)
CEBA B-to-A Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input (Active LOW)
LEBA B-to-A Latch Enable Input (Active LOW)
A A-to-B Data Inputs or B-to-A Three-State Outputs
B B-to-A Data Inputs or A-to-B Three-State Outputs

Function Table

[1,2]

Inputs Latch Outputs

CEAB LEAB OEAB A-to-B

[3]

B

H X X Storing High Z
X H X Storing X
X X H X High Z

L L L Transparent Current A Inputs
L H L Storing Previous A Inputs

Operating Range

Range

Ambient

Temperature V

CC

Commercial −40°C to +85°C 5V ± 5%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

[7]

Max. Unit

V

OH

Output HIGH Voltage VCC=Min., IOH=−15 mA 2.4 3.3 V

V

OL

Output LOW Voltage VCC=Min., IOL=12 mA 0.3 0.55 V

R

OUT

Output Resistance VCC=Min., IOL=12 mA 20 25 40 Ω

V

IH

Input HIGH Voltage 2.0 V

V

IL

Input LOW Voltage 0.8 V

V

H

Hysteresis

[8]

All inputs 0.2 V

V

IK

Input Clamp Diode Voltage VCC=Min., IIN=−18 mA −0.7 −1.2 V

I

IH

Input HIGH Current VCC=Max., VIN=V

CC

5 µA

I

IH

Input HIGH Current VCC=Max., VIN=2.7V ±1 µA

I

IL

Input LOW Current VCC=Max., VIN=0.5V ±1 µA

I

OZH

Off State HIGH-Level Output
Current

VCC=Max., V

OUT

=2.7V 15 µA

I

OZL

Off State LOW-Level
Output Current

VCC=Max., V

OUT

=0.5V −15 µA

I

OS

Output Short Circuit Current

[9]

VCC=Max., V

OUT

=0.0V −60 −120 −225 mA

I

OFF

Power-Off Disable VCC=0V, V

OUT

=4.5V ±1 µA

Notes:

1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.

2. A-to-B data flow shown: B-to-A is the same, except using

CEBA, LEBA, and OEBA.

3. Before LEAB LOW-to-HIGH transition.

4. Unless otherwise noted, these limits are over the operating free-air temperature range.

5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.

6. T

A

is the “instant on” case temperature.

CY74FCT2543T

3

Capacitance

[8]

Parameter Description Test Conditions Typ.

[7]

Max. Unit

C

IN

Input Capacitance 5 10 pF

C

OUT

Output Capacitance 9 12 pF

Power Supply Characteristics

Parameter Description Test Conditions Typ.

[7]

Max. Unit

I

CC

QuiescentPowerSupply Current VCC=Max., VIN≤0.2V, VIN≥VCC−0.2V 0.1 0.2 mA

∆I

CC

QuiescentPowerSupplyCurrent
(TTL inputs)

VCC=Max., VIN=3.4V,

[10]

f1=0, Outputs Open

0.5 2.0 mA

I

CCD

Dynamic Power Supply
Current

[11]

VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
CEAB and OEAB=LOW, CEBA=HIGH,
V

IN

≤0.2V or VIN≥VCC−0.2V

0.06 1.2 mA/
MHz

I

C

Total Power Supply Current

[12]

VCC=Max.,f0=10MHz,50% DutyCycle,Outputs
Open, One Bit Toggling at f

1

=5 MHz,
CEAB and OEAB=LOW, CEBA=HIGH,
f

0

=LEAB =10 MHz, VIN≤0.2V or VIN≥VCC−0.2V

0.7 1.4 mA

VCC=Max.,f0=10MHz,50% DutyCycle,Outputs
Open, One Bit Toggling at f

1

=5 MHz,
CEAB and OEAB=LOW, CEBA=HIGH,
f

0

=LEAB =10 MHz, VIN=3.4V or VIN=GND

1.2 3.4 mA

VCC=Max.,f0=10MHz,50% DutyCycle,Outputs
Open, Eight Bits Toggling at f

1

=5 MHz,
CEAB and OEAB=LOW, CEBA=HIGH,
f

0

=LEAB =10 MHz, VIN≤0.2V or VIN≥VCC−0.2V

2.8 5.6

[13]

mA

VCC=Max.,f0=10MHz,50% DutyCycle,Outputs
Open, Eight Bits Toggling at f

1

=5 MHz,
CEAB and OEAB=LOW, CEBA=HIGH,
f

0

=LEAB =10 MHz, VIN=3.4V or VIN=GND

5.1 14.6

[13]

mA

Notes:

7. Typical values are at V

CC

=5.0V, TA=+25˚C ambient.

8. This parameter is specified but not tested.

9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values.Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter
tests, I

OS

tests should be performed last.

10. Per TTL driven input (V

IN

=3.4V); all other inputs at VCC or GND.

11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

12. I

C

=I

QUIESCENT

+ I

INPUTS

+ I

DYNAMIC

IC=ICC+∆ICCDHNT+I

CCD(f0

/2 + f1N1)

I

CC

= Quiescent Current with CMOS input levels

∆I

CC

= Power Supply Current for a TTL HIGH input (VIN=3.4V)

D

H

= Duty Cycle for TTL inputs HIGH

N

T

= Number of TTL inputs at D

H

I

CCD

= Dynamic Current caused by an input transition pair (HLH or LHL)

f

0

= Clock frequency for registered devices, otherwise zero

f

1

= Input signal frequency

N

1

= Number of inputs changing at f

1

All currents are in milliamps and all frequencies are in megahertz.

13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.

CY74FCT2543T

4

Document #: 38−00348−A

Switching Characteristics Over the Operating Range

[14]

Parameter Description

CY74FCT2543T CY74FCT2543AT CY74FCT2543CT

Unit Fig. No.

[15]

Min. Max. Min. Max. Min. Max.

t

PLH

t

PHL

Propagation Delay
Transparent Mode
A to B or B to A

2.5 8.5 2.5 6.5 2.5 5.5 ns 1, 3

t

PLH

t

PHL

Propagation Delay
LEBA to A LEAB to B

2.5 12.5 2.5 8.0 2.5 7.0 ns 1, 5

t

PZH

t

PZL

Output Enable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B

2.0 12.0 2.0 9.0 2.0 8.0 ns 1, 7, 8

t

PZH

t

PZL

Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B

2.0 9.0 2.0 7.5 2.0 6.5 ns 1, 7, 8

t

S

Set-Up Time HIGH or LOW,
A or B to

LEBA or LEAB

2.0 2.0 2.0 ns 9

t

H

Hold Time HIGH or LOW,
A or B to

LEBA or LEAB

2.0 2.0 2.0 ns 9

t

W

Pulse Width LOW
LEBA or LEAB

5.0 5.0 5.0 ns 5

Ordering Information

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

5.3 CY74FCT2543CTQCT Q13 24-Lead (150-Mil) QSOP Commercial
CY74FCT2543CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

6.5 CY74FCT2543ATQCT Q13 24-Lead (150-Mil) QSOP Commercial
CY74FCT2543ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC

8.5 CY74FCT2543TQCT Q13 24-Lead (150-Mil) QSOP Commercial

Notes:

14. Minimum limits are specified but not tested on Propagation Delays.

15. See “Parameter Measurement Information” in the General Information section.

CY74FCT2543T

5

Package Diagrams

24-Lead Quarter Size Outline Q13

24-Lead (300-Mil) Molded SOIC S13

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated