Texas Instruments CD74HCT112E, CD74HC112M96, CD74HC112E, CD54HCT112F3A, CD54HC112F3A Datasheet

Data sheet acquired from Harris Semiconductor

/
j

SCHS141

March 1998

CD74HC112,

CD74HCT112

Dual J-K Flip-Flop with Set and Reset

Negative-Edge Trigger

[ /Title
(CD74
HC112
,
CD74
HCT11

2)
Sub­ect

(Dual
J-K
Flip­Flop
with
Setand
Reset
Nega-

Features

• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

o

C to 125oC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Description

The Harris CD74HC112 and CD74HCT112 utilize silicon­gate CMOS technology to achieve operating speeds
equivalent to LSTTL parts. They exhibit the low power
consumption of standard CMOS integrated circuits, together
with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q and
negative-going transition of the clock pulse. Set and Reset
are accomplished asynchronously by low-level inputs.

The 74HCT logic family is functionally as well as pin­compatible with the standard 74LS logic family.

.

Q outputs. They change state on the

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD74HC112E -55 to 125 16 Ld PDIP E16.3

(oC) PACKAGE

OH

PKG.

NO.

Pinout

CD74HC112, CD74HCT112

(PDIP)

TOP VIEW

16

1

1CP

2

1K

3

1J

4

1S

5

1Q

6

1Q

7

2Q

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

V

CC

15

1R

14

2R

13

2CP
2K

12

2J

11
10

2S

9

2Q

File Number 1843.1

Functional Diagram

CD74HC112, CD74HCT112

4

1S

1K

1CP

1R

2S

2K

2CP

2R

3

1J

2

1

15

10

11

2J

12

13

14

F/F 1

F/F 2

5

1Q

6

1Q

9

2Q

7

2Q

GND = 8
VCC = 16

TRUTH TABLE

INPUTS OUTPUTS

S R CP J K Q Q

LHXXXHL
H
L
H
H
HH
HH

L

L
H ↓
H ↓

XXXLH
X X X H (Note 3) H (Note 3)

L L No Change
HL

↓
↓

LH
H H Toggle

H H H X X No Change

NOTE:
H = High Level (Steady State)
L = Low Level (Steady State)
X = Don’t Care

↓

= High-to-Low Transition

3. Output states unpredictable if both S and R go High simultaneously after both being low at the same time.

2

CD74HC112, CD74HCT112

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

4. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

f

Thermal Resistance (Typical, Note 4) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC112, CD74HCT112

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load

NOTE:

5. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

I

CC

V

V

V

V

I

CC

∆I

IH

IL

OH

OL

I

I

CC

VCC or

GND

- - 4.5 to

- - 4.5 to

VIH or

V

IL

-0.02 4.5 3.98 - - 3.84 - 3.7 - V

VIH or

V

IL

V

CC

and

GND

VCC or

GND

V

CC

- 2.1

VCC (V)

0 6 - - 4 - 40 - 80 µA

5.5

5.5

- 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.26 - 0.33 - 0.4 V

4 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 4 - 40 - 80 µA

- 4.5 to

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

1S, 2S 0.5
1K, 2K 0.6
1R, 2R 0.65

1J, 2J, 1CP, 2CP 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

Pulse Width CP t

W

CONDITIONS

- 2 80 - - 100 - 120 - ns

V

CC

(V)

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC112, CD74HCT112

Prerequisite For Switching Specifications (Continued)

TEST

PARAMETER SYMBOL

Pulse Width R, St

Setup Time J, K, to CP t

SU

Hold Time J, K, to CP t

Removal Time R to CP, S to CP t

CP Frequency f

REM

MAX

W

H

CONDITIONS

- 2 80 - - 100 - 120 - ns

- 2 80 - - 100 - 120 - ns

-20--0-0-ns

- 2 80 - - 100 - 120 - ns

- 2 6 - - 5 - 4 - MHz

HCT TYPES

Pulse Width CP t
Pulse Width R, St
Setup Time J, K, to CP t
Hold Time J, K, to CP t
Removal Time R to CP, S to CP t
CP Frequency f

SU

W

H

REM

W

MAX

- 4.5 16 - - 20 - 24 - ns

- 4.5 18 - - 23 - 27 - ns

- 4.5 16 - - 20 - 24 - ns

- 4.5 3 - - 3 - 3 - ns

- 4.5 20 - - 25 - 30 - ns

- 4.5 30 - - 25 - 20 - MHz

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 0 - - 0 - 0 - ns
60--0-0-ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
CP to Q, Q

Propagation Delay,
S to Q, Q

Propagation Delay,
R to Q, Q

t

PLH

t

PLH

t

PLH

, tf = 6ns

r

25oC -40oC TO 85oC -55oC TO 125oC

, t

PHLCL

TEST

CONDITIONS

V

CC

(V)

= 50pF 2 - - 175 - 220 - 265 ns
CL= 50pF 4.5 - - 35 - 44 - 53 ns
CL= 15pF 5 - 14 - ----ns
CL= 50pF 6 - - 30 - 37 - 45 ns

, t

PHLCL

= 50pF 2 - - 155 - 195 - 235 ns
CL= 50pF 4.5 - - 31 - 39 - 47 ns
CL= 15pF 5 - 13 - ----ns
CL= 50pF 6 - - 26 - 33 - 40 ns

, t

PHLCL

= 50pF 2 - - 180 - 225 - 270 ns
CL= 50pF 4.5 - - 36 - 45 - 54 ns
CL= 15pF 5 - 15 - ----ns
CL= 50pF 6 - - 31 - 38 - 46 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD74HC112, CD74HCT112

Switching Specifications Input t

PARAMETER SYMBOL

Output Transition Time t

, tf = 6ns (Continued)

r

CONDITIONS

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

TEST

V

CC

(V)

CL= 50pF 4.5 - - 15 - 19 - 22 ns
CL= 50pF 6 - - 13 - 16 - 19 ns

Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

MAX

C

I

PD

- - - - 10 - 10 - 10 pF

CL = 15pF 5 - 60 - ----MHz

- 5-12-----pF

(Notes 6, 7)

HCT TYPES

Propagation Delay,
CP to Q, Q

Propagation Delay,
S to Q, Q

Propagation Delay,
R to Q, Q

Output Transition Time t
Input Capacitance C
CP Frequency f
Power Dissipation Capacitance

t

PLH

t

PLH

t

PLH

TLH

, t

, t

, t

, t

MAX

C

PD

I

PHLCL

= 50pF 4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - ----ns

PHLCL

= 50pF 4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - ----ns

PHLCL

= 50pF 4.5 - - 37 - 46 - 56 ns
CL = 15pF 5 - 14 - ----ns

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

CL = 15pF 5 - 60 - ----MHz

- 5-20-----pF

(Notes 6, 7)

NOTES:

6. CPD is used to determine the dynamic power consumption, per flip-flop.

7. PD = CPD V

2

fi + Σ CLfowhere fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%
10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

f

CL

50%

I

V

CC

GND

1.3V

I

fC

L

3V

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

6

CD74HC112, CD74HCT112

Test Circuits and Waveforms

(Continued)

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

90%
50%
10%

THL

90%

t

50%

10%

PLH

INVERTING

OUTPUT

t

PHL

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

tfC

L

V

50%

GND

t

H(L)

V
50%

t

SU(L)

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

CC

CC

= 6ns

tr = 6ns

INPUT

t

2.7V

1.3V

0.3V

THL

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

3V

GND

3V

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

1.3V

90%

1.3V
t

IC

t

PLH

TLH

t

THL

90%

1.3V
10%

t

PHL

GND

C

L

50pF

FIGURE 6. HCT SETUP TIMES,HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

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