CD4051B, CD4052B, CD4053B
[ /Title
(CD405
1B,
CD4052
B,
CD4053
B)
/Subject
(CMOS
Analog
Multiplexers/Dem
ultiplexers with
Logic
Level
Conversion)
/Author
()
/Keywords
(Harris
Semiconductor,
CD4000
Data sheet acquired from Harris Semiconductor
SCHS047D
CMOS Analog Multiplexers/Dem ultiple xer s
with Logic Level Con version
The CD4051B, CD4052B, and CD4053B analog multiplexers
are digitally-controlled analog switches having low ON
impedance and very low OFF leakage current. Control of
analog signals up to 20V
signal amplitudes of 4.5V to 20V (if V
V
DD-VEE
differences above 13V, a V
required). For example, if V
V
EE
controlled by digital inputs of 0V to 5V. These multiplexer
circuits dissipate extremely low quiescent power over the
full V
independent of the logic state of the control signals. When
a logic “1” is present at the inhibit input terminal, all
channels are off.
The CD4051B is a single 8-Channel multiplexerhavingthree
binary control inputs, A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned on,
and connect one of the 8 inputs to the output.
The CD4052B is a differential 4-Channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 of 4 pairs of channels to be
turned on and connect the analog inputs to the outputs.
The CD4053B is a triple 2-Channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole, double-throw
configuration.
When these devices are used as demultiplexers, the
“CHANNEL IN/OUT” terminals are the outputs and the
“COMMON OUT/IN” terminals are the inputs.
of up to 13V can be controlled; for VDD-VEElevel
= -13.5V, analog signals from -13.5V to +4.5V can be
DD-VSS
and VDD-VEE supply-voltage ranges,
can be achieved by digital
P-P
DD-VSS
DD-VSS
DD
of at least 4.5V is
= +4.5V, VSS = 0V, and
= 3V, a
Ordering Information
TEMP.RANGE
PART NUMBER
(oC) PACKAGE
August 1998 - Revised March 2000
Features
• Wide Range of Digital and Analog Signal Levels
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20V
• Low ON Resistance, 125Ω (Typ)Over15V
Range for V
• High OFF Resistance, Channel Leakage of ±100pA (Typ)
at V
DD-VEE
• Logic-Level Conversion for Digital Addressing Signals of
3V to 20V (V
Signals to 20V
• Matched Switch Characteristics, r
V
DD-VEE
• Very Low Quiescent Power Dissipation Under All DigitalControl Input and Supply Conditions, 0.2µW (Typ) at
V
DD-VSS
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 10% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range, 100nA at 18V and 25
• Break-Before-Make Switching Eliminates Channel
Overlap
DD-VEE
= 18V
= 15V
= VDD-VEE = 10V
= 18V
DD-VSS
= 3V to 20V) to Switch Analog
(VDD-VEE = 20V)
P-P
= 5Ω (Typ) for
ON
Signal Input
P-P
o
C
P-P
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
CD4051BF, CD4052BF,
CD4053BF
CD4051BE, CD4052BE,
CD4053BE
CD4051BM, CD4051BNS -55 to 125 16 Ld SOIC
CD4051BPW, CD4052BPW,
CD4053BPW
-55 to 125 16 Ld CERAMIC
DIP
-55 to 125 16 Ld PDIP
-55 to 125 16 Ld TSSOP
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
© 2000, Texas Instruments Incorporated
Copyright
Pinouts
CHANNELS
IN/OUT
COM OUT/IN
CHANNELS
IN/OUT
CD4051B, CD4052B, CD4053B
CD4051B (PDIP, CDIP, SOIC, TSSOP)
TOP VIEW
16
V
DD
2
15
14
1
CHANNELS IN/OUT
13
0
12
3
A
11
10
B
9
C
IN/OUT
OUT/IN CX OR CY
IN/OUT CX
INH
V
V
EE
SS
1
4
2
6
3
4
7
5
5
6
7
8
Y CHANNELS
COMMON “Y” OUT/IN
Y CHANNELS
CD4053B (PDIP, CDIP, TSSOP)
TOP VIEW
16
V
DD
OUT/IN bx OR by
15
14
OUT/IN ax OR ay
13
ay
12
ax
A
11
10
B
9
C
INH
V
V
by
bx
EE
SS
1
2
3
cy
4
5
6
7
8
CD4052B (PDIP, CDIP, TSSOP)
TOP VIEW
1
0
IN/OUT
IN/OUT
IN/OUT
INH
V
V
EE
SS
2
2
3
4
3
5
1
6
7
8
16
V
DD
2
15
X CHANNELS
IN/OUT
14
1
13
COMMON “X” OUT/IN
12
0
X CHANNELS
IN/OUT
3
11
10
A
9
B
Functional Block Diagrams
11
A †
10
B †
LOGIC
LEVEL
CONVERSION
9
C †
6
INH †
8 7
V
SS
†All inputs are protected by standard CMOS protection network.
CD4051B
CHANNEL IN/OUT
01234567
V
16
DD
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
V
EE
134 2 5 1 12 15 14
TG
TG
TG
TG
TG
TG
TG
TG
COMMON
OUT/IN
3
2
CD4051B, CD4052B, CD4053B
Functional Block Diagrams
16
10
A †
B †
INH †
9
6
LOGIC
LEVEL
CONVERSION
V
SS
(Continued)
V
DD
BINARY
1 OF 4
DECODER
WITH
INHIBIT
78
V
EE
TO
CD4052B
X CHANNELS IN/OUT
0123
1211 15 14
Y CHANNELS IN/OUT
TG
TG
TG
TG
TG
TG
TG
TG
4251
3210
COMMON X
OUT/IN
13
3
COMMON Y
OUT/IN
A †
B †
C †
INH †
CONVERSION
11
10
9
6
LOGIC
LEVEL
CD4053B
BINARY TO
1 OF 2
V
16
DD
DECODERS
WITH
INHIBIT
IN/OUT
V
DD
axaybxbycxcy
123 5 1 2 13
TG
TG
TG
TG
TG
TG
COMMON
OUT/IN
ax OR ay
14
COMMON
OUT/IN
bx OR by
15
COMMON
OUT/IN
cx OR cy
4
8
V
SS
V
7
EE
†All inputs are protected by standard CMOS protection network.
3
CD4051B, CD4052B, CD4053B
TRUTH TABLES
INPUT STATES
“ON” CHANNEL(S)INHIBIT C B A
CD4051B
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1 X X X None
CD4052B
INHIBIT B A
0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None
CD4053B
INHIBIT A OR B OR C
0 0 ax or bx or cx
0 1 ay or by or cy
1 X None
X = Don’t Care
4
CD4051B, CD4052B, CD4053B
Absolute Maximum Ratings
Supply Voltage (V+ to V-)
Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V
DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD51.
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V
RL = 100Ω, Unless Otherwise Specified (Note 3)
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
PARAMETER
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
Quiescent Device
Current, IDD Max
Drain to Source ON
Resistance rON Max
0 ≤ VIS≤ V
Change in ON
Resistance (Between
Any Two Channels),
∆r
ON
OFF Channel Leakage
Current: Any Channel
OFF (Max) or ALL
ChannelsOFF(Common
OUT/IN) (Max)
Capacitance: - -5 5- 5
Propagation Delay Time
(Signal Input to Output
DD
Input, C
IS
Output, C
Feedthrough
OS
CD4051 -----30 - pF
CD4052 -----18 - pF
CD4053 ----- 9 - pF
C
IOS
- - - 5 5 5 150 150 - 0.04 5 µA
- - - 10 10 10 300 300 - 0.04 10 µA
- - - 15 20 20 600 600 - 0.04 20 µA
- - - 20 100 100 3000 3000 - 0.08 100 µA
- 0 0 5 800 850 1200 1300 - 470 1050 Ω
- 0 0 10 310 330 520 550 - 180 400 Ω
- 0 0 15 200 210 300 320 - 125 240 Ω
- 0 0 5 -----15 - Ω
- 0 010-----10 - Ω
- 0 015-----5 - Ω
-0018±100 (Note 2) ±1000 (Note 2) - ±0.01 ±100
V
DD
RL = 200kΩ,
CL = 50pF,
tr, tf = 20ns
5 -----3060ns
10-----1530ns
15-----1020ns
Thermal Information
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
E Package . . . . . . . . . . . . . . . . . . . . . . 67 N/A
F Package . . . . . . . . . . . . . . . . . . . . . . 115 45
D Package . . . . . . . . . . . . . . . . . . . . . . 73 N/A
NS Package. . . . . . . . . . . . . . . . . . . . . 64 N/A
PW Package. . . . . . . . . . . . . . . . . . . . . 108 N/A
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC
(SOIC - Lead Tips Only)
= ±5V, AV = +1,
SUPPLY
UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 12525MIN TYP MAX
nA
(Note 2)
----- 5 - pF
-----0.2 - pF
5
CD4051B, CD4052B, CD4053B
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V
RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3)
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
PARAMETER
CONTROL (ADDRESS OR INHIBIT), V
Input Low Voltage, VIL,
Max
Input High Voltage, VIH,
Min
Input Current, IIN (Max) VIN = 0, 18 18 ±0.1 ±0.1 ±1 ±1-±10
Propagation Delay Time:
Address-to-Signal
OUT(ChannelsON or
OFF) See Figures 10,
11, 14
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning ON)
See Figure 11
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning
OFF) See Figure 15
Input Capacitance, C
(Any Address or Inhibit
Input)
NOTE:
2. Determined by minimum feasible leakage measurement for automatic testing.
VIL = V
through
1kΩ;
VIH = V
through
1kΩ
tr, tf = 20ns,
CL = 50pF,
RL = 10kΩ
tr, tf = 20ns,
CL = 50pF,
RL = 1kΩ
tr, tf = 20ns,
CL = 50pF,
RL = 10kΩ
IN
C
VEE = VSS,
DD
RL = 1kΩ to VSS,
IIS < 2µA on All
OFF Channels
DD
-100 5 -----200400ns
-100 5 -----130300ns
5 1.5 1.5 1.5 1.5 - - 1.5 V
103333 - - 3 V
154444 - - 4 V
5 3.5 3.5 3.5 3.5 3.5 - - V
1077777 - - V
15 11 11 11 11 11 - - V
0 0 5 -----450720ns
0 010-----160320ns
0 015-----120240ns
-5 0 5 -----225450ns
0 0 5 -----400720ns
0 010-----160320ns
0 015-----120240ns
0 0 5 -----200450ns
0 010-----90210ns
0 015-----70160ns
----- 5 7.5pF
SUPPLY
= ±5V, AV = +1,
-5
UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 12525MIN TYP MAX
±0.1 µA
Electrical Specifications
PARAMETER
Cutoff (-3dB) Frequency Channel ON (Sine Wave Input)
TEST CONDITIONS LIMITS
UNITSVIS (V) VDD (V) RL (kΩ) TYP
5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 30 MHz
VEE = VSS, CD4052 25 MHz
20Log
V
OS
----------- -
V
IS
3dB–=
VOS at Any Channel 60 MHz
CD4051 20 MHz
6
CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS LIMITS
PARAMETER
Total Harmonic Distortion, THD 2 (Note 3) 5 10 0.3 %
3 (Note 3) 10 0.2 %
5 (Note 3) 15 0.12 %
VEE = VSS, fIS = 1kHz Sine Wav e %
-40dB Feedthrough Frequency
(All Channels OFF)
-40dB Signal Crosstalk
Frequency
Address-or-Inhibit-to-Signal
Crosstalk
5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 8 MHz
VEE = VSS, CD4052 10 MHz
V
20Log
OS
----------- -
V
IS
40dB–=
VOS at Any Channel 8 MHz
CD4051 12 MHz
5 (Note 3) 10 1 Between Any 2 Channels 3 MHz
VEE = VSS, Between Sections,
20Log
V
OS
----------- -
V
IS
40dB–=
CD4052 Only
Between Any Two
Sections, CD4053
Only
-1010
Measured on Common 6 MHz
Measured on Any Chan-
10 MHz
nel
In Pin 2, Out Pin 14 2.5 MHz
In Pin 15, Out Pin 14 6 MHz
65 mV
(Note 4)
VEE=0,VSS=0,tr,tf=20ns,V
CC
65 mV
= VDD - VSS (Square Wave)
NOTES:
–
3. Peak-to-Peak voltage symmetrical about
4. Both ends of channel.
V
DDVEE
-----------------------------
2
UNITSVIS (V) VDD (V) RL (kΩ) TYP
PEAK
PEAK
Typical Performance Curves
600
VDD - VEE = 5V
500
400
300
200
, CHANNEL ON RESISTANCE (Ω)
100
ON
r
0
-4 -3 -2 -1 0 1 2 3 4
, INPUT SIGNAL VOLTAGE (V)
V
IS
FIGURE 1. CHANNEL ON RESISTANCEvsINPUTSIGNAL
VOLTAGE (ALL TYPES)
TA = 125oC
= 25oC
T
A
TA = -55oC
300
V
- VEE = 10V
DD
250
200
150
100
, CHANNEL ON RESISTANCE (Ω)
50
ON
r
5
0
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
, INPUT SIGNAL VOLTAGE (V)
V
IS
TA = 125oC
TA = 25oC
= -55oC
T
A
FIGURE 2. CHANNEL ON RESISTANCEvsINPUTSIGNAL
VOLTAGE (ALL TYPES)
7
CD4051B, CD4052B, CD4053B
Typical Performance Curves
(Continued)
600
TA = 25oC
500
VDD - VEE = 5V
400
300
200
10V
, CHANNEL ON RESISTANCE (Ω)
100
ON
r
0
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
V
, INPUT SIGNAL VOLTAGE (V)
IS
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
6
VDD = 5V
V
= 0V
SS
= -5V
V
EE
4
T
= 25oC
A
2
0
-2
, OUTPUT SIGNAL VOLTAGE (V)
-4
OS
V
-6
-6 -4 -2 0 2 4 6
V
, INPUT SIGNAL VOLTAGE (V)
IS
RL = 100kΩ, RL = 10kΩ
15V
1kΩ
500Ω
100Ω
250
VDD - VEE = 15V
200
TA = 125oC
150
100
TA = 25oC
TA = -55oC
50
, CHANNEL ON RESISTANCE (Ω)
ON
r
0
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
V
, INPUT SIGNAL VOLTAGE (V)
IS
FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
5
10
TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
C
= 50pF
L
4
10
3
10
2
10
, POWER DISSIPATION PACKAGE (µW)
D
P
10
1
VDD = 15V
VDD = 10V
VDD = 5V
CL = 15pF
2
10
10
10
SWITCHING FREQUENCY (kHz)
3
TEST CIRCUIT
V
DD
B/D
f
CD4029
ABC
V
DD
1011
100Ω
13
14
15
CD4051
12
1
5
2
4
8
7
100Ω
4
10
9
6
C
L
Ι
3
5
10
FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS
(CD4051B)
5
10
TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
CL = 50pF
4
10
3
10
2
10
, POWER DISSIPATION PACKAGE (µW)
D
P
10
1
VDD = 15V
CL = 15pF
10
VDD = 5V
10
VDD = 10V
2
10
f
V
DD
100Ω
100Ω
3
TEST CIRCUIT
V
DD
CD4029
B/D
AB
10
9
1
5
2
4
CD4052
6
7
8
Ι
4
10
3
C
13
12
14
15
11
SWITCHING FREQUENCY (kHz)
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4052B)
8
FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4051B)
5
10
TA = 25oC
ALTERNATING “O”
AND “I” PATTERN
C
= 50pF
L
4
10
, POWER DISSIPATION PACKAGE (µW)
P
3
10
CL = 15pF
10
VDD = 5V
2
10
2
10
D
10
1
SWITCHING FREQUENCY (kHz)
L
5
10
100Ω
10
VDD = 15V
V
DD
100Ω
3
VDD = 10V
TEST CIRCUIT
f
9
3
5
CD4053
10
11
6
7
8
Ι
4
10
4
C
L
12
13
2
1
15
14
5
10
FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4053B)
Test Circuits and Waveforms
= 15V
V
DD
VDD = 7.5V
CD4051B, CD4052B, CD4053B
VDD = 5V
VDD = 5V
7.5V
VSS = 0V
VEE = 0V
VSS = 0V
7
8
(A)
V
EE
= -7.5V
7
8
(B)
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels
are: “0” = VSSand “1” = VDD. The analog signal (through the TG) may
swing from VEE to VDD.
FIGURE 9. TYPICAL BIAS VOLTAGES
t
= 20ns
10%
90%
50%
r
90%
50%
90%
50%
TURN-ON TIME
10%
TURN-OFF TIME
tf = 20ns
10%
10%
1616 1616
5V
= 0V VSS = 0V
V
SS
10%
t
7
8
(C)
t
90%
50%
PHZ
VEE = -10V
5V
VEE = -5V
= 20ns
r
90%
TURN-OFF TIME
90%
50%
7
8
(D)
tf = 20ns
10%
10%
TURN-ON
TIME
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON
(RL = 1kΩ)
V
DD
1
16
2
15
3
4
5
6
7
8
CD4051
I
14
DD
13
12
11
10
9
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF
1
2
3
4
5
6
7
8
CD4052
FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF
(RL = 1kΩ)
V
DD
16
15
I
14
DD
13
12
11
10
9
1
2
3
4
5
6
7
8
CD4053
V
DD
16
15
14
13
12
11
10
I
DD
9
9
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms
V
DD
1
16
2
I
DD
1
16
2
3
4
5
6
7
8
CD4051
15
14
13
12
11
10
9
V
DD
V
EE
V
SS
15
3
14
4
13
5
12
6
11
7
10
8
9
CD4051
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
V
DD
OUTPUT
R
C
L
L
V
DD
V
SS
CLOCK
IN
V
SS
(Continued)
OUTPUT
C
L
V
EE
V
EE
V
DD
1
16
2
I
DD
15
3
14
4
13
5
12
6
11
7
10
8
9
CD4052
1
R
2
L
3
V
DD
4
5
SS
EE
6
7
8
V
V
CD4052
V
16
DD
15
14
13
12
11
V
DD
10
V
SS
9
V
SS
CLOCK
IN
V
EE
V
SS
1
2
3
4
5
6
7
8
CD4053
1
2
3
4
5
6
7
8
CD4053
V
DD
16
15
I
DD
14
13
12
11
10
9
V
DD
16
15
14
R
L
13
12
V
DD
11
V
SS
10
9
V
SS
CLOCK
IN
OUTPUT
C
L
V
EE
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
OUTPUT
1
2
3
4
5
6
7
8
AND t
16
15
14
13
12
11
10
PLH
V
V
R
DD
SS
L
CLOCK
IN
50pF
V
V
DD
V
EE
V
SS
EE
t
PHL
CD4051
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
V
DD
µA
1K
1
16
2
15
3
1K
V
IH
V
IL
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
14
4
13
5
12
6
11
7
10
89
CD4051B
V
DD
OUTPUT
1
50pF
R
L R
V
DD
V
SS
CLOCK
9
V
SS
V
IH
V
IL
IN
1
2
3
IH
IL
4
5
6
7
89
V
V
CD4052B
2
3
V
EE
4
5
V
DD
6
7
V
EE
V
8
SS
t
AND t
PHL
CD4052
V
DD
16
1K
15
14
13
1K
12
11
10
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
µA
16
15
14
13
12
11
10
9
PLH
V
V
DD
OUTPUT
50pF
L
V
DD
V
SS
CLOCK
IN
V
SS
V
IH
V
IL
V
IH
IL
1
16
V
15
14
13
12
11
10
PLH
16
15
14
13
12
11
10
DD
9
V
SS
V
DD
µA
1K
V
IH
V
IL
2
3
4
V
EE
5
V
DD
6
7
V
EE
V
8
SS
t
AND t
PHL
CD4053
1
1K
2
3
4
5
6
7
89
CD4053B
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
10
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms
V
DD
1
16
2
15
3
14
4
13
5
12
6
11
7
10
89
CD4051
Ι
CD4053
FIGURE 17. QUIESCENT DEVICE CURRENT FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT
V
1
16
2
15
3
14
4
13
5
12
6
11
7
10
89
V
SS
CD4051
CD4053
Ι
DD
Ι
NOTE: Measureinputssequentially,
to both VDD and VSS connect all
unused inputs to either VDDor VSS.
(Continued)
V
DD
1
16
2
15
3
14
4
13
5
12
6
11
7
10
89
CD4052
V
DD
V
SS
10kΩ
V
DD
TG
“ON”
V
SS
KEITHLEY
160 DIGITAL
MULTIMETER
1kΩ
RANGE
H.P.
MOSELEY
7030A
Y
X-Y
PLOTTER
X
CIRCUIT
V
DD
1
16
2
15
3
14
4
13
5
12
6
11
7
10
89
V
SS
CD4052
V
DD
Ι
V
SS
NOTE: Measureinputssequentially,
to both VDD and VSS connect all
unused inputs to either VDDor VSS.
FIGURE 19. INPUT CURRENT
5V
P-P
R
L
CHANNEL
OFF
CHANNEL
ON
5V
P-P
V
DD
OFF
CHANNEL
6
7
8
1K
RF
VM
COMMON
CHANNEL
ON
CHANNEL
OFF
R
L
RF
VM
R
L
FIGURE 20. FEEDTHROUGH (ALL TYPES) FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS
(ALL TYPES)
5V
P-P
CHANNEL IN X
ON OR OFF
CHANNEL IN Y
ON OR OFF
R
L
RF
VM
R
L
FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)
RF
VM
R
L
11
CD4051B, CD4052B, CD4053B
Test Circuits and Waveforms
DIFFERENTIAL
SIGNALS
(Continued)
CD4052
DIFF.
AMPLIFIER/
LINE DRIVER
DIFF.
MULTIPLEXING
FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B
Special Considerations
In applications where separate power sources are used to
drive V
should exceed V
provision avoids permanent current flow or clamp action on
the V
CD4051B, CD4052B or CD4053B.
and the signal inputs, the VDDcurrent capability
DD
DD/RL(RL
supply when power is applied or removed from the
DD
= effective external load). This
COMMUNICATIONS
LINK
DIFF.
RECEIVER
CD4052
DEMULTIPLEXING
A
B
C
Q
A
D
E
1/2
B
CD4556
E
0
Q
1
Q
2
A
B
C
INH
A
B
C
INH
A
B
C
INH
CD4051B
CD4051B
CD4051B
COMMON
OUTPUT
FIGURE 24. 24-TO-1 MUX ADDRESSING
12
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated
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