Texas Instruments CD4051BPWR, CD4051BPW, CD4051BNSR, CD4051BM96, CD4051BM Datasheet

CD4051B, CD4052B, CD4053B

[ /Title
(CD405
1B,
CD4052
B,
CD4053
B)
/Sub­ject
(CMOS
Analog
Multi­plex­ers/Dem
ultiplex­ers with
Logic
Level
Conver­sion)
/Author
()
/Key­words
(Harris
Semi­conduc­tor,
CD4000

Data sheet acquired from Harris Semiconductor
SCHS047D

CMOS Analog Multiplexers/Dem ultiple xer s
with Logic Level Con version

The CD4051B, CD4052B, and CD4053B analog multiplexers
are digitally-controlled analog switches having low ON
impedance and very low OFF leakage current. Control of
analog signals up to 20V
signal amplitudes of 4.5V to 20V (if V
V

DD-VEE

differences above 13V, a V
required). For example, if V
V

EE

controlled by digital inputs of 0V to 5V. These multiplexer
circuits dissipate extremely low quiescent power over the
full V
independent of the logic state of the control signals. When
a logic “1” is present at the inhibit input terminal, all
channels are off.

The CD4051B is a single 8-Channel multiplexerhavingthree
binary control inputs, A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned on,
and connect one of the 8 inputs to the output.

The CD4052B is a differential 4-Channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 of 4 pairs of channels to be
turned on and connect the analog inputs to the outputs.

The CD4053B is a triple 2-Channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole, double-throw
configuration.

When these devices are used as demultiplexers, the
“CHANNEL IN/OUT” terminals are the outputs and the
“COMMON OUT/IN” terminals are the inputs.

of up to 13V can be controlled; for VDD-VEElevel

= -13.5V, analog signals from -13.5V to +4.5V can be

DD-VSS

and VDD-VEE supply-voltage ranges,

can be achieved by digital

P-P

DD-VSS

DD-VSS

DD

of at least 4.5V is

= +4.5V, VSS = 0V, and

= 3V, a

Ordering Information

TEMP.RANGE

PART NUMBER

(oC) PACKAGE

August 1998 - Revised March 2000

Features

• Wide Range of Digital and Analog Signal Levels

- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V

- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20V

• Low ON Resistance, 125Ω (Typ)Over15V
Range for V

• High OFF Resistance, Channel Leakage of ±100pA (Typ)
at V

DD-VEE

• Logic-Level Conversion for Digital Addressing Signals of
3V to 20V (V
Signals to 20V

• Matched Switch Characteristics, r
V

DD-VEE

• Very Low Quiescent Power Dissipation Under All Digital­Control Input and Supply Conditions, 0.2µW (Typ) at
V

DD-VSS

• Binary Address Decoding on Chip

• 5V, 10V and 15V Parametric Ratings

• 10% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range, 100nA at 18V and 25

• Break-Before-Make Switching Eliminates Channel
Overlap

DD-VEE

= 18V

= 15V

= VDD-VEE = 10V

= 18V

DD-VSS

= 3V to 20V) to Switch Analog

(VDD-VEE = 20V)

P-P

= 5Ω (Typ) for

ON

Signal Input

P-P

o

C

P-P

Applications

• Analog and Digital Multiplexing and Demultiplexing

• A/D and D/A Conversion

• Signal Gating

CD4051BF, CD4052BF,
CD4053BF

CD4051BE, CD4052BE,
CD4053BE

CD4051BM, CD4051BNS -55 to 125 16 Ld SOIC

CD4051BPW, CD4052BPW,
CD4053BPW

-55 to 125 16 Ld CERAMIC
DIP

-55 to 125 16 Ld PDIP

-55 to 125 16 Ld TSSOP

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

© 2000, Texas Instruments Incorporated

Copyright

Pinouts

CHANNELS

IN/OUT

COM OUT/IN

CHANNELS

IN/OUT

CD4051B, CD4052B, CD4053B

CD4051B (PDIP, CDIP, SOIC, TSSOP)

TOP VIEW

16

V

DD

2

15
14

1

CHANNELS IN/OUT

13

0

12

3
A

11
10

B

9

C

IN/OUT

OUT/IN CX OR CY

IN/OUT CX

INH
V
V

EE
SS

1

4

2

6

3
4

7

5

5

6
7
8

Y CHANNELS

COMMON “Y” OUT/IN

Y CHANNELS

CD4053B (PDIP, CDIP, TSSOP)

TOP VIEW

16

V

DD

OUT/IN bx OR by

15
14

OUT/IN ax OR ay

13

ay

12

ax
A

11
10

B

9

C

INH
V
V

by
bx

EE
SS

1
2
3

cy

4
5
6
7
8

CD4052B (PDIP, CDIP, TSSOP)

TOP VIEW

1

0

IN/OUT

IN/OUT

IN/OUT

INH
V
V

EE
SS

2

2

3
4

3

5

1

6
7
8

16

V

DD

2

15

X CHANNELS
IN/OUT

14

1

13

COMMON “X” OUT/IN

12

0

X CHANNELS
IN/OUT

3

11
10

A

9

B

Functional Block Diagrams

11

A †

10

B †

LOGIC
LEVEL

CONVERSION

9

C †

6

INH †

8 7

V

SS

†All inputs are protected by standard CMOS protection network.

CD4051B

CHANNEL IN/OUT

01234567

V

16

DD

BINARY

TO

1 OF 8

DECODER

WITH

INHIBIT

V

EE

134 2 5 1 12 15 14

TG

TG

TG

TG

TG

TG

TG

TG

COMMON

OUT/IN

3

2

CD4051B, CD4052B, CD4053B

Functional Block Diagrams

16

10

A †

B †

INH †

9

6

LOGIC

LEVEL

CONVERSION

V

SS

(Continued)

V

DD

BINARY

1 OF 4

DECODER

WITH

INHIBIT

78

V

EE

TO

CD4052B

X CHANNELS IN/OUT

0123

1211 15 14

Y CHANNELS IN/OUT

TG

TG

TG

TG

TG

TG

TG

TG

4251
3210

COMMON X

OUT/IN

13

3

COMMON Y

OUT/IN

A †

B †

C †

INH †

CONVERSION

11

10

9

6

LOGIC
LEVEL

CD4053B

BINARY TO

1 OF 2

V

16

DD

DECODERS

WITH

INHIBIT

IN/OUT

V

DD

axaybxbycxcy
123 5 1 2 13

TG

TG

TG

TG

TG

TG

COMMON

OUT/IN

ax OR ay

14

COMMON

OUT/IN

bx OR by

15

COMMON

OUT/IN

cx OR cy

4

8

V

SS

V

7

EE

†All inputs are protected by standard CMOS protection network.

3

CD4051B, CD4052B, CD4053B

TRUTH TABLES

INPUT STATES

“ON” CHANNEL(S)INHIBIT C B A

CD4051B

0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1 X X X None

CD4052B

INHIBIT B A

0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None

CD4053B

INHIBIT A OR B OR C

0 0 ax or bx or cx
0 1 ay or by or cy
1 X None

X = Don’t Care

4