Texas Instruments BQ4285S-SB2, BQ4285Q, BQ4285P-SB2, BQ4285S-SB2TR Datasheet

1

Features

➤ Direct clock/calendar replace-

ment for IBM

®

AT-compatible

computers and other applications

➤ Functionally compatible with the

DS1285

-

Closely matches MC146818A
pin configuration

➤ 114 bytes of general nonvolatile

storage

➤ Automatic backup and write-

protect control to external SRAM

➤ 160 ns cycle time allows fast bus

operation

➤ Selectable Intel or Motorola bus

timing (PLCC), Intel bus timing
(DIP and SOIC)

➤ Less than 0.5

µ

A load under bat-

tery operation

➤ 14 bytes for clock/calendar and

control

➤ Calendar in day of the week, day of

the month, months, and years, with
automatic leap-year adjustment

➤ Time of day in seconds, minutes,

and hours

-

12- or 24-hour format

-

Optional daylight saving
adjustment

➤ BCD or binary format for clock

and calendar data

➤ Programmable square wave out-

put

➤ Three individually maskable in-

terrupt event flags:

-

Periodic rates from 122µs to
500 ms

-

Time-of-day alarm once per
second to once per day

- End-of-clock update cycle

➤ 24-pin plastic DIP or SOIC

General Description

The CMOS bq4285 is a low-power
microprocessor peripheral providing
a time-of-day clock and 100-year cal­endar with alarm features and bat­tery operation. Other features include
three maskable interrupt sources,
square wave output, and 114 bytes of
general nonvolatile storage.

The bq4285 write-protects the clock,
calendar, and storage registers dur­ing power failure. A backup battery
then maintains data and operates
the clock and calendar.

The bq4285 is a fully compatible real­time clock for IBM AT-compatible com­puters and other applications. The only
external components are a 32.768kHz
crystal and a backup battery.

The bq4285 integrates a battery­backup controller to make a standard
CMOS SRAM nonvolatile during
power-fail conditions. During power­fail, the bq4285 automatically write­protects the external SRAM and pro­vides a V

CC

output sourced from the

clock backup battery.

PN428502.eps

28-Pin PLCC

5
6

7
8
9
10
11

25
24

23
22
21
20
19

432

1

282726

12131415161718

AD

0

AD

1

AD

2

AD

3

AD

4

AD

5

NC

AD

6

NC

AD

7

V

SSCSAS

NC

CE

IN

BC
INT
RST
DS

V

SS

R/W

X2X1MOT

V

OUTVCC

SQW

CE

OUT

Pin Names

AD0–AD7Multiplexed address/data

input/output

MOT Bus type select input

(PLCC only )

CS

Chip select input

AS Address strobe input
DS Data strobe input
R/W

Read/write input

INT

Interrupt request output

RST

Reset input

SQW Square wave output
BC 3V backup cell input
X1–X2 Crystal inputs

NC No connect
CE

IN

RAM chip enable input

CE

OUT

RAM chip enable output

V

OUT

Supply output

V

CC

+5V supply

V

SS

Ground

Jan.1999 D

1

PN428501.eps

24-Pin DIP or SOIC

2
3

4
5
6
7
8

24
23

22
21
20
19
18

17
9
10

16

15
11
12

14

13

V

CC
SQW
CE

OUT

BC
INT
RST
DS
V

SS
R/W

AS
CS

V

OUT

X

1

X

2

AD

0

AD

1

AD

2

AD

3

AD

4

AD

5

AD

6

AD

7

V

SS

CE

IN

Pin Connections

bq4285

Real-Time Clock(RTC)With NVRAM Control

Block Diagram

Pin Descriptions

AD0–AD7Multiplexed address/data input/

output

The bq4285 bus cycle consists of two
phases: the address phase and the data­transfer phase. The address phase pre­cedes the data-transfer phase. During the
address phase, an address placed on
AD

0

–AD7is latched into the bq4285 on the
falling edge of the AS signal. During the
data-transfer phase of the bus cycle, the
AD0–AD7pins serve as a bidirectional data
bus.

MOT Bus type select input (PLCC package

only)

MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to V

CC

for Motorola timing or to VSSfor
Intel timing (see Table 1). The setting
should not be changed during system opera­tion. MOT is internally pulled low by a 20K

Ω

resistor. For the DIP and SOIC pack­ages, this pin is internally connected to VSS,
enabling the bus timing for the Intel archi­tecture.

CS

Chip select input

CS should be driven low and held stable
during the data-transfer phase of a bus cy­cle accessing the bq4285.

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Jan.1999 D

Bus

Type

MOT

LevelDSEquivalent

R/W

EquivalentASEquivalent

Motorola V

CC

DS, E, or

Φ

2

R/W AS

Intel V

SS

RD,
MEMR,
or I/OR

WR,
MEMW,
or I/OW

ALE

Table 1. Bus Setup

bq4285

AS Address strobe input

AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad­dress on AD0–AD7. This demultiplexing
process is independent of the CS signal.
For DIP, SOIC, and PLCC packages with
MOT=VCC, the AS input is provided a sig­nal similar to ALE in an Intel-based sys­tem.

DS Data strobe input

For DIP, SOIC, and PLCC packages with
MOT=V

SS

, the DS input is provided a sig­nal similar to RD, MEMR, or I/OR in an
Intel-based system. The falling edge on DS
is used to enable the outputs during a read
cycle.

For the PLCC package, when MOT = VCC,
DS controls data transfer during a bq4285
bus cycle. During a read cycle, the bq4285
drives the bus after the rising edge on DS.
During a write cycle, the falling edge on DS
is used to latch write data into the chip.

R/W

Read/write input

For DIP, SOIC, and PLCC packages with
MOT=VSS, R/W is provided a signal simi­lar to WR, MEMW, or I/OW in an Intel­based system. The rising edge on R/W
latches data into the bq4285.

For the PLCC package, when MOT = VCC,
the level on R/W identifies the direction of
data transfer. A high level on R/W indi­cates a read bus cycle, whereas a low on
this pin indicates a write bus cycle.

INT

Interrupt request output

INT is an open-drain output. INT is as­serted low when any event flag is set and
the corresponding event enable bit is also
set. INT becomes high-impedance
whenever register C is read (see the Con­trol/Status Registers section).

RST

Reset input

The bq4285 is reset when RST is pulled
low. When reset, INT becomes high­impedance, and the bq4285 is not accessi­ble. Table 4 in the Control/Status Registers
section lists the register bits that are
cleared by a reset.

Reset may be disabled by connecting RST
to VCC. This allows the control bits to re­tain their states through power­down/power-up cycles.

SQW Square-wave output

SQW may output a programmable fre­quency square-wave signal during normal
(V

CC

valid) system operation. Any one of
the 13 specific frequencies may be selected
through register A. This pin is held low
when the square-wave enable bit (SQWE)
in register B is 0 (see the Control/Status
Registers section).

BC 3V backup cell input

BC should be connected to a 3V backup cell
for RTC operation and storage register non­volatility in the absence of power. When
V

CC

slews down past VBC(3V typical), the
integral control circuitry switches the
power source to BC. When VCCreturns
above VBC, the power source is switched to
VCC.

Upon power-up, a voltage within the V

BC

range must be present on the BC pin for
the oscillator to start up.

X1–X2 Crystal inputs

The X1–X2 inputs are provided for an ex­ternal 32.768Khz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci­tance. A trimming capacitor may be neces­sary for extremely precise time-base gen­eration.

CE

IN

External RAM chip enable input,
active low

CE

IN

should be driven low to enable the
controlled external RAM. CEINis internally
pulled up with a 50KΩresistor.

CE

OUT

External RAM chip enable output,
active low

When power is valid, CE

OUT

reflects CE

IN.

V

OUT

Supply output

V

OUT

provides the higher of VCCor VBC,
switched internally, to supply external RAM.

V

CC

+5V supply

V

SS

Ground

3

Jan.1999 D

bq4285

Functional Description

Address Map

The bq4285 provides 14 bytes of clock and control/status
registers and 114 bytes of general nonvolatile storage.
Figure 1 illustrates the address map for the bq4285.

Update Period

The update period for the bq4285 is one second. The
bq4285 updates the contents of the clock and calendar
locations during the update cycle at the end of each up-

date period (see Figure 2). The alarm flag bit may also
be set during the update cycle.

The bq4285 copies the local register updates into the
user buffer accessed by the host processor. Whena1is
written to the update transfer inhibit bit (UTI) in regis­ter B, the user copy of the clock and calendar bytes re­mains unchanged, while the local copy of the same bytes
continues to be updated every second.

The update-in-progress bit (UIP) in register A is set
t

BUC

time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.

4

Figure 1. Address Map

Figure 2. Update Period Timing and UIP

Jan.1999 D

bq4285

Programming the RTC

The time-of-day, alarm, and calendar bytes can be writ­ten in either the BCD or binary format (see Table 2).

These steps may be followed to program the time, alarm,
and calendar:

1. Modify the contents of register B:

a. Write a 1 to the UTI bit to prevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to the data

format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.

c. Write the appropriate value to the hour

format (HF) bit.

2. Write new values to all the time, alarm, and

calendar locations.

3. Clear the UTI bit to allow update transfers.

On the next update cycle, the RTC updates all 10 bytes
in the selected format.

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Jan.1999 D

Address RTC Bytes

Range

Decimal Binary

Binary-Coded

Decimal

0 Seconds 0–59 00H–3BH 00H–59H

1 Seconds alarm 0–59 00H–3BH 00H–59H

2 Minutes 0–59 00H–3BH 00H–59H

3 Minutes alarm 0–59 00H–3BH 00H–59H

4 Hours, 12-hour format 1–12 01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours, 24-hour format 0–23 00H–17H 00H–23H

5 Hours alarm, 12-hour format 1–12 01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours alarm, 24-hour format 0–23 00H–17H 00H–23H

6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H

7 Day of month 1–31 01H–1FH 01H–31H

8 Month 1–12 01H–0CH 01H–12H

9 Year 0–99 00H–63H 00H–99H

Table 2. Time, Alarm, and Calendar Formats

bq4285

Square-Wave Output

The bq4285 divides the 32.768kHz oscillator frequency
to produce the 1 Hz update frequency for the clock and
calendar. Thirteen taps from the frequency divider are
fed to a 16:1 multiplexer circuit. The output of this mux
is fed to the SQW output and periodic interrupt genera­tion circuitry. The four least-significant bits of register
A, RS0–RS3, select among the 13 taps (see Table 3). The
square-wave output is enabled by writinga1tothe
square-wave enable bit (SQWE) in register B.

Interrupts

The bq4285 allows three individually selected interrupt
events to generate an interrupt request. These three in­terrupt events are:

■

The periodic interrupt, programmable to occur once
every 122µs to 500 ms

■

The alarm interrupt, programmable to occur once per
second to once per day

■

The update-ended interrupt, which occurs at the end
of each update cycle

Each of the three interrupt events is enabled by an indi­vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre­sponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT

high-impedance.

Two methods can be used to process bq4285 interrupt
events:

■

Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.

■

Do not enable the interrupts and use a polling
routine to periodically check the status of the flag
bits.

The individual interrupt sources are described in detail
in the following sections.

6

Register A Bits Square Wave Periodic Interrupt

RS3 RS2 RS1 RS0 Frequency Units Period Units

0000None None

0001256Hz3.90625 ms

0010128Hz7.8125 ms

00118.192 kHz 122.070

µ

s

01004.096 kHz 244.141

µ

s

01012.048 kHz 488.281

µ

s

01101.024 kHz 976.5625

µ

s

0111512Hz1.95315 ms

1000256Hz3.90625 ms

1001128Hz7.8125 ms

101064Hz15.625 ms

101132Hz31.25 ms

110016Hz62.5 ms

11018Hz125 ms

11104Hz250 ms

11112Hz500 ms

Table 3. Square-Wave Frequency/Periodic Interrupt Rate

Jan.1999 D

bq4285

PeriodicInterrupt

The mux output used to drive the SQW output also drives
the interrupt-generation circuitry. If the periodic interrupt
event is enabled by writinga1totheperiodic interrupt
enable bit (PIE) in register C, an interrupt request is gen­erated once every 122µs to 500ms. The period between in­terrupts is selected by the same bits in register A that se­lect the square wave frequency (see Table 3).

Alarm Interrupt

During each update cycle, the RTC compares the hours,
minutes, and seconds bytes with the three corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is gen­erated.

An alarm byte may be removed from the comparison by
setting it to a “don’t care” state. An alarm byte is set to a
“don’t care” state by writinga1toeachofitstwomost­significant bits. A “don’t care” state may be used to select
the frequency of alarm interrupt events as follows:

■

If none of the three alarm bytes is “don’t care,” the
frequency is once per day, when hours, minutes, and
seconds match.

■ If only the hour alarm byte is “don’t care,” the frequency

is once per hour, when minutes and seconds match.

■

If only the hour and minute alarm bytes are “don’t care,”
the frequency is once per minute, when seconds match.

■

If the hour, minute, and second alarm bytes are
“don’t care,” the frequency is once per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set
toa1attheendofanupdate cycle. If the update inter­rupt enable bit (UIE) of register B is 1, and the update
transfer inhibit bit (UTI) in register B is 0, then an in­terrupt request is generated at the end of each update
cycle.

Accessing RTC bytes

Time and calendar bytes read during an update cycle
may be in error. Three methods to access the time and
calendar bytes without ambiguity are:

■

Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).

■

Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of t

BUC

time to access the clock bytes (see Figure 3).

■

Use the periodic interrupt event to generate
interrupt requests every tPItime, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler will have a minimum of tPI/2 +
t

BUC

time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq4285 and VCCis
above V

PFD

, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on
but keeps the frequency divider disabled. Any other
pattern to these bits keeps the oscillator off.

7

Figure 3. Update-Ended/Periodic Interrupt Relationship

Jan.1999 D

bq4285

Power-Down/Power-Up Cycle

The bq4285 continuously monitors VCCfor out-of­tolerance. During a power failure, when VCCfalls below
V

PFD

(4.17V typical), the bq4285 write-protects the clock
and storage registers. When VCCis below VBC(3V typi­cal), the power source is switched to BC. RTC operation
and storage data are sustained by a valid backup energy
source. When VCCis above VBC, the power source is
VCC. Write-protection continues for t

CSR

time after V

CC

rises above V

PFD

.

An external CMOS static RAM is battery-backed using
the V

OUT

and chip enable output pins from the bq4285.
As the voltage input VCCslows down during a power
failure, the chip enable output, CE

OUT,

is forced inactive

independent of the chip enable input CE

IN.

This activity unconditionally write-protects the external
SRAM as VCCfalls below V

PFD

. If a memory access is in
process to the external SRAM during power-fail detec­tion, that memory cycle continues to completion before
the memory is write-protected. If the memory cycle is
not terminated within time t

WPT

(30µs maximum), the
chip enable output is unconditionally driven high,
write-protecting the controlled SRAM.

As the supply continues to fall past V

PFD

, an internal

switching device forces V

OUT

to the external backup en-

ergy source. CE

OUT

is held high by the V

OUT

energy

source.

During power-up, V

OUT

is switched back to the 5V sup­ply as VCCrises above the backup cell input voltage
sourcing V

OUT

.CE

OUT

is held inactive for time t

CER

(200ms maximum) after the power supply has reached
V

PFD

, independent of the CEINinput, to allow for proces-

sor stabilization.

During power-valid operation, the CE

IN

input is passed

through to the CE

OUT

output with a propagation delay

of less than 10ns.

Figure 4 shows the hardware hookup for the external
RAM.

A primary backup energy source input is provided on
the bq4285. The BC input accepts a 3V primary battery,
typically some type of lithium chemistry. To prevent
battery drain when there is no valid data to retain,
V

OUT

and CE

OUT

are internally isolated from BC by the
initial connection of a battery. Following the first appli­cation of VCCabove V

PFD

, this isolation is broken, and

the backup cell provides power to V

OUT

and CE

OUT

for

the external SRAM.

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Jan.1999 D

Figure 4. External RAM Hookup to the bq4285 RTC

bq4285