Texas Instruments BQ3285S-SB2, BQ3285Q, BQ3285P-SB2 Datasheet

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Features

➤ Direct clock/calendar replace-

ment for IBM

AT-compatible

computers and other applications

➤ Functionally compatible with the

DS1285

Closely matches MC146818A pin configuration

➤ 114 bytes of general nonvolatile

storage

➤ 160ns cycle time allows fast bus

operation

➤ Selectable Intel or Motorola bus

timing

➤ Less than 0.5

A load under bat-

tery operation

➤ 14 bytes for clock/calendar and

control

➤ BCD or binary format for clock

and calendar data

➤ Calendar in day of the week, day

of the month, months, and years, with automatic leap-year adjustment

➤ Time of day in seconds, minutes,

and hours

12- or 24-hour format

Optional daylight saving adjustment

➤ Programmable square wave out-

put

➤ Three individually maskable in-

terrupt event flags:

Periodic rates from 122µs to 500ms

Time-of-day alarm once per second to once per day

- End-of-clock update cycle

➤ 24-pin plastic DIP or SOIC

General Description

The CMOS bq3285 is a low-power microprocessor peripheral providing a time-of-day clock and 100-year calendar with alarm features and battery operation. Other features include three maskable interrupt sources, square wave output, and 114 bytes of general nonvolatile storage.

The bq3285 write-protects the clock, calendar, and storage registers during power failure. A backup battery then maintains data and operates the clock and calendar.

The bq3285 is a fully compatible real-time clock for IBM AT compatible computers and other applications. The only external components are a 32.768kHz crystal and a backup battery

bq3285

Real-Time Clock (RTC)

PN328501.eps

28-Pin PLCC

5 6

7 8 9 10 11

25 24

23 22 21 20 19

432

282726

12131415161718

SSCSAS

RCL BC

INT RST DS V

R/W

X2X1MOTNCVCCSQW

Pin Names

AD0–AD7Multiplexed address/data

input/output MOT Bus type select input CS Chip select input AS Address strobe input DS Data strobe input R/W Read/write input INT Interrupt request

output RST Reset input SQW Square wave output RCL RAM clear input BC 3V backup cell input X1–X2 Crystal inputs NC No connect V

+5V supply V

Ground

PN328501.eps

24-Pin DIP or SOIC

2 3

4 5 6 7 8

24 23

22 21 20

19 18

17 9 10

15 11 12

CC SQW NC

BC INT RST DS V

SS R/W

AS CS

MOT

X1 X2

RCL

Pin Connections

Jan.1999 E

Block Diagram

Pin Descriptions

MOT Bus type select input

MOT selects bus timing for either Motorola or Intel architecture. This pin should be tied to VCCfor Motorola timing or to VSSfor Intel timing (see Table 1). The setting should not be changed during system operation. MOT is internally pulled low by a 30KΩ resistor.

–AD7Multiplexed address/data input/

output

The bq3285 bus cycle consists of two phases: the address phase and the datatransfer phase. The address phase precedes the data-transfer phase. During the address phase, an address placed on AD

–AD7is latched into the bq3285 on the falling edge of the AS signal. During the data-transfer phase of the bus cycle, the AD0–AD7pins serve as a bidirectional data bus.

AS Address strobe input

AS serves to demultiplex the address/data bus. The falling edge of AS latches the address on AD

–AD7. This demultiplexing process is independent of the CS signal. For DIP, SOIC, and PLCC packages with MOT = VCC, the AS input is provided a signal similar to ALE in an Intel-based system.

Jan.1999 E

Bus

Type

MOT

LevelDSEquivalent

R/W

EquivalentASEquivalent

Motorola

DS,E,or

R/W

Intel

RD, MEMR,or I/OR

WR, MEMW,or I/OW

ALE

Table 1. Bus Setup

bq3285

DS Data strobe input

When MOT = VCC, DS controls data transfer during a bq3285 bus cycle. During a read cycle, the bq3285 drives the bus after the rising edge on DS. During a write cycle, the falling edge on DS is used to latch write data into the chip.

When MOT = VSS, the DS input is provided a signal similar to RD, MEMR, or I/OR in an Intel-based system. The falling edge on DS is used to enable the outputs during a read cycle.

R/W

Read/write input

When MOT = V

, the level on R/W identifies the direction of data transfer. A high level on R/W indicates a read bus cycle, whereas a low on this pin indicates a write bus cycle.

When MOT = VSS, R/W is provided a signal similar to WR, MEMW, or I/OW in an Intelbased system. The rising edge on R/W latches data into the bq3285.

Chip select input

CS should be driven low and held stable during the data-transfer phase of a bus cycle accessing the bq3285.

INT

Interrupt request output

INT is an open-drain output. INT is asserted low when any event flag is set and the corresponding event enable bit is also set. INT becomes high-impedance whenever register C is read (see the Control/Status Registers section).

SQW Square-wave output

SQW may output a programmable frequency square-wave signal during normal (V

valid) system operation. Any one of the 13 specific frequencies may be selected through register A. This pin is held low when the square-wave enable bit (SQWE) in register B is 0 (see the Control/Status Registers section).

RCL

RAM clear input

A low level on the RCL pin causes the contents of each of the 114 storage bytes to be set to FF(hex). The contents of the clock and control registers are unaffected. This pin should be used as a user-interface input (pushbutton to ground) and not connected to the output of any active component. RCL input is only recognized when held low for at least 125ms in the presence of VCCwhen the oscillator is running. Using RAM clear does not affect the battery load. This pin is connected internally to a 30KΩpull-up resistor.

BC 3V backup cell input

BC should be connected to a 3V backup cell for RTC operation and storage register nonvolatility in the absence of power. When V

slews down past VBC(3V typical), the integral control circuitry switches the power source to BC. When VCCreturns above VBC, the power source is switched to VCC.

Upon power-up, a voltage within the V

range must be present on the BC pin for the oscillator to start up.

RST

Reset input

The bq3285 is reset when RST is pulled low. When reset, INT becomes high-impedance, and the bq3285 is not accessible. Table 4 in the Control/Status Registers section lists the register bits that are cleared by a reset.

Reset may be disabled by connecting RST to VCC. This allows the control bits to retain their states through powerdown/power-up cycles.

X1–X2 Crystal inputs

The X1–X2 inputs are provided for an external 32.768Khz quartz crystal, Daiwa DT-26 or equivalent, with 6pF load capacitance. A trimming capacitor may be necessary for extremely precise time-base generation.

In the absence of a crystal, an oscillated output of 32.768kHz can be fed into the X1 input.

Jan.1999 E

bq3285

Functional Description

Address Map

The bq3285 provides 14 bytes of clock and control/status registers and 114 bytes of general nonvolatile storage. Figure 1 illustrates the address map for the bq3285.

Update Period

The update period for the bq3285 is one second. The bq3285 updates the contents of the clock and calendar locations during the update cycle at the end of each up-

date period (see Figure 2). The alarm flag bit may also be set during the update cycle.

The bq3285 copies the local register updates into the user buffer accessed by the host processor. Whena1is written to the update transfer inhibit bit (UTI) in register B, the user copy of the clock and calendar bytes remains unchanged, while the local copy of the same bytes continues to be updated every second.

The update-in-progress bit (UIP) in register A is set t

BUC

time before the beginning of an update cycle (see Figure 2). This bit is cleared and the update-complete flag (UF) is set at the end of the update cycle.

Clock and

Control Status

Registers

Storage

Registers

Bytes

114

Bytes

00 00

01 02 03 04

05 06 07 08 09 0A

0B 0C 0D

1 2 3 4

5 6 7 8

9 10 11

12 13

13 14

127 7F

BCD or

Binary

Format

Seconds

Seconds Alarm

Minutes

Minutes Alarm

Hours

Month

Year Register A Register B Register C Register D

Hours Alarm Day of Week

Day of Month

Figure 1. Address Map

Update Period

(1s)

BUC

tUC (Update Cycle)

UIP

Figure 2. Update Period Timing and UIP

Jan.1999 E

bq3285

Programming the RTC

The time-of-day, alarm, and calendar bytes can be written in either the BCD or binary format (see Table 2).

These steps may be followed to program the time, alarm, and calendar:

1. Modify the contents of register B:

a. Write a 1 to the UTI bit to prevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to the data

format (DF) bit to select BCD or binary format for all time, alarm, and calendar bytes.

c. Write the appropriate value to the hour

format (HF) bit.

2. Write new values to all the time, alarm, and calendar locations.

3. Clear the UTI bit to allow update transfers.

On the next update cycle, the RTC updates all 10 bytes in the selected format.

Address RTC Bytes

Range

Decimal Binary Binary-Coded Decimal

0 Seconds 0–59 00H–3BH 00H–59H

1 Seconds alarm 0–59 00H–3BH 00H–59H

2 Minutes 0–59 00H–3BH 00H–59H

3 Minutes alarm 0–59 00H–3BH 00H–59H

Hours, 12-hour format

1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours, 24-hour format 0–23 00H–17H 00H–23H

Hours alarm, 12-hour format

1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours alarm, 24-hour format 0–23 00H–17H 00H–23H

6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H

7 Day of month 1–31 01H–1FH 01H–31H

8 Month 1–12 01H–0CH 01H–12H

9 Year 0–99 00H–63H 00H–99H

Table 2. Time, Alarm,and Calendar Formats

Jan.1999 E

bq3285

Square-Wave Output

The bq3285 divides the 32.768kHz oscillator frequency to produce the 1Hz update frequency for the clock and calendar. Thirteen taps from the frequency divider are fed to a 16:1 multiplexer circuit. The output of this mux is fed to the SQW output and periodic interrupt generation circuitry. The four least-significant bits of register A, RS0–RS3, select among the 13 taps (see Table 3). The square-wave output is enabled by writinga1tothe square-wave enable bit (SQWE) in register B.

Interrupts

The bq3285 allows three individually selected interrupt events to generate an interrupt request. These three interrupt events are:

The periodic interrupt, programmable to occur once every 122µs to 500ms

The alarm interrupt, programmable to occur once per second to once per day

The update-ended interrupt, which occurs at the end of each update cycle

Each of the three interrupt events is enabled by an individual interrupt-enable bit in register B. When an event occurs, its event flag bit in register C is set. If the corresponding event enable bit is also set, then an interrupt request is generated. The interrupt request flag bit (INTF) of register C is set with every interrupt request. Reading register C clears all flag bits, including INTF, and makes INT

high-impedance.

Two methods can be used to process bq3285 interrupt events:

Enable interrupt events and use the interrupt request output to invoke an interrupt service routine.

Do not enable the interrupts and use a polling routine to periodically check the status of the flag bits.

The individual interrupt sources are described in detail in the following sections.

RS3 RS2 RS1 RS0 Frequency Units Period Units

0000None None

0001256 Hz3.90625 ms

0010128 Hz7.8125 ms

00118.192 kHz 122.070

01004.096 kHz 244.141

01012.048 kHz 488.281

01101.024 kHz 976.5625

0111512 Hz1.95315 ms

1000256 Hz3.90625 ms

1001128 Hz7.8125 ms

101064 Hz15.625 ms

101132 Hz31.25 ms

110016 Hz62.5 ms

11018 Hz125 ms

11104 Hz250 ms

11112 Hz500 ms

Table 3. Square-Wave Frequency/Periodic Interrupt Rate

Jan.1999 E

bq3285

PeriodicInterrupt

The mux output used to drive the SQW output also drives the interrupt-generation circuitry. If the periodic interrupt event is enabled by writinga1totheperiodic interrupt enable bit (PIE) in register C, an interrupt request is generated once every 122µs to 500ms. The period between interrupts is selected by the same bits in register A that select the square wave frequency (see Table 3).

Alarm Interrupt

During each update cycle, the RTC compares the hours, minutes, and seconds bytes with the three corresponding alarm bytes. If a match of all bytes is found, the alarm interrupt event flag bit, AF in register C, is set to 1. If the alarm event is enabled, an interrupt request is generated.

An alarm byte may be removed from the comparison by setting it to a “don’t care” state. An alarm byte is set to a “don’t care” state by writinga1toeachofitstwo most-significant bits. A “don’t care” state may be used to select the frequency of alarm interrupt events as follows:

If none of the three alarm bytes is “don’t care,” the frequency is once per day, when hours, minutes, and seconds match.

n If only the hour alarm byte is “don’t care,” the

frequency is once per hour, when minutes and seconds match.

If only the hour and minute alarm bytes are “don’t care,” the frequency is once per minute, when seconds match.

If the hour, minute, and second alarm bytes are “don’t care,” the frequency is once per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set toa1attheendofanupdate cycle. If the update interrupt enable bit (UIE) of register B is 1, and the update transfer inhibit bit (UTI) in register B is 0, then an interrupt request is generated at the end of each update cycle.

Accessing RTC bytes

Time and calendar bytes read during an update cycle may be in error. Three methods to access the time and calendar bytes without ambiguity are:

Enable the update interrupt event to generate interrupt requests at the end of the update cycle. The interrupt handler has a maximum of 999ms to access the clock bytes before the next update cycle begins (see Figure 3).

Poll the update-in-progress bit (UIP) in register A. If UIP = 0, the polling routine has a minimum of t

BUC

time to access the clock bytes (see Figure 3).

Use the periodic interrupt event to generate interrupt requests every tPItime, such that UIP = 1 always occurs between the periodic interrupts. The interrupt handler has a minimum of tPI/2+t

BUC

time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq3285 and VCCis above V

PFD

, the internal oscillator and frequency divider are turned on by writing a 010 pattern to bits 4 through 6 of register A. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. Any other pattern to these bits keeps the oscillator off.

Jan.1999 E

Figure 3. Update-Ended/Periodic Interrupt Relationship

bq3285

Power-Down/Power-Up Cycle

The bq3285 continuously monitors VCCfor out-oftolerance. During a power failure, when VCCfalls below V

PFD

(4.17V typical), the bq3285 write-protects the clock and storage registers. When VCCis below VBC(3V typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup energy source. When VCCis above VBC, the power source is VCC. Write-protection continues for t

CSR

time after VCCrises

above V

PFD

Control/Status Registers

The four control/status registers of the bq3285 are accessible regardless of the status of the update cycle (see Table 4).

The frequency of the square-wave and the periodic event rate.

n Oscillator operation.

Status of the update cycle.

RS0–RS3 - Frequency Select

These bits select one of the 13 frequencies for the SQW output and the periodic interrupt rate,as shown in Table 3.

OS0–OS2 - OscillatorControl

These three bits control the state of the oscillator and divider stages. A pattern of 010 enables RTC operation by turning on the oscillator and enabling the frequency divider. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When 010 is written, the RTC begins its first update after 500ms.

UIP - UpdateCycleStatus

This read-only bit is set prior to the update cycle. When UIP equals 1, an RTC update cycle may be in progress. UIP is cleared at the end of each update cycle. This bit is also cleared when the update transfer inhibit (UTI) bit in register B is 1.

Reg.

Loc.

(Hex) Read Write

Bit Name and State on Reset

7 (MSB) 6 5 4 3 2 1 0 (LSB)

A 0A Yes Yes

UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na

B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 SQWE 0 DF na HF na DSE na

C 0C Yes No INTF 0 PF 0 AF 0 UF 0 - 0-0-0 -0

D 0DYesNoVRTna-0-0-0 - 0-0-0 -0

Notes: 1. Except bit 7.

2. na = not affected

Table 4. Control/Status Registers

7654 3 210

UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0

76543210

----RS3RS2RS1RS0

76543210

-OS2OS1OS0----

76543210

UIP-------

Jan.1999 E

bq3285

Update cycle transfer operation

Square-wave output

Interrupt events

Daylight saving adjustment

Clock and calendar data formats

All bits of register B are read/write.

DSE - Daylight Saving Enable

This bit enables daylight-saving time adjustments when written to 1:

n On the last Sunday in October, the first time the

bq3285 increments past 1:59:59 AM, the time falls back to 1:00:00 AM.

On the first Sunday in April, the time springs forward from 2:00:00 AM to 3:00:00 AM.

HF - HourFormat

This bit selects the time-of-day and alarm hour format:

1 = 24-hour format

0 = 12-hour format

DF - DataFormat

This bit selects the numeric format in which the time, alarm, and calendar bytes are represented:

1 = Binary

0 = BCD

SQWE - Square-Wave Enable

This bit enables the square-wave output:

1 = Enabled

0 = Disabled and held low

UIE - UpdateCycleInterrupt Enable

This bit enables an interrupt request due to an update ended interrupt event:

1 = Enabled

0 = Disabled

The UIE bit is automatically cleared when the UTI bit equals 1.

AIE - AlarmInterruptEnable

This bit enables an interrupt request due to an alarm

interrupt event:

1 = Enabled

0 = Disabled

PIE - Periodic Interrupt Enable

This bit enables an interrupt request due to a periodic

interrupt event:

1 = Enabled

0 = Disabled

7654 3 210

---- - --DSE

7654 3 210

---- -DF--

7654 3 210

---UIE- ---

7654 3 210

UTI PIE AIE UIE SQWE DF HF DSE

7654 3 210

--AIE- - ---

7654 3 210

-PIE-- - ---

7654 3 210

---- - -HF-

7654 3 210

----SQWE - - -

Jan.1999 E

bq3285

UTI - UpdateTransfer Inhibit

This bit inhibits the transfer of RTC bytes to the user buffer:

1 = Inhibits transfer and clears UIE

0 = Allows transfer

Bits 0–3 -UnusedBits

These bits are always set to 0.

UF - UpdateEventFlag

This bit is set toa1attheendoftheupdate cycle. Reading register C clears this bit.

AF - AlarmEventFlag

This bit is set to a 1 when an alarm event occurs. Reading register C clears this bit.

PF - Periodic Event Flag

This bit is set to a 1 every t

time, where tPIis the time period selected by the settings of RS0–RS3 in register A. Reading register C clears this bit.

INTF - InterruptRequestFlag

This flag is set to a 1 when any of the following is true:

AIE = 1 and AF = 1

PIE = 1 and PF = 1

UIE = 1 and UF = 1

Reading register C clears this bit.

Bits 0–6 -UnusedBits

These bits are always set to 0.

VRT - Valid RAM andTime

1 = Valid backup energy source

0 = Backup energy source is depleted

When the backup energy source is depleted (VRT = 0), data integrity of the RTC and storage registers is not guaranteed.

7654 3 210

UTI--- - ---

7654 3 210

---- 0000

7654 3 210

---UF- ---

7654 3 210

--AF- - ---

7654 3 210

-PF- - - - - -

7654 3 210

INTF - - - - - - -

7654 3 210

INTF PF AF UF 0 0 0 0

7654 3 210

-000 0 000

7654 3 210

VRT000 0 000

7654 3 210

VRT - - - - - - -

Jan.1999 E

bq3285

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

DC voltage applied on VCCrelative to V

-0.3 to 7.0 V

DC voltage applied on any pin excluding V

relative to V

-0.3 to 7.0 V

≤

+ 0.3

OPR

Operating temperature 0 to +70 °C Commercial

STG

Storage temperature -55 to +125 °C

BIAS

Temperature under bias -40 to +85 °C

SOLDER

Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (T

= T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit

Supply voltage 4.5 5.0 5.5 V

Supply voltage 0 0 0 V

Input low voltage -0.3 - 0.8 V

Input high voltage 2.2 - VCC+ 0.3 V

Backup cell voltage 2.5 - 4.0 V

Note: Typical values indicate operation at TA= 25°C.

Jan.1999 E

bq3285

DC Electrical Characteristics (T

= T

OPR

, VCC= 5V±10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

Input leakage current - -

AVIN= VSSto V

Output leakage current - -

–AD7, INT, and SQW in high impedance, V

OUT

= VSSto V

Output high voltage 2.4 - - V IOH= -2.0 mA

Output low voltage - - 0.4 V IOL= 4.0 mA

Operating supply current

- 7 15 mA

Min. cycle, duty = 100%, I

= 0mA, IOL= 0mA

Supply switch-over voltage - V

-V

CCB

Battery operation current - 0.3 0.5

AVBC= 3V, TA= 25°C

PFD

Power-fail-detect voltage 4.0 4.17 4.35 V

RCL

Input current when RCL = VSS. - - 185

A Internal 30K pull-up

MOTH

Input current when MOT = V

- - -185

A Internal 30K pull-down

Notes: Typical values indicate operation at TA= 25°C, VCC= 5V or VBC= 3V.

Crystal Specifications (DT-26 or Equivalent)

Symbol Parameter Minimum Typical Maximum Unit

Oscillation frequency - 32.768 - kHz

Load capacitance - 6 - pF

Temperature turnover point 20 25 30 °C

k Parabolic curvature constant - - -0.042 ppm/°C

Q Quality factor 40,000 70,000 -

Series resistance - - 45 K

Ω

Shunt capacitance - 1.1 1.8 pF

0/C1

Capacitance ratio - 430 600

Drive level - - 1

∆

f/f

Aging (first year at 25°C) - 1 - ppm

Jan.1999 E

bq3285

Capacitance (T

= 25°C, F = 1MHz, VCC= 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

I/O

Input/output capacitance - - 7 pF V

OUT

= 0V

Input capacitance - - 5 pF VIN= 0V

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0 to 3.0 V

Input rise and fall times 5 ns

Input and output timing reference levels 1.5 V (unless otherwise specified)

Output load (including scope and jig) See Figures 4 and 5

Figure 4. Output Load A Figure 5. Output Load B

Jan.1999 E

bq3285

Read/Write Timing (T

= T

OPR

, VCC= 5V±10%)

Symbol Parameter Minimum Typical Maximum Unit Notes

CYC

Cycle time 160 - - ns

DSL

DS low or RD/WR high time 80 - - ns

DSH

DS high or RD/WR low time 55 - - ns

RWH

R/W hold time 0 - - ns

RWS

R/W setup time 10 - - ns

Chip select setup time 5 - - ns

Chip select hold time 0 - - ns

DHR

Read data hold time 0 - 25 ns

DHW

Write data hold time 0 - - ns

Address setup time 20 - - ns

Address hold time 5 - - ns

DAS

Delay time, DS to AS rise 10 - - ns

ASW

Pulse width, AS high 30 - - ns

ASD

Delay time, AS to DS rise (RD/WR fall)

35 - - ns

Output data delay time from DS rise (RD fall)

- - 50 ns

Write data setup time 30 - - ns

BUC

Delay time before update cycle - 244 -

Periodic interrupt time interval ----See Table 3

Time of update cycle - 1 -

Jan.1999 E

bq3285

Motorola Bus Read/Write Timing

Jan.1999 E

bq3285

Intel Bus Write Timing

Intel Bus Read Timing

Jan.1999 E

bq3285

Power-Down/Power-Up Timing (T

= T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Conditions

VCCslew from 4.5V to 0V 300 - -

VCCslew from 0V to 4.5V 100 - -

CSR

CS at VIHafter power-up

20 - 200 ms

Internal write-protection period after V

passes V

PFD

on power-up.

Power-Down/Power-Up Timing

Jan.1999 E

bq3285

Interrupt Delay Timing

Jan.1999 E

bq3285

Interrupt Delay Timing (T

= T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit

RSW

Reset pulse width 5 - -

IRR

INT release from RST --2

IRD

INT release from DS (RD)--2

bq3285

Jan.1999 E

24-Pin DIP (P)

Dimension Minimum Maximum

A 0.160 0.190

A1 0.015 0.040

B 0.015 0.022

B1 0.045 0.065

C 0.008 0.013 D 1.240 1.280 E 0.600 0.625

E1 0.530 0.570

e 0.600 0.670 G 0.090 0.110 L 0.115 0.150

S 0.070 0.090

All dimensions are in inches.

24-Pin DIP (P)

24-Pin SOIC (S)

Dimension Minimum Maximum

A 0.095 0.105

A1 0.004 0.012

B 0.013 0.020 C 0.008 0.013 D 0.600 0.615 E 0.290 0.305

e 0.045 0.055 H 0.395 0.415 L 0.020 0.040

All dimensions are in inches.

24-Pin SOIC (S)

Jan.1999 E

bq3285

28-Pin Quad PLCC (Q)

Dimension Minimum Maximum

A 0.165 0.180

A1 0.020 -

B 0.012 0.021

B1 0.025 0.033

C 0.008 0.012

D 0.485 0.495 D1 0.445 0.455 D2 0.390 0.430

E 0.485 0.495

E1 0.445 0.455 E2 0.390 0.430

e 0.045 0.055

All dimensions are in inches.

28-Pin Quad PLCC (Q)

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 2 Address strobe input Clarification

1 11 Backup cell voltage V

Was 2.0 min; is 2.5 min

112

Power-fail detect voltage V

PFD

Was 4.1 min, 4.25 max; is 4.0 min, 4.35 max

2 3, 12 Crystal type Daiwa DT-26 (not DT-26S) Clarification

3 12 Changed value in first table I

RCL

max. was 275; is now 185

3 12 Changed value in first table

MOTH

max. was -275; is now

-185

3 12 Changed values for conditions of I

RCL,IMOTH

Was 20K; is now 30K

4 1, 8, 20 PLCC last time buy and Reg A update Reg A labeling corrected

Notes: Change 1 = Nov. 1992 B changes from June 1991 A.

Change 2 = Nov. 1993 C changes from Nov. 1992 B. Change 3 = Sept. 1996 D changes from Nov. 1993 C Change 4 = Jan. 1999 E changes from Sept. 1996 D

Jan.1999 E

bq3285

Ordering Information

bq3285 -

Package Option:

P = 24-pin plastic DIP (0.600) S = 24-pin SOIC (0.300) Q = 28-pin quad PLCC—Last time buy

Device:

bq3285 Real-Time Clock with 114 bytes of

general storage

Temperature:

blank = Commercial (0 to +70°C)

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Texas Instruments BQ3285S-SB2, BQ3285Q, BQ3285P-SB2 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual