Texas Instruments BQ3285S-SB2, BQ3285Q, BQ3285P-SB2 Datasheet

Features

➤ Direct clock/calendar replace-

ment for IBM

®

AT-compatible

computers and other applications

➤ Functionally compatible with the

DS1285

-

Closely matches MC146818A
pin configuration

➤ 114 bytes of general nonvolatile

storage

➤ 160ns cycle time allows fast bus

operation

➤ Selectable Intel or Motorola bus

timing

➤ Less than 0.5

µ

A load under bat-

tery operation

➤ 14 bytes for clock/calendar and

control

➤ BCD or binary format for clock

and calendar data

➤ Calendar in day of the week, day

of the month, months, and years,
with automatic leap-year adjust­ment

➤ Time of day in seconds, minutes,

and hours

-

12- or 24-hour format

-

Optional daylight saving
adjustment

➤ Programmable square wave out-

put

➤ Three individually maskable in-

terrupt event flags:

-

Periodic rates from 122µs to
500ms

-

Time-of-day alarm once per
second to once per day

- End-of-clock update cycle

➤ 24-pin plastic DIP or SOIC

General Description

The CMOS bq3285 is a low-power
microprocessor peripheral providing
a time-of-day clock and 100-year cal­endar with alarm features and bat­tery operation. Other features in­clude three maskable interrupt
sources, square wave output, and 114
bytes of general nonvolatile storage.

The bq3285 write-protects the clock,
calendar, and storage registers during
power failure. A backup battery
then maintains data and operates the
clock and calendar.

The bq3285 is a fully compatible
real-time clock for IBM AT com­patible computers and other appli­cations. The only external compo­nents are a 32.768kHz crystal and
a backup battery

1

bq3285

Real-Time Clock (RTC)

PN328501.eps

28-Pin PLCC

5
6

7
8
9
10
11

25
24

23
22
21
20
19

432

1

282726

12131415161718

AD

0

AD

1

AD

2

AD

3

AD

4

AD

5

NC

AD

6

NC

AD

7

V

SSCSAS

NC

RCL
BC

INT
RST
DS
V

SS

R/W

X2X1MOTNCVCCSQW

NC

Pin Names

AD0–AD7Multiplexed address/data

input/output
MOT Bus type select input
CS Chip select input
AS Address strobe input
DS Data strobe input
R/W Read/write input
INT Interrupt request

output
RST Reset input
SQW Square wave output
RCL RAM clear input
BC 3V backup cell input
X1–X2 Crystal inputs
NC No connect
V

CC

+5V supply
V

SS

Ground

1

PN328501.eps

24-Pin DIP or SOIC

2
3

4
5
6
7
8

24
23

22
21
20

19
18

17
9
10

16

15
11
12

14

13

V

CC
SQW
NC

BC
INT
RST
DS
V

SS
R/W

AS
CS

MOT

X1
X2

AD

0

AD

1

AD

2

AD

3

AD

4

AD

5

AD

6

AD

7

V

SS

RCL

Pin Connections

Jan.1999 E

Block Diagram

Pin Descriptions

MOT Bus type select input

MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCCfor Motorola timing or to VSSfor
Intel timing (see Table 1). The setting
should not be changed during system opera­tion. MOT is internally pulled low by a
30KΩ resistor.

AD

0

–AD7Multiplexed address/data input/

output

The bq3285 bus cycle consists of two
phases: the address phase and the data­transfer phase. The address phase pre­cedes the data-transfer phase. During the
address phase, an address placed on
AD

0

–AD7is latched into the bq3285 on the
falling edge of the AS signal. During the
data-transfer phase of the bus cycle, the
AD0–AD7pins serve as a bidirectional data
bus.

AS Address strobe input

AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad­dress on AD

0

–AD7. This demultiplexing pro­cess is independent of the CS signal. For
DIP, SOIC, and PLCC packages with MOT =
VCC, the AS input is provided a signal simi­lar to ALE in an Intel-based system.

2

Jan.1999 E

Bus

Type

MOT

LevelDSEquivalent

R/W

EquivalentASEquivalent

Motorola

V

CC

DS,E,or

Φ

2

R/W

AS

Intel

V

SS

RD,
MEMR,or
I/OR

WR,
MEMW,or
I/OW

ALE

Table 1. Bus Setup

bq3285

DS Data strobe input

When MOT = VCC, DS controls data trans­fer during a bq3285 bus cycle. During a
read cycle, the bq3285 drives the bus after
the rising edge on DS. During a write cycle,
the falling edge on DS is used to latch write
data into the chip.

When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.

R/W

Read/write input

When MOT = V

CC

, the level on R/W identi­fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.

When MOT = VSS, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel­based system. The rising edge on R/W
latches data into the bq3285.

CS

Chip select input

CS should be driven low and held stable
during the data-transfer phase of a bus cy­cle accessing the bq3285.

INT

Interrupt request output

INT is an open-drain output. INT is as­serted low when any event flag is set and
the corresponding event enable bit is also
set. INT becomes high-impedance whenever
register C is read (see the Control/Status
Registers section).

SQW Square-wave output

SQW may output a programmable fre­quency square-wave signal during normal
(V

CC

valid) system operation. Any one of
the 13 specific frequencies may be selected
through register A. This pin is held low
when the square-wave enable bit (SQWE)
in register B is 0 (see the Control/Status
Registers section).

RCL

RAM clear input

A low level on the RCL pin causes the con­tents of each of the 114 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCCwhen
the oscillator is running. Using RAM clear
does not affect the battery load. This pin is
connected internally to a 30KΩpull-up re­sistor.

BC 3V backup cell input

BC should be connected to a 3V backup cell
for RTC operation and storage register non­volatility in the absence of power. When
V

CC

slews down past VBC(3V typical), the
integral control circuitry switches the
power source to BC. When VCCreturns
above VBC, the power source is switched to
VCC.

Upon power-up, a voltage within the V

BC

range must be present on the BC pin for
the oscillator to start up.

RST

Reset input

The bq3285 is reset when RST is pulled low.
When reset, INT becomes high-impedance,
and the bq3285 is not accessible. Table 4 in
the Control/Status Registers section lists
the register bits that are cleared by a reset.

Reset may be disabled by connecting RST
to VCC. This allows the control bits to re­tain their states through power­down/power-up cycles.

X1–X2 Crystal inputs

The X1–X2 inputs are provided for an ex­ternal 32.768Khz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci­tance. A trimming capacitor may be neces­sary for extremely precise time-base gen­eration.

In the absence of a crystal, an oscillated
output of 32.768kHz can be fed into the X1
input.

3

Jan.1999 E

bq3285

Functional Description

Address Map

The bq3285 provides 14 bytes of clock and control/status
registers and 114 bytes of general nonvolatile storage.
Figure 1 illustrates the address map for the bq3285.

Update Period

The update period for the bq3285 is one second. The
bq3285 updates the contents of the clock and calendar
locations during the update cycle at the end of each up-

date period (see Figure 2). The alarm flag bit may also
be set during the update cycle.

The bq3285 copies the local register updates into the
user buffer accessed by the host processor. Whena1is
written to the update transfer inhibit bit (UTI) in regis­ter B, the user copy of the clock and calendar bytes re­mains unchanged, while the local copy of the same bytes
continues to be updated every second.

The update-in-progress bit (UIP) in register A is set
t

BUC

time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.

4

Clock and

Control Status

Registers

Storage

Registers

14

Bytes

114

Bytes

00 00

01
02
03
04

05
06
07
08
09
0A

0B
0C
0D

00

1
2
3
4

5
6
7
8

9
10
11

12
13

13
14

127 7F

0E

0D

BCD or

Binary

Format

Seconds

Seconds Alarm

Minutes

Minutes Alarm

Hours

Month

Year
Register A
Register B
Register C
Register D

Hours Alarm
Day of Week

Day of Month

Figure 1. Address Map

Update Period

(1s)

t

BUC

tUC (Update Cycle)

UIP

Figure 2. Update Period Timing and UIP

Jan.1999 E

bq3285

Programming the RTC

The time-of-day, alarm, and calendar bytes can be writ­ten in either the BCD or binary format (see Table 2).

These steps may be followed to program the time, alarm,
and calendar:

1. Modify the contents of register B:

a. Write a 1 to the UTI bit to prevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to the data

format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.

c. Write the appropriate value to the hour

format (HF) bit.

2. Write new values to all the time, alarm, and
calendar locations.

3. Clear the UTI bit to allow update transfers.

On the next update cycle, the RTC updates all 10 bytes
in the selected format.

5

Address RTC Bytes

Range

Decimal Binary Binary-Coded Decimal

0 Seconds 0–59 00H–3BH 00H–59H

1 Seconds alarm 0–59 00H–3BH 00H–59H

2 Minutes 0–59 00H–3BH 00H–59H

3 Minutes alarm 0–59 00H–3BH 00H–59H

4

Hours, 12-hour format

1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours, 24-hour format 0–23 00H–17H 00H–23H

5

Hours alarm, 12-hour format

1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours alarm, 24-hour format 0–23 00H–17H 00H–23H

6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H

7 Day of month 1–31 01H–1FH 01H–31H

8 Month 1–12 01H–0CH 01H–12H

9 Year 0–99 00H–63H 00H–99H

Table 2. Time, Alarm,and Calendar Formats

Jan.1999 E

bq3285

Square-Wave Output

The bq3285 divides the 32.768kHz oscillator frequency
to produce the 1Hz update frequency for the clock and
calendar. Thirteen taps from the frequency divider are
fed to a 16:1 multiplexer circuit. The output of this mux
is fed to the SQW output and periodic interrupt genera­tion circuitry. The four least-significant bits of register
A, RS0–RS3, select among the 13 taps (see Table 3). The
square-wave output is enabled by writinga1tothe
square-wave enable bit (SQWE) in register B.

Interrupts

The bq3285 allows three individually selected interrupt
events to generate an interrupt request. These three in­terrupt events are:

n

The periodic interrupt, programmable to occur once
every 122µs to 500ms

n

The alarm interrupt, programmable to occur once per
second to once per day

n

The update-ended interrupt, which occurs at the end
of each update cycle

Each of the three interrupt events is enabled by an indi­vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre­sponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT

high-impedance.

Two methods can be used to process bq3285 interrupt
events:

n

Enable interrupt events and use the interrupt request
output to invoke an interrupt service routine.

n

Do not enable the interrupts and use a polling routine
to periodically check the status of the flag bits.

The individual interrupt sources are described in detail
in the following sections.

6

Register A Bits Square Wave Periodic Interrupt

RS3 RS2 RS1 RS0 Frequency Units Period Units

0000None None

0001256 Hz3.90625 ms

0010128 Hz7.8125 ms

00118.192 kHz 122.070

µ

s

01004.096 kHz 244.141

µ

s

01012.048 kHz 488.281

µ

s

01101.024 kHz 976.5625

µ

s

0111512 Hz1.95315 ms

1000256 Hz3.90625 ms

1001128 Hz7.8125 ms

101064 Hz15.625 ms

101132 Hz31.25 ms

110016 Hz62.5 ms

11018 Hz125 ms

11104 Hz250 ms

11112 Hz500 ms

Table 3. Square-Wave Frequency/Periodic Interrupt Rate

Jan.1999 E

bq3285

PeriodicInterrupt

The mux output used to drive the SQW output also
drives the interrupt-generation circuitry. If the periodic
interrupt event is enabled by writinga1totheperiodic
interrupt enable bit (PIE) in register C, an interrupt re­quest is generated once every 122µs to 500ms. The pe­riod between interrupts is selected by the same bits in
register A that select the square wave frequency (see Ta­ble 3).

Alarm Interrupt

During each update cycle, the RTC compares the hours,
minutes, and seconds bytes with the three corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is gen­erated.

An alarm byte may be removed from the comparison by
setting it to a “don’t care” state. An alarm byte is set to
a “don’t care” state by writinga1toeachofitstwo
most-significant bits. A “don’t care” state may be used to
select the frequency of alarm interrupt events as follows:

n

If none of the three alarm bytes is “don’t care,” the
frequency is once per day, when hours, minutes, and
seconds match.

n If only the hour alarm byte is “don’t care,” the

frequency is once per hour, when minutes and
seconds match.

n

If only the hour and minute alarm bytes are “don’t
care,” the frequency is once per minute, when seconds
match.

n

If the hour, minute, and second alarm bytes are
“don’t care,” the frequency is once per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set
toa1attheendofanupdate cycle. If the update inter­rupt enable bit (UIE) of register B is 1, and the update
transfer inhibit bit (UTI) in register B is 0, then an in­terrupt request is generated at the end of each update
cycle.

Accessing RTC bytes

Time and calendar bytes read during an update cycle
may be in error. Three methods to access the time and
calendar bytes without ambiguity are:

n

Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).

n

Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of t

BUC

time to access the clock bytes (see Figure 3).

n

Use the periodic interrupt event to generate
interrupt requests every tPItime, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2+t

BUC

time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq3285 and VCCis
above V

PFD

, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on,
but keeps the frequency divider disabled. Any other pat­tern to these bits keeps the oscillator off.

7

Jan.1999 E

Figure 3. Update-Ended/Periodic Interrupt Relationship

bq3285