Texas Instruments BQ3285EDSSTR, BQ3285EDSS, BQ3285LDSSTR, BQ3285LDSS Datasheet

bq3285ED/LD

Features

➤ ACPI-compliant

day-of-month alarm

➤ Direct clock/calendar replace-

ment for IBM
computers and other applications

➤ 2.7–5.5V operation (bq3285LD);

4.5–5.5V operation (bq3285ED)

➤ 242 bytes of general nonvolatile

storage

➤ Dedicated 32.768kHz output pin
➤ System wake-up capability—

alarm interrupt output active in
battery-backup mode

➤ Less than 0.55µA load under bat-

tery operation

➤ Selectable Intel or Motorola bus

timing

➤ 24-pin plastic SSOP

®

AT-compatible

Real-Time Clock(RTC

General Description

The CMOS bq3285ED/LD is a low­power microprocessor peripheral pro­viding a time-of-day clock and 100­year calendar with alarm features
and battery operation. The architec­ture is based on the bq3285/7 RTC
with added features: low-voltage op­eration, 32.768kHz output, 128 addi­tional bytes of CMOS, and a day-of­month alarm to be compliant with
the ACPIRTC specification.

A 32.768kHz output is available for
sustaining power-management ac­tivities. The bq3285ED/LD 32kHz
output is always on whenever V
valid. In VCCstandby mode, the
32kHz is active, and the bq3285LD
typically draws 100µA while the
bq3285ED typically draws 300µA.
Wake-up capability is provided by
an alarm interrupt, which is active
in battery-backup mode. In battery­backup mode, current drain is less
than 550nA.

CC

The bq3285ED/LD write-protects the
clock, calendar, and storage registers
during power failure. A backup
battery then maintains data and oper­ates the clockand calendar.

The bq3285ED/LD is a fully com­patible real-time clock for IBM AT­compatible computers and other ap­plications. The only external compo­nents are a 32.768kHz crystal and a
backup battery.

The bq3285ED is intended for use in
5V systems. The bq3285LD is in­tended for use in 3V systems; the
bq3285LD, however, may also oper­ate at 5V and then go into a 3V

is

power-down state, write-protecting
as if in a 3V system.

)

Pin Connections Pin Names

AD0–AD7Multiplexed address/

data input/output

MOT

X1

X2
AD
AD
AD
AD
AD
AD
AD
AD

V

SS

July 1997

0
1
2
3
4
5
6
7

1
2

3
4
5
6
7
8
9
10
11
12

24-Pin SSOP

24
23

22
21
20
19
18
17
16
15
14

13

V
32k

EXTRAM
RCL
BC
INT
RST
DS
V
R/W
AS
CS

PN3285ED/LD.eps

CC

SS

MOT Bus type select input

CS Chip select input

AS Address strobe input

DS Data strobe input

R/W Read/write input

INT Interrupt request output

RST Reset input

32K 32.768kHz output

EXTRAM Extended RAM enable

RCL RAM clear input

BC 3V backup cell input

X1–X2 Crystal inputs

V

CC

V

SS

Power supply

Ground

1

bq3285ED/LD

Block Diagram

X

1

X

2

Time­Base

Oscillator

÷ 8 ÷ 64 ÷ 64

RST
MOT

CS

R/W

AS

AD0–AD

DS

RCL

EXTRAM

V

CC
BC

µ

P

Bus

I/F

7

CS

Power-

Fail

Control

V

OUT

Write
Protect

Pin Descriptions

MOT Bus type select input

MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCCfor Motorola timing or to VSSfor
Intel timing (see Table 1). The setting
should not be changed during system opera­tion. MOT is internally pulled low by a 30K

resistor.

Ω

Table 1. Bus Setup

Bus

Type

Motorola V

Intel V

MOT

LevelDSEquivalent

DS,E,or

CC

2

Φ

RD,
MEMR,or

SS

I/OR

EquivalentASEquivalent

R/W

WR,
MEMW,or
I/OW

3

Control/Status

Registers

Clock/Calendar, Alarm

and Control Bytes

User Buffer

(14 Bytes)

Storage Registers

(114 Bytes)

Storage Registers

(128 Bytes)

R/W

AS

ALE

4

16 1 MUX

:

Control/Calendar

Update

32K

Driver

Interupt

Generator

32K

INT

BD328501.eps

AD0–AD7Multiplexed address/data

input/output

The bq3285ED/LD bus cycle consists of two
phases: the address phase and the data­transfer phase. The address phase pre­cedes the data-transfer phase. During the
address phase, an address placed on
AD0–AD7and EXTRAM is latched into the
bq3285ED/LD on the falling edge of the AS
signal. During the data-transfer phase of
the bus cycle, the AD0–AD7pins serve as a
bidirectional data bus.

AS Address strobe input

AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad­dress on AD0–AD7and EXTRAM. This de­multiplexing process is independent of the
CS signal. For DIP and SOIC packages
with MOT = VSS, the AS input is provided a
signal similar to ALE in an Intel-based sys­tem.

July 1997

2

bq3285ED/LD

DS Data strobe input

When MOT = VCC, DS controls data trans­fer during a bq3285ED/LD bus cycle. Dur­ing a read cycle, the bq3285ED/LD drives
the bus after the rising edge on DS. During
a write cycle, the falling edge on DS is used
to latch write data into the chip.

When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.

R/W

CS Chip select input

INT Interrupt request output

32K 32.768 kHz output

EXTRAM Extended RAM enable

Read/write input

When MOT = VCC, the level on R/W identi­fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.

When MOT = VSS, R/W is provided a signal
similar to WR, MEMW,or I/OW in an Intel­based system. The rising edge on R/W
latches data into the bq3285ED/LD.

CS should be driven low and held stable
during the data-transfer phase of a bus cy­cle accessing the bq3285ED/LD.

INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than VCC. INT is asserted low when any
event flag is set and the corresponding
event enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).

32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at

32.768kHz as long as VCCis valid.

Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30k
pull-down resistor. To access the RTC regis­ters,EXTRAM must be low.

RCL

BC 3V backup cell input

RST Reset input

X1–X2 Crystal inputs

Ω

RAM clear input

A low level on the RCL pin causes the con­tents of each of the 242 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCC. Us­ing RAM clear does not affect the battery
load. This pin is connected internally to a
30kΩpull-up resistor.

BC should be connected to a 3V backup cell
for RTC operation and storage register non­volatility in the absence of system power.
When VCCslews down past VBC(3V typi­cal), the integral control circuitry switches
the power source to BC. When VCCreturns
above VBC, the power source is switched to
VCC.

Upon power-up, a voltage within the V
range must be present on the BC pin for
the oscillator to start up.

The bq3285ED/LD is reset when RST is
pulled low. When reset, INT becomes high
impedance, and the bq3285ED/LD is not ac­cessible. Table 4 in the Control/Status Reg­isters section lists the register bits that are
cleared by a reset.

Reset may be disabled by connecting RST
to VCC. This allows the control bits to re­tain their states through power­down/power-upcycles.

The X1–X2 inputs are provided for an ex­ternal 32.768kHz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci­tance. A trimming capacitor may be neces­sary for extremely precise time-base gen­eration.

In the absence of a crystal, a 32.768kHz
waveformcan be fed into the X1 input.

BC

July 1997

3

bq3285ED/LD

Functional Description

Address Map

The bq3285ED/LD provides 14 bytes of clock and con­trol/status registers and 242 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq3285ED/LD.

Update Period

The update period for the bq3285ED/LD is one second.
The bq3285ED/LD updates the contents of the clock and
calendar locations during the update cycle at the end of

16 Bytes

114

Bytes

128

Bytes

0

13
14

127

0

127

Clock and

Control Status

Registers

Storage

Registers

with

EXTRAM = 0

Storage

Registers

with

EXTRAM = 1

00

0D
0E

7F
00

7F

each update period (see Figure 2). The alarm flag bit
may also be set during the update cycle.

The bq3285ED/LD copies the local register updates into
the user buffer accessed by the host processor. When a 1
is written to the update transfer inhibit bit (UTI) in reg­ister B, the user copy of the clock and calendar bytes re­mains unchanged, while the local copy of the same bytes
continues to be updated every second.

The update-in-progress bit (UIP) in register A is set

time before the beginning of an update cycle (see

t

BUC

Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.

0
1

Seconds Alarm

2

Minutes Alarm

3
4

Hours Alarm

5
6

Day of Week

7

Date of Month
8
9

10
11
12

Day of Month

13

Seconds

Minutes

Hours

Month

Year
Register A
Register B

Register C

Alarm

00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D

FG328501.eps

BCD

or
Binary
Format

UIP

Figure 1. Address Map

Update Period

(1 sec.)

t

BUC

Figure 2. Update Period Timing and UIP

4

t

UC

TD3285e1.eps

(Update Cycle)

July 1997

bq3285ED/LD

Programming the RTC

The time-of-day, alarm, and calendar bytes can be writ­ten in either the BCD or binary format (see Table 2).

These steps may be followed to program the time, alarm,
and calendar:

1. Modify the contents of register B:
a. Writea1totheUTIbittoprevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to thedata

format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.

c. Write the appropriate valueto the hour

format (HF) bit.

2. Write new values to all thetime, alarm, and
calendar locations.

3. Clear the UTI bit to allowupdate transfers.

On the next update cycle, the RTC updates all 10 bytes
in the selected format.

Table 2. Time, Alarm, and Calendar Formats

Range

Address RTC Bytes

0 Seconds 0–59 00H–3BH 00H–59H
1 Seconds alarm 0–59 00H–3BH 00H–59H

Decimal Binary

Binary-Coded

Decimal

2 Minutes 0–59 00H–3BH 00H–59H
3 Minutes alarm 0–59 00H–3BH 00H–59H

4

Hours, 12-hour format 1–12

Hours, 24-hour format 0–23 00H–17H 00H–23H

Hours alarm, 12-hour format 1–12

5

Hours alarm, 24-hour format 0–23 00H–17H 00H–23H
6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H
7 Day of month 1–31 01H–1FH 01H–31H
8 Month 1–12 01H–0CH 01H–12H
9 Year 0–99 00H–63H 00H–99H

D Day of month alarm 1–31 01H-1FH 01–31H

July 1997

01H–OCH AM;

81H–8CH PM

01H–OCH AM;

81H–8CH PM

5

01H–12H AM;

81H–92H PM

01H–12H AM;

81H–92H PM

bq3285ED/LD

32kHz Output

The bq3285ED/LD provides for a 32.768kHz output, and
the output is always active whenever VCCis valid (V
+t

). The bq3285ED/LD output is not affected by the

CSR

bit settings in Register A. Time-keeping aspects, how­ever,still require setting OS0-OS2.

Interrupts

The bq3285ED/LD allows three individually selected in­terrupt events to generate an interrupt request. These

Each of the three interrupt events is enabled by an indi­vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre­sponding event enable bit is also set, then an interrupt

PFD

request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT

high-impedance.

Two methods can be used to process bq3285ED/LD in­terrupt events:

Enable interrupt events and use the interrupt

n

request output to invoke an interrupt service routine.

three interrupt events are:

The periodic interrupt, programmable to occur once

n

every 122µs to 500ms.
The alarm interrupt, programmable to occur once per

n

second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.

The update-ended interrupt, which occurs at the end

n

Do not enable the interrupts and use a polling

n

routine to periodically check the status of the flag
bits.

The individual interrupt sources are described in detail
in the following sections.

of each update cycle.

Table 3. Periodic Interrupt Rate

Register A Bits Periodic Interrupt

OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0 Period Units

0100000None
0100001 3.90625 ms
0100010 7.8125 ms
0100011 122.070
0100100 244.141
0100101 488.281
0100110 976.5625
0100111 1.95315 ms
0101000 3.90625 ms
0101001 7.8125 ms
0101010 15.625 ms
0101011 31.25 ms
0101100 62.5 ms
0101101 125 ms
0101110 250 ms
0101111 500 ms

011XXXX

same as above defined

by RS3–RS0

µ
µ
µ
µ

s
s
s
s

July 1997

6

PeriodicInterrupt

If the periodic interrupt event is enabled by writing a 1
to the periodic interrupt enable bit (PIE) in register C,
an interrupt request is generated once every 122µsto
500ms. The period between interrupts is selected with
bits RS3-RS0 in register A (see Table3).

Alarm Interrupt

The alarm interrupt is active in battery-backup mode,
providing a “wake-up” capability. During each update
cycle, the RTC compares the day-of-the-month, hours,
minutes, and seconds bytes with the four corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is gen­erated.

An alarm byte may be removed from the comparison by
setting it to a “don't care” state. The seconds, minutes,
and hours alarm bytes are set to a “don't care” state by
writinga1toeachofitstwomost-significant bits. The
day-of-the-month alarm byte is set to a “don’t care”state
by setting DA5–DA0, in register D, to all zeros. A “don't
care” state may be used to select the frequency of alarm
interrupt events as follows:

n

If none of the four alarm bytes is “don't care,” the
frequency is once per month, when day-of-the-month,
hours, minutes, and seconds match.

n

If only the day-of-the-month alarm byte is “don’t
care”, the frequency is once per day, when hours,
minutes, and seconds match.

n

If only the day-of-the-month and hour alarm byte is
“don't care,” the frequency is once per hour, when
minutes and seconds match.

n

If only the day-of-the-month, hour and minute alarm
bytes are “don't care,” the frequency is once per
minute, when seconds match.

bq3285ED/LD

If the day-of-the-month, hour, minute, and second

n

alarm bytes are “don't care,” the frequency is once
per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set to
a 1 at the end of an update cycle. If the update interrupt
enable bit (UIE) of register B is 1, and the update transfer
inhibit bit (UTI) in register B is 0, then an interrupt re­quest is generated at the end of each update cycle.

Accessing RTC bytes

The EXTRAM pin must be low to access the RTC regis­ters. Time and calendar bytes read during an update
cycle may be in error. Three methods to access the time
and calendar bytes without ambiguity are:

Enable the update interrupt event to generate

n

interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).

Poll the update-in-progress bit (UIP) in register A. If

n

UIP = 0, the polling routine has a minimum of t
time to access the clock bytes (see Figure 3).

n

Use the periodic interrupt event to generate
interrupt requests every tPItime, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2+t
time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq3285ED/LD and
VCCis above V
divider are turned on by writing a 010 pattern to bits 4
through 6 of register A. A pattern of 11X turns the os­cillator on but keeps the frequency divider disabled.Any

, the internal oscillator and frequency

PFD

BUC

BUC

July 1997

1 Sec.

UIP

PF

UF

(tPl)/2 (tPl)/2 t

Pl

t

BUC

Figure 3. Update-Ended/Periodic Interrupt Relationship

7

t

UC

T3285L02.eps

bq3285ED/LD

other pattern to these bits keeps the oscillator off. A
pattern of 010 must be set for the bq3285ED/LD to keep
time in battery backup mode.

Power-Down/Power-Up Cycle

The bq3285ED and bq3285LD power-up/power-down cy­cles are different. The bq3285LD continuously monitors
VCCfor out-of-tolerance. During a power failure, when
VCCfalls below V

(2.53V typical), the bq3285LD write-

PFD

protects the clock and storage registers . The power source
is switched to BC when VCCis less than V
greater than V
is less than V

, or when VCCis less than VBCand V

PFD

. RTC operation and storage data are

PFD

PFD

and BC is

BC

sustained by a valid backup energy source. When VCCis
above V
tinues for t

The bq3285ED continuously monitors V

, the power source is VCC. Write-protection con-

PFD

time after VCCrises above V

CSR

PFD

CC

.

for out-of­tolerance. During a power failure, when VCCfalls below
V

(4.17V typical), the bq3285ED write-protects the

PFD

clock and storage registers. When VCCis below VBC(3V
typical), the power source is switched to BC. RTC opera­tion and storage data are sustained by a valid backup
energy source. When VCCis above VBC, the power
source is VCC. Write-protection continues for t
after VCCrises above V

PFD

.

CSR

time

Control/Status Registers

The four control/status registers of the bq3285ED/LD
are accessible regardless of the status of the update cy­cle (see Table4).

Register A

Register A Bits

76543210

UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0

Register A programs:

The frequency of the periodic event rate.

n

Oscillator operation.

n

Time-keeping

n

Register A provides:

Status of the update cycle.

n

RS0–RS3 - Frequency Select

76543210

----RS3RS2RS1RS0

These bits select the periodic interrupt rate, as shown in
Table3.

OS0–OS2 - Oscillator Control

76543210

-OS2OS1OS0----

These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op­eration by turning on the oscillator andenabling the fre­quency divider. This pattern must be set to turn the os­cillator on and to ensure that the bq3285ED/LD keeps
time in battery-backup mode. A pattern of 11X turnsthe
oscillator on, but keeps the frequency divider disabled.
When 010 is written, the RTC begins its first update af­ter 500ms.

Table 4. Control/Status Registers

Loc.

Reg.

(Hex) Read Write

A 0A Yes Yes

7 (MSB) 6 5 4 3 2 1 0 (LSB)

1

UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na
B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 - 0 DF na HF na DSE na
C 0C Yes No INTF 0 PF 0 AF 0 UF 0 - 0 - na - 0 - 0

2

D 0D Yes Yes

VRT na - 0 DA5 na DA4 na DA3 na DA2 na DA1 na DA0 na

Notes: na = not affected.

1. Except bit 7.

2. Except bits 6 and 7.

Bit Name and State on Reset

8

July 1997

bq3285ED/LD

UIP - Update Cycle Status

76543210

UIP-------

This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.

Register B

Register B Bits

7654 3 210

UTI PIE AIE UIE - DF HF DSE

Register B enables:

Update cycle transfer operation

n

Interrupt events

n

n

Daylight saving adjustment

Register B selects:

n

Clock and calendar data formats

All bits of register B are read/write.

Bit 3 - Unused Bit.

DSE - Daylight Saving Enable

7654 3 210

---- - --DSE

This bit enables daylight-saving time adjustments when
written to 1:

n

On the last Sunday in October, the first time the
bq3285ED/LD increments past 1:59:59 AM, the time
falls back to 1:00:00 AM.

n

On the first Sunday in April, the time springs
forward from 2:00:00 AM to 3:00:00 AM.

HF - Hour Format

7654 3 210

---- - -HF-

DF - Data Format

7654 3 210

---- -DF--

This bit selects the numeric format in which the time,
alarm,and calendar bytes are represented:

1 = Binary
0 = BCD

UIE - Update Cycle Interrupt Enable

7654 3 210

---UIE- ---

This bit enables an interrupt request due to an update
ended interrupt event:

1 = Enabled
0 = Disabled

The UIE bit is automatically cleared when the UTI bit
equals 1.

AIE - Alarm Interrupt Enable

7654 3 210

--AIE- - ---

This bit enables an interrupt request due to an alarm
interrupt event:

1 = Enabled
0 = Disabled

PIE - PeriodicInterrupt Enable

7654 3 210

-PIE-- - ---

This bit enables an interrupt request due to a periodic
interrupt event:

1 = Enabled
0 = Disabled

This bit selects the time-of-day and alarm hour format:

1 = 24-hour format
0 = 12-hour format

July 1997

UTI - Update TransferInhibit

7654 3 210

UTI--- - ---

9

bq3285ED/LD

This bit inhibits the transfer of RTC bytes to the user
buffer:

1 = Inhibits transfer and clears UIE
0 = Allows transfer

Register C

Register C Bits

7654 3 210

INTF PF AF UF 0 - 0 0

Register C is the read-only event status register.

Bits 0, 1, 2, 3 - Unused Bits

7654 3 210

----0-00

These bits are always set to 0.

UF - Update Event Flag

7654 3 210

---UF----

This bit is set toa1attheendoftheupdate cycle.
Reading register C clears this bit.

AF - Alarm Event Flag

7654 3 210

--AF- - ---

This bit is set to a 1 when an alarm event occurs. Read­ing register C clears this bit.

PF - PeriodicEvent Flag

7654 3 210

-PF- - - - - -

This bit is set to a 1 every t
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.

time, where tPIis the time

PI

AIE = 1 and AF = 1
PIE = 1 and PF = 1
UIE = 1 and UF = 1

Reading register C clears this bit.

Register D

Register D Bits

7654 3 210

VRT 0 DA5 DA4 DA3 DA2 DA1 DA0

Register D provides for the read-only data integrity
status bit, and the day-of-the-month alarm.

Bits6-UnusedBit

7654 3 210

-0-- - ---

This bit is always set to 0.

VRT - Valid RAM and Time

7654 3 210

VRT - - - - - - -

1 = Validbackup energy source
0 = Backup energy source is depleted

When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.

DA0–DA5

7654 3 210

- - DA5 DA4 DA3 DA2 DA1 DA0-

These bits store the value for the day-of-the-month
alarm. If DA0–DA5 are set to zero, then the day-of-the­month alarm is disabled . These bits are not affected by
a reset.

INTF - Interrupt Request Flag

7654 3 210

INTF - - - - - - -

This flag is set to a 1 when any of the following is true:

July 1997

10

bq3285ED/LD

Absolute Maximum Ratings—bq3285ED

Symbol Parameter Value Unit Conditions

V

CC

V

T

T

OPR

T

STG

T

BIAS

T

SOLDER

DC voltage applied on VCCrelative to V
DC voltage applied on any pin excluding V

relative to V

SS

SS

CC

Operating temperature 0 to +70 °C Commercial
Storage temperature -55 to +125 °C
Temperature under bias -40 to +85 °C
Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed inthis data sheet. Expo­sure to conditions beyond the operational limits for extended periods of timemay affect device reliability.

Absolute Maximum Ratings—bq3285LD

-0.3 to 7.0 V

-0.3 to 7.0 V V

+ 0.3

V

≤

T

CC

Symbol Parameter Value Unit Conditions

V

CC

V

T

T

OPR

T

STG

T

BIAS

T

SOLDER

DC voltage applied on VCCrelative to V
DC voltage applied on any pin excluding V

relative to V

SS

SS

CC

Operating temperature 0 to +70 °C Commercial
Storage temperature -55 to +125 °C
Temperature under bias -40 to +85 °C
Soldering temperature 260 °C For 10 seconds

-0.3 to 7.0 V

-0.3 to 7.0 V V

V

+ 0.3

≤

T

CC

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded.Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed inthis data sheet. Expo­sure to conditions beyond the operational limits for extended periods of timemay affect device reliability.

July 1997

11

bq3285ED/LD

Recommended DC Operating Conditions—bq3285ED (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit

V

CC

V

SS

V

IL

V

IH

V

BC

Supply voltage 4.5 5.0 5.5 V
Supply voltage 0 0 0 V
Input low voltage -0.3 - 0.8 V
Input high voltage 2.2 - VCC+ 0.3 V
Backup cell voltage 2.4 - 4.0 V

Note: Typical values indicate operation at TA= 25°C.

Recommended DC Operating Conditions—bq3285LD (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit

V

CC

V

SS

V

IL

V

IH

V

BC

Supply voltage 2.7 3.0 5.5 V
Supply voltage 0 0 0 V
Input low voltage -0.3 - 0.6 V
Input high voltage 2.2 - VCC+ 0.3 V
Backup cell voltage 2.4 - 4.0 V

Note: Typical values indicate operation at TA= 25°C.

Crystal Specifications—bq3285ED/LD (DT-26 or Equivalent)

Symbol Parameter Minimum Typical Maximum Unit

f

O

C

L

T

P

k Parabolic curvature constant - - -0.042 ppm/°C
Q Quality factor 40,000 70,000 ­R

1

C

0

C

0/C1

D

L

f/f

∆

O

Oscillation frequency - 32.768 - kHz
Load capacitance - 6 - pF
Temperature turnover point 20 25 30 °C

Series resistance - - 45 K
Shunt capacitance - 1.1 1.8 pF
Capacitance ratio - 430 600
Drive level - - 1

W

µ

Aging (first year at 25°C) - 1 - ppm

July 1997

12

Ω

bq3285ED/LD

DC Electrical Characteristics—bq3285ED (T

A=TOPR,VCC

= 5V)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

I

LI

Input leakage current - -

1

±

AVIN=VSSto V

µ

CC

AD0–AD7and INT in

I

LO

V

OH

V

OL

I

CC

I

CCSB

V

SO

I

CCB

V

PFD

I

RCL

I

MOTH

Output leakage current - -

1

±

A

high impedance,

µ

V

OUT=VSS

Output high voltage 2.4 - - V IOH= -2.0 mA

Output low voltage - - 0.4 V IOL= 4.0 mA

Operating supply current - 7 15 mA

Standby supply current

Supply switch-over voltage - V

-

300 -

BC

-V

Battery operation current - 0.4 0.55

Min. cycle, duty = 100%,
IOH= 0mA, IOL= 0mA

V

IN=VSS

CS≥VCC- 0.2

A

µ

AVBC=3V,TA= 25°C

µ

or VCC,

Power-fail-detectvoltage 4.0 4.17 4.35 V

Input current when RCL =VSS. - - 185

Input current when MOT = V

Input current when MOT = V

CC

SS

- - -185

--0

A Internal 30K pull-up

µ

A Internal 30K pull-down

µ

A Internal 30K pull-down

µ

to V

CC

I

XTRAM

Input current when EXTRAM =
V

CC

Input current when EXTRAM =
V

SS

- - -185

--0

Note: Typical values indicate operation at TA= 25°C, VCC=5VorVBC=3V.

July 1997

13

A Internal 30K pull-down

µ

A Internal 30K pull-down

µ

bq3285ED/LD

DC Electrical Characteristics—bq3285LD (T

Symbol Parameter Minimum Typical

I

LI

I

LO

V

V

I

CC

I

CCSB

V

I

CCB

V

I

RCL

OH

OL

SO

PFD

Input leakage current - -

Output leakage current - -

Output high voltage 2.2 - - V IOH= -1.0 mA

Output low voltage - - 0.4 V IOL= 2.0 mA

Operating supply current - 5

2

Standby supply current - 100

Supply switch-over voltage

-V

PFD

-VBC-VV

Battery operation current - 0.4 0.55

Power-fail-detectvoltage 2.4 2.53 2.65 V

Input current when RCL =VSS. - - 120

A=TOPR,VCC

1

Maximum Unit Conditions/Notes

= 3V)

1

±

AVIN=VSSto V

µ

AD0–AD7and INT in high

1

±

9mA

3

-

-VV

A

impedance,

µ

V

OUT=VSS

Min. cycle, duty = 100%,

I

= 0mA, IOL= 0mA

OH

V

IN=VSS

A

µ

CS

BC

BC

V

BC

A

µ

VCC<V

A Internal 30Kpull-up

µ

or VCC,

- 0.2

V

≥

CC

>V

PFD

<V

PFD

=3V,TA= 25°C,

BC

to V

CC

CC

I

MOTH

I

XTRAM

Input current when MOT = V

Input current when MOT = V

CC

SS

Input current when EXTRAM =
V

CC

Input current when EXTRAM =
V

SS

- - -120

--0

- - -120

--0

Notes: 1. Typical values indicate operation at TA= 25°C, VCC=3V.

2. 7mAat V

3. 300µAatV

CC

=5V

CC

=5V

14

A Internal 30Kpull-down

µ

A Internal 30Kpull-down

µ

A Internal 30Kpull-down

µ

A Internal 30Kpull-down

µ

July 1997

bq3285ED/LD

Capacitance—bq3285ED/LD (T

Symbol Parameter Minimum Typical Maximum Unit Conditions

C

I/O

C

IN

Note: This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin.

Input/output capacitance - - 7 pF V
Input capacitance - - 5 pF VIN=0V

= 25°C, F = 1MHz,VCC= 5.0V)

A

OUT

=0V

AC Test Conditions—bq3285ED

Parameter Test Conditions

Input pulse levels 0 to 3.0 V
Input rise and fall times 5 ns
Input and output timing reference levels 1.5 V (unless otherwise specified)
Output load (including scope and jig) See Figures 4 and 5

For all outputs

except INT

+5V

960

INT

+5V

1.15k

510

Figure 4. Output Load—bq3285ED

July 1997

50pF

130pF

Figure 5. Output Load—bq3285ED

15

bq3285ED/LD

AC Test Conditions—bq3285LD

Parameter Test Conditions

Input pulse levels 0 to 2.3 V, VCC=3V
Input rise and fall times 5 ns
Input and output timing reference levels 1.2 V (unless otherwise specified)
Output load (including scope and jig) See Figures 6 and 7

Note: 1. For 5V timing, please refer to bq3285ED.

1

+3.3V

1238

For all outputs

except INT

1164

50pF

Figure 6. Output Load—bq3285LD

+3.3V

1.45k

INT

130pF

Figure 7. Output Load B—bq3285LD

16

July 1997

bq3285ED/LD

Read/Write Timing—bq3285ED (T

A=TOPR,VCC

= 5V)

Symbol Parameter Minimum Typical Maximum Unit Notes

t

CYC

t

DSL

t

DSH

t

RWH

t

RWS

t

CS

t

CH

t

DHR

t

DHW

t

AS

t

AH

t

DAS

t

ASW

t

ASD

t

OD

t

DW

t

BUC

t

PI

t

UC

Cycle time 160 - - ns
DS low or RD/WR high time 80 - - ns
DS high or RD/WR low time 55 - - ns
R/W hold time 0 - - ns
R/W setup time 10 - - ns
Chip select setup time 5 - - ns
Chip select hold time 0 - - ns
Read data hold time 0 - 25 ns
Write data hold time 0 - - ns
Address setup time 20 - - ns
Address hold time 5 - - ns
Delay time, DS to AS rise 10 - - ns
Pulse width, AS high 30 - - ns
Delay time, AS to DS rise (RD/WR

fall)
Output data delay time from DS rise

(RD fall)

35 - - ns

- - 50 ns

Write data setup time 30 - - ns
Delay time before update cycle - 244 -

s

µ

Periodic interrupt time interval ----SeeTable 3
Time of update cycle - 1 -

s

µ

July 1997

17

bq3285ED/LD

Read/Write Timing—bq3285LD (T

A=TOPR,VCC

= 3V)

Symbol Parameter Minimum Typical Maximum Unit Notes

t

CYC

t

DSL

t

DSH

t

RWH

t

RWS

t

CS

t

CH

t

DHR

t

DHW

t

AS

t

AH

t

DAS

t

ASW

t

ASD

t

OD

t

DW

t

BUC

t

PI

t

UC

Cycle time 270 - - ns
DS low or RD/WR high time 135 - - ns
DS high or RD/WR low time 90 - - ns
R/W hold time 0 - - ns
R/W setup time 15 - - ns
Chip select setup time 8 - - ns
Chip select hold time 0 - - ns
Read data hold time 0 - 40 ns
Write data hold time 0 - - ns
Address setup time 30 - - ns
Address hold time 15 - - ns
Delay time, DS to AS rise 15 - - ns
Pulse width, AS high 50 - - ns
Delay time, AS to DS rise (RD/WR fall) 55 - - ns
Output data delay time from DS rise

(RD fall)

- - 100 ns

Write data setup time 50 - - ns
Delay time before update cycle - 244 -

s

µ

Periodic interrupt time interval ----SeeTable 3
Time of update cycle - 1 -

s

µ

18

July 1997

Motorola Bus Read/Write Timing—bq3285ED/LD

t

ASW

AS

bq3285ED/LD

DS

R/W

CS

AD0 -AD

(WRITE)

AD0 -AD

(READ)

t

DAS

t

DSL

t

RWS

t

CS

t

AS

7

t

AS

7

t

ASD

t

CYC

t

DSH

t

RWH

t

CH

t

AH

t

AH

t

DW

t

OD

t

DHW

t

DHR

T3285L03.eps

July 1997

19

bq3285ED/LD

Intel Bus Read Timing—bq3285ED/LD

AS (ALE)

t

CYC

t

ASW

DS (RD)

t

DSL

R/W (WR)

t

DAS

t

CS

CS

t

AS

AD0 -AD

7

Intel Bus Write Timing—bq3285ED/LD

AS (ALE)

t

ASW

t

DSL

DS (RD)

t

DAS

t

t

ASD

t

AH

ASD

t

CYC

t

DSH

t

OD

t

DSH

t

CH

t

DHR

T3285L04.eps

R/W (WR)

CS

AD0 -AD

t

CS

t

AS

t

AH

t

DW

t

DHW

t

CH

T3285L05.eps

July 1997

20

bq3285ED/LD

Power-Down/Power-Up Timing—bq3285ED (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Conditions

t

F

t

R

VCCslew from 4.5V to 0V 300 - ­VCCslew from 0V to 4.5V 100 - -

s

µ

s

µ

Internal write-protection

t

CSR

CS at VIHafter power-up 20 - 200 ms

period after VCCpasses V

PFD

on power-up.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Power-Down/Power-Up Timing—bq3285ED

t

F

4.5
V

V

CC

PFD

V

SO

t

R

4.5

V

PFD

V

SO

CS

July 1997

21

t

CSR

T3285L08.eps

bq3285ED/LD

Power-Down/Power-Up Timing—bq3285LD (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Conditions

t

F

t

R

VCCslew from 2.7V to 0V 300 - ­VCCslew from 0V to 2.7V 100 - -

s

µ

s

µ

Internal write-protection

t

CSR

CS at VIHafter power-up 20 - 200 ms

period after VCCpasses V

PFD

on power-up.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Power-Down/Power-Up Timing—bq3285LD

t

F

2.7

V

V

CC

PFD

V

SO

t

R

2.7

V

PFD

V

SO

t

CSR

CS

INT

(Alarm)

T3285L06.eps

July 1997

22

bq3285ED/LD

Interrupt Delay Timing—bq3285ED/LD

(TA=T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit

t

RSW

t

IRR

t

IRD

Reset pulse width 5 - ­INT release from RST --2
INT release from DS - - 2

Interrupt Delay Timing—bq3285ED/LD

RD (Intel)

DS (Mot)

t

RSW

RST

INT

s

µ

s

µ

s

µ

July 1997

t

IRD

t

IRR

T3285L07.eps

23

bq3285ED/LD

24-Pin SSOP (SS)

24-Pin SS(0.150" SSOP

Inches Millimeters

Dimension

A 0.061 0.068 1.55 1.73

A1 0.004 0.010 0.10 0.25

B 0.008 0.012 0.20 0.30
C 0.007 0.010 0.18 0.25
D 0.337 0.344 8.56 8.74
E 0.150 0.157 3.81 3.99

e .025 BSC 0.64 BSC
H 0.230 0.244 5.84 6.20
L 0.016 0.035 0.41 0.89

Min. Max. Min. Max.

)

July 1997

24

Ordering Information

bq3285ED/LD -

bq3285ED/LD

Temperature:

blank = Commercial (0 to +70°C)

PackageOption:

SS= 24-pin SSOP (0.150)

Device:

bq3285ED Real-Time Clock with 242

bytes of general storage
or
bq3285LD Real-Time Clock with 242

bytes of general storage

(3V operation)

July 1997

25

IMPORTANT NOTICE

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