Texas Instruments BQ3285ECSSTR, BQ3285ECSS, BQ3285LCSSTR, BQ3285LCSS Datasheet

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Features

➤ Direct clock/calendar replace-

ment for IBM

AT-compatible

computers and other applications

➤ 2.7–5.5V operation (bq3285LC);

4.5–5.5V operation (bq3285EC)

➤ 242 bytes of general nonvolatile

storage

➤ Dedicated 32.768kHz output pin ➤ System wake-up capability—

alarm interrupt output active in battery-backup mode

➤ Less than 0.5µA load under bat-

tery operation

➤ Selectable Intel or Motorola bus

timing

➤ 24-pin plastic SOIC or SSOP

General Description

The CMOS bq3285EC/LC is a lowpower microprocessor peripheral providing a time-of-day clock and 100year calendar with alarm features and battery operation. The architecture is based on the bq3285/7 RTC with added features: low-voltage operation, 32.768kHz output, and an extra 128bytes of CMOS.

A 32.768kHz output is available for sustaining power-management activities. The bq3285EC 32kHz output is always on whenever V

is valid. For the bq3285LC, the output is on when the oscillator is turned on. In VCCstandby mode, the 32kHz is active, and the bq3285LC typically draws 100µA while the bq3285EC typically draws 300µA. Wake-up capability is provided by an alarm interrupt, which is active

in battery-backup mode. In battery backup mode, current drain is less than 500nA.

The bq3285EC/LC write-protects the clock, calendar , and storage registers during power failure. A backup battery then maintains data and operates the clockand calendar.

The bq3285EC/LC is a fully compatible real-time clock for IBM ATcompatible computers and other applications. The only external components are a 32.768kHz crystal and a backup battery.

The bq3285EC is intended for use in 5V systems. The bq3285LC is intended for use in 3V systems; the bq3285LC, however, may also operate at 5V and then go into a 3V power-down state, write-protecting as if in a 3V system.

PN3285EC.eps

24-Pin SSOP

2 3

4 5 6 7 8

24 23

22 21 20 19 18

17 9 10

15 11 12

CC 32k EXTRAM

BC INT RST DS V

SS R/W

AS CS

MOT

X1 X2

RCL

bq3285EC/LC

Pin Connections Pin Names

July 1996

AD0–AD7Multiplexed address/

data input/output

MOT Bus type select input

CS Chip select input

AS Address strobe input

DS Data strobe input

R/W Read/write input

INT Interrupt request output

RST Reset input

32K 32.768kHz output

EXTRAM Extended RAM enable

RCL RAM clear input

BC 3V backup cell input

X1–X2 Crystal inputs

Power supply

Ground

Real-Time Clock(RTC

)

Block Diagram

Pin Descriptions

MOT Bus type select input

MOT selects bus timing for either Motorola or Intel architecture. This pin should be tied to VCCfor Motorola timing or to VSSfor Intel timing (see Table 1). The setting should not be changed during system operation. MOT is internally pulled low by a 30K

Ω

resistor.

AD0–AD7Multiplexed address/data

input/output

The bq3285EC/LC bus cycle consists of two phases: the address phase and the datatransfer phase. The address phase precedes the data-transfer phase. During the address phase, an address placed on AD0–AD7and EXTRAM is latched into the bq3285EC/LC on the falling edge of the AS signal. During the data-transfer phase of the bus cycle, the AD0–AD7pins serve as a bidirectional data bus.

AS Address strobe input

AS serves to demultiplex the address/data bus. The falling edge of AS latches the address on AD0–AD7and EXTRAM. This demultiplexing process is independent of the CS signal. For DIP and SOIC packages with MOT = VSS, the AS input is provided a signal similar to ALE in an Intel-based system.

bq3285EC/LC

Bus

Type

MOT

LevelDSEquivalent

R/W

EquivalentASEquivalent

Motorola V

DS,E,or

R/W

Intel V

RD, MEMR,or I/OR

WR, MEMW,or I/OW

ALE

Table 1. Bus Setup

BD328501.eps

Bus

I/F

Power-

Fail

Control

Storage Registers

(114 Bytes)

User Buffer

(14 Bytes)

OUT

Clock/Calendar, Alarm

and Control Bytes

TimeBase

Oscillator

Control/Status

Registers

÷ 8 ÷ 64 ÷ 64

16 1 MUX

Interupt

Generator

Control/Calendar

Update

AD0–AD

MOT

32K

INT

RST

R/W

Storage Registers

(128 Bytes)

RCL

EXTRAM

Write Protect

32K

Driver

July 1996

DS Data strobe input

When MOT = VCC, DS controls data transfer during a bq3285EC/LC bus cycle. During a read cycle, the bq3285EC/LC drives the bus after the rising edge on DS. During a write cycle, the falling edge on DS is used to latch write data into the chip.

When MOT = VSS, the DS input is provided a signal similar to RD, MEMR, or I/OR in an Intel-based system. The falling edge on DS is used to enable the outputs during a read cycle.

R/W

Read/write input

When MOT = VCC, the level on R/W identifies the direction of data transfer. A high level on R/W indicates a read bus cycle, whereas a low on this pin indicates a write bus cycle.

When MOT = VSS, R/W is provided a signal similar to WR, MEMW, or I/OW in an Intelbased system. The rising edge on R/W latches data into the bq3285EC/LC.

CS Chip select input

CS should be driven low and held stable during the data-transfer phase of a bus cycle accessing the bq3285EC/LC.

INT Interrupt request output

INT is an open-drain output. This allows alarm INT to be valid in battery-backup mode. To use this feature, connect INT through a resistor to a power supply other than VCC. INT is asserted low when any event flag is set and the corresponding event enable bit is also set. INT becomes high-impedance whenever register C is read (see the Control/Status Registers section).

32K 32.768 kHz output

32K provides a buffered 32.768 kHz output. The frequency remains on and fixed at

32.768kHz as long as VCCis valid.

EXTRAM Extended RAM enable

Enables 128 bytes of additional nonvolatile SRAM. It is connected internally to a 30k

Ω

pull-down resistor. To access the RTC registers,EXTRAM must be low.

RCL

RAM clear input

A low level on the RCL pin causes the contents of each of the 242 storage bytes to be set to FF(hex). The contents of the clock and control registers are unaffected. This pin should be used as a user-interface input (pushbutton to ground) and not connected to the output of any active component. RCL input is only recognized when held low for at least 125ms in the presence of VCC. Using RAM clear does not affect the battery load. This pin is connected internally to a 30kΩpull-up resistor.

BC 3V backup cell input

BC should be connected to a 3V backup cell for RTC operation and storage register nonvolatility in the absence of system power. When VCCslews down past VBC(3V typical), the integral control circuitry switches the power source to BC. When VCCreturns above VBC, the power source is switched to VCC.

Upon power-up, a voltage within the V

range must be present on the BC pin for the oscillator to start up.

RST Reset input

The bq3285EC/LC is reset when RST is pulled low. When reset, INT becomes high impedance, and the bq3285EC/LC is not accessible. Table 4 in the Control/Status Registers section lists the register bits that are cleared by a reset.

Reset may be disabled by connecting RST to VCC. This allows the control bits to retain their states through powerdown/power-upcycles.

X1–X2 Crystal inputs

The X1–X2 inputs are provided for an external 32.768kHz quartz crystal, Daiwa DT-26 or equivalent, with 6pF load capacitance. A trimming capacitor may be necessary for extremely precise time-base generation.

In the absence of a crystal, a 32.768kHz waveformcan befed intothe X1input.

bq3285EC/LC

July 1996

Functional Description

Address Map

The bq3285EC/LC provides 14 bytes of clock and control/status registers and 242 bytes of general nonvolatile storage. Figure 1 illustrates the address map for the bq3285EC/LC.

Update Period

The update period for the bq3285EC/LC is one second. The bq3285EC/LC updates the contents of the clock and calendar locations during the update cycle at the end of

each update period (see Figure 2). The alarm flag bit may also be set during the update cycle.

The bq3285EC/LC copies the local register updates into the user buffer accessed by the host processor. When a 1 is written to the update transfer inhibit bit (UTI) in register B, the user copy of the clock and calendar bytes remains unchanged, while the local copy of the same bytes continues to be updated every second.

The update-in-progress bit (UIP) in register A is set t

BUC

time before the beginning of an update cycle (see Figure 2). This bit is cleared and the update-complete flag (UF) is set at the end of the update cycle.

Figure 1. Address Map

Figure 2. Update Period Timing and UIP

bq3285EC/LC

July 1996

Programming the RTC

The time-of-day, alarm, and calendar bytes can be written in either the BCD or binary format (see Table 2).

These steps may be followed to program the time, alarm, and calendar:

1. Modify the contents of register B: a. Writea1totheUTIbittoprevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to the data

format (DF) bit to select BCD or binary format for all time, alarm, and calendar bytes.

c. Write the appropriate value to the hour

format (HF) bit.

2. Write new values to all the time, alarm, and calendar locations.

3. Clear the UTI bit to allow update transfers.

On the next update cycle, the RTC updates all 10 bytes in the selected format.

bq3285EC/LC

Address RTC Bytes

Range

Decimal Binary

Binary-Coded

Decimal

0 Seconds 0–59 00H–3BH 00H–59H 1 Seconds alarm 0–59 00H–3BH 00H–59H 2 Minutes 0–59 00H–3BH 00H–59H 3 Minutes alarm 0–59 00H–3BH 00H–59H

Hours, 12-hour format 1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours, 24-hour format 0–23 00H–17H 00H–23H

Hours alarm, 12-hour format 1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours alarm, 24-hour format 0–23 00H–17H 00H–23H 6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H 7 Day of month 1–31 01H–1FH 01H–31H 8 Month 1–12 01H–0CH 01H–12H 9 Year 0–99 00H–63H 00H–99H

Table 2. Time,Alarm, and Calendar Formats

July 1996

32kHz Output

The bq3285EC/LC provides for a 32.768kHz output. For the bq3285EC,the output is always active whenever V

is valid (V

PFD+tCSR

). The bq3285EC output is not affected by the bit settings in Register A. Time-keeping aspects, however, still require setting OS0-OS2. The bq3285LC output is active when the oscillator is turned on by setting the OSC0-OSC2 bits in Register A.

Interrupts

The bq3285EC/LC allows three individually selected interrupt events to generate an interrupt request. These three interrupt events are:

The periodic interrupt, programmable to occur once every 122µs to 500ms.

The alarm interrupt, programmable to occur once per second to once per day, is active in battery-backup mode, providing a “wake-up” feature.

The update-ended interrupt, which occurs at the end of each update cycle.

Each of the three interrupt events is enabled by an individual interrupt-enable bit in register B. When an event occurs, its event flag bit in register C is set. If the corresponding event enable bit is also set, then an interrupt request is generated. The interrupt request flag bit (INTF) of register C is set with every interrupt request. Reading register C clears all flag bits, including INTF, and makes INT

high-impedance.

Two methods can be used to process bq3285EC/LC interrupt events:

Enable interrupt events and use the interrupt request output to invoke an interrupt service routine.

Do not enable the interrupts and use a polling routine to periodically check the status of the flag bits.

The individual interrupt sources are described in detail in the following sections.

bq3285EC/LC

OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0 Period Units

0100000None 0100001 3.90625 ms 0100010 7.8125 ms 0100011 122.070

0100100 244.141

0100101 488.281

0100110 976.5625

s 0100111 1.95315 ms 0101000 3.90625 ms 0101001 7.8125 ms 0101010 15.625 ms 0101011 31.25 ms 0101100 62.5 ms 0101101 125 ms 0101110 250 ms 0101111 500 ms

011XXXX

same as above defined

by RS3–RS0

Table 3. Periodic Interrupt Rate

July 1996

PeriodicInterrupt

If the periodic interrupt event is enabled by writing a 1 to the periodic interrupt enable bit (PIE) in register C, an interrupt request is generated once every 122µsto 500ms. The period between interrupts is selected with bits RS3-RS0 in register A (see Table3).

Alarm Interrupt

The alarm interrupt is active in battery-backup mode, providing a “wake-up” capability. During each update cycle, the RTC compares the hours, minutes, and seconds bytes with the three corresponding alarm bytes. If a match of all bytes is found, the alarm interrupt event flag bit, AF in register C, is set to 1. If the alarm event is enabled, an interrupt request is generated.

An alarm byte may be removed from the comparison by setting it to a “don't care” state. An alarm byte is set to a “don't care” state by writinga1toeachofitstwo most-significant bits. A “don't care” state may be used to select the frequency of alarm interrupt events as follows:

If none of the three alarm bytes is “don't care,” the frequency is once per day, when hours, minutes, and seconds match.

If only the hour alarm byte is “don't care,” the frequency is once per hour, when minutes and seconds match.

If only the hour and minute alarm bytes are “don't care,” the frequency is once per minute, when seconds match.

If the hour, minute, and second alarm bytes are “don't care,” the frequency is once per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set to a 1 at the end of an update cycle. If the update interrupt enable bit (UIE) of register B is 1, and the update transfer inhibit bit (UTI) in register B is 0, then an interrupt request is generated at the end of each update cycle.

Accessing RTC bytes

The EXTRAM pin must be low to access the RTC registers. Time and calendar bytes read during an update cycle may be in error. Three methods to access the time and calendar bytes without ambiguity are:

Enable the update interrupt event to generate interrupt requests at the end of the update cycle. The interrupt handler has a maximum of 999ms to access the clock bytes before the next update cycle begins (see Figure 3).

Poll the update-in-progress bit (UIP) in register A. If UIP = 0, the polling routine has a minimum of t

BUC

time to access the clock bytes (see Figure 3).

Use the periodic interrupt event to generate interrupt requests every tPItime, such that UIP = 1 always occurs between the periodic interrupts. The interrupt handler has a minimum of tPI/2+t

BUC

time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq3285LC and VCCis above V

PFD

, the internal oscillator and frequency divider are turned on by writing a 010 pattern to bits 4 through 6 of register A. A pattern of 11X turns the oscillator on but keeps the frequency divider disabled. Any other pattern to these bits keeps the oscillator off. A pattern of 010 must be set for the bq3285EC/LC to keep time in battery backup mode.

bq3285EC/LC

Figure 3. Update-Ended/Periodic Interrupt Relationship

July 1996

Power-Down/Power-Up Cycle

The bq3285EC and bq3285LC power-up/power-down cycles are different. The bq3285LC continuously monitors VCCfor out-of-tolerance. During a power failure, when VCCfalls below V

PFD

(2.53V typical), the bq3285LC writeprotects the clock and storage registers. The power source is switched to BC when VCCis less than V

PFD

and BC is

greater than V

PFD

, or when VCCis less than VBCand V

is less than V

PFD

. RTC operation and storage data are sustained by a valid backup energy source. When VCCis above V

PFD

, the power source is VCC. Write-protection con-

tinues for t

CSR

time after VCCrises above V

PFD

The bq3285EC continuously monitors V

for out-oftolerance. During a power failure, when VCCfalls below V

PFD

(4.17V typical), the bq3285EC write-protects the clock and storage registers. When VCCis below VBC(3V typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup energy source. When VCCis above VBC, the power source is VCC. Write-protection continues for t

CSR

time

after VCCrises above V

PFD

Control/Status Registers

The four control/status registers of the bq3285EC/LC are accessible regardless of the status of the update cycle (see Table4).

The frequency of the periodic event rate.

Oscillator operation.

Time-keeping

Status of the update cycle.

RS0–RS3 - Frequency Select

These bits select the periodic interrupt rate, as shown in Table3.

OS0–OS2 - Oscillator Control

These three bits control the state of the oscillator and divider stages. A pattern of 010 or 011 enables RTC operation by turning on the oscillator and enabling the frequency divider. This pattern must be set to turn the oscillator on for the bq3285LC and to ensure that the bq3285EC/LC will keep time in battery-backup mode. A pattern of 11X turns the oscillator on, but keeps the frequency divider disabled. When 010 is written, the RTC begins its first update after 500ms.

UIP - Update Cycle Status

This read-only bit is set prior to the update cycle. When UIP equals 1, an RTC update cycle may be in progress. UIP is cleared at the end of each update cycle. This bit is also cleared when the update transfer inhibit (UTI) bit in register B is 1.

bq3285EC/LC

76543210

UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0

76543210

----RS3RS2RS1RS0

76543210

-OS2OS1OS0----

76543210

UIP-------

July 1996

Reg.

Loc.

(Hex) Read Write

Bit Name and State on Reset

7 (MSB) 6 5 4 3 2 1 0 (LSB)

A 0A Yes Yes

UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 - 0 DF na HF na DSE na C 0C Yes No INTF 0 PF 0 AF 0 UF 0 - 0 - na - 0 - 0 D0DYesNoVRTna-0-0-0 - 0-0-0-0

Notes: na = not affected.

1. Except bit 7.

Table 4. Control/Status Registers

Update cycle transfer operation

Interrupt events

Daylight saving adjustment

Clock and calendar data formats

All bits of register B are read/write.

Bit 3 - Unused Bit.

DSE - Daylight Saving Enable

This bit enables daylight-saving time adjustments when written to 1:

On the last Sunday in October, the first time the bq3285EC/LC increments past 1:59:59 AM, the time falls back to 1:00:00 AM.

On the first Sunday in April, the time springs forward from 2:00:00 AM to 3:00:00 AM.

HF - Hour Format

This bit selects the time-of-day and alarm hour format:

1 = 24-hour format 0 = 12-hour format

DF - Data Format

This bit selects the numeric format in which the time, alarm,and calendar bytes are represented:

1 = Binary 0 = BCD

UIE - Update Cycle Interrupt Enable

This bit enables an interrupt request due to an update ended interrupt event:

1 = Enabled 0 = Disabled

The UIE bit is automatically cleared when the UTI bit equals 1.

AIE - Alarm Interrupt Enable

This bit enables an interrupt request due to an alarm interrupt event:

1 = Enabled 0 = Disabled

PIE - PeriodicInterrupt Enable

This bit enables an interrupt request due to a periodic interrupt event:

1 = Enabled 0 = Disabled

UTI - Update TransferInhibit

This bit inhibits the transfer of RTC bytes to the user buffer:

1 = Inhibits transfer and clears UIE 0 = Allows transfer

bq3285EC/LC

7654 3 210

---- - --DSE

7654 3 210

---- - -HF-

7654 3 210

---- -DF--

7654 3 210

---UIE- ---

7654 3 210

UTI PIE AIE UIE - DF HF DSE

7654 3 210

--AIE- - ---

7654 3 210

-PIE-- - ---

July 1996

7654 3 210

UTI--- - ---

Bits 0, 1, 2,3 - Unused Bits

These bits are always setto 0.

UF - Update Event Flag

This bit is set toa1attheendoftheupdate cycle. Reading register C clears this bit.

AF - Alarm Event Flag

This bit is set to a 1 when an alarm event occurs. Reading register C clears this bit.

PF - PeriodicEvent Flag

This bit is set to a 1 every t

time, where tPIis the time period selected by the settings of RS0–RS3 in register A. Reading register C clears this bit.

INTF - Interrupt Request Flag

This flag is set to a 1 when any of the following is true:

AIE = 1 and AF = 1 PIE = 1 and PF = 1 UIE = 1 and UF = 1

Reading register C clears this bit.

Bits 0–6 - Unused Bits

These bits are always setto 0.

VRT - ValidRAMand Time

1 = Validbackupenergy source 0 = Backup energy source is depleted

When the backup energy source is depleted (VRT = 0), data integrity of the RTC and storage registers is not guaranteed.

7654 3 210

----0-00

7654 3 210

---UF----

7654 3 210

--AF- - ---

7654 3 210

-PF- - - - - -

7654 3 210

INTF - - - - - - -

7654 3 210

VRT000 0 000

7654 3 210

-0000 000

7654 3 210

VRT--- - ---

July 1996

bq3285EC/LC

7654 3 210

INTF PF AF UF 0 - 0 0

bq3285EC/LC

Absolute Maximum Ratings—bq3285EC

Symbol Parameter Value Unit Conditions

DC voltage applied on VCCrelative to V

-0.3 to 7.0 V

DC voltage applied on any pin excluding V

relative to V

-0.3 to 7.0 V V

≤

+ 0.3

OPR

Operating temperature 0 to +70 °C Commercial

STG

Storage temperature -55 to +125 °C

BIAS

Temperature under bias -40 to +85 °C

SOLDER

Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.

July 1996

Absolute Maximum Ratings—bq3285LC

Symbol Parameter Value Unit Conditions

DC voltage applied on VCCrelative to V

-0.3 to 7.0 V

DC voltage applied on any pin excluding V

relative to V

-0.3 to 7.0 V V

≤

+ 0.3

OPR

Operating temperature 0 to +70 °C Commercial

STG

Storage temperature -55 to +125 °C

BIAS

Temperature under bias -40 to +85 °C

SOLDER

Soldering temperature 260 °C For 10 seconds

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

bq3285EC/LC

July 1996

Recommended DC Operating Conditions—bq3285EC (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit

Supply voltage 4.5 5.0 5.5 V

Supply voltage 0 0 0 V

Input low voltage -0.3 - 0.8 V

Input high voltage 2.2 - VCC+ 0.3 V

Backup cell voltage 2.4 - 4.0 V

Note: Typicalvalues indicate operation at TA= 25°C.

Recommended DC Operating Conditions—bq3285LC (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit

Supply voltage 2.7 3.0 5.5 V

Supply voltage 0 0 0 V

Input low voltage -0.3 - 0.6 V

Input high voltage 2.2 - VCC+ 0.3 V

Backup cell voltage 2.4 - 4.0 V

Note: Typicalvalues indicate operation at TA= 25°C.

Crystal Specifications—bq3285EC/LC (DT-26 or Equivalent)

Symbol Parameter Minimum Typical Maximum Unit

Oscillation frequency - 32.768 - kHz

Load capacitance - 6 - pF

Temperature turnover point 20 25 30 °C k Parabolic curvature constant - - -0.042 ppm/°C Q Quality factor 40,000 70,000 R

Series resistance - - 45 K

Ω

Shunt capacitance - 1.1 1.8 pF C

0/C1

Capacitance ratio - 430 600 D

Drive level - - 1

∆

f/f

Aging (first year at 25°C) - 1 - ppm

bq3285EC/LC

July 1996

DC Electrical Characteristics—bq3285EC (T

A=TOPR,VCC

=5V)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

Input leakage current - -

AVIN=VSSto V

Output leakage current - -

AD0–AD7and INT in high impedance, V

OUT=VSS

to V

Output high voltage 2.4 - - V IOH= -2.0 mA

Output low voltage - - 0.4 V IOL= 4.0 mA

Operating supply current - 7 15 mA

Min. cycle, duty = 100%, IOH= 0mA, IOL= 0mA

CCSB

Standby supply current - 300 -

µA

IN=VSS

or VCC,

CS≥VCC- 0.2

Supply switch-over voltage - V

-V

CCB

Battery operation current - 0.3 0.5

AVBC=3V,TA= 25°C

PFD

Power-fail-detectvoltage 4.0 4.17 4.35 V

RCL

Input current when RCL =VSS. - - 185

A Internal 30K pull-up

MOTH

Input current when MOT = V

- - -185

A Internal 30K pull-down

Input current when MOT = V

--0

A Internal 30K pull-down

XTRAM

Input current when EXTRAM = V

- - -185

A Internal 30K pull-down

Input current when EXTRAM = V

--0

A Internal 30K pull-down

Note: Typicalvalues indicate operation at TA= 25°C,VCC=5VorVBC=3V.

bq3285EC/LC

July 1996

DC Electrical Characteristics—bq3285LC (T

A=TOPR,VCC

=3V±10%)

Symbol Parameter Minimum Typical

Maximum Unit Conditions/Notes

Input leakage current - -

AVIN=VSSto V

Output leakage current - -

AD0–AD7and INT in high impedance, V

OUT=VSS

to V

Output high voltage 2.2 - - V IOH= -1.0 mA

Output low voltage - - 0.4 V IOL= 2.0 mA

Operating supply current - 5

9mA

Min. cycle, duty = 100%,

= 0mA, IOL= 0mA

CCSB

Standby supply current - 100

IN=VSS

or VCC,

≥

- 0.2

Supply switch-over voltage

-V

PFD

-VV

PFD

-VBC-VV

PFD

CCB

Battery operation current - 0.3 0.5

=3V,TA= 25°C,

VCC<V

PFD

Power-fail-detectvoltage 2.4 2.53 2.65 V

RCL

Input current when RCL =VSS. - - 120

A Internal 30K pull-up

MOTH

Input current when MOT = V

- - -120

A Internal 30K pull-down

Input current when MOT = V

--0

A Internal 30K pull-down

XTRAM

Input current when EXTRAM = V

- - -120

A Internal 30K pull-down

Input current when EXTRAM = V

--0

A Internal 30K pull-down

Notes: 1. Typical values indicate operation at TA= 25°C,VCC=3V.

2. 7mA at V

=5V

3. 300µAatV

=5V

bq3285EC/LC

July 1996

AC Test Conditions—bq3285EC

Parameter Test Conditions

Input pulse levels 0 to 3.0 V Input rise and fall times 5 ns Input and output timing reference levels 1.5V (unless otherwise specified) Output load (including scope and jig) See Figures 4 and 5

Capacitance—bq3285EC/LC (T

= 25°C, F = 1MHz, VCC= 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

I/O

Input/output capacitance - - 7 pF V

OUT

=0V

Input capacitance - - 5 pF VIN=0V

Note: Thisparameter is sampled and not 100% tested. It does not include the X1 or X2 pin.

+5V

960

50pF

For all outputs

except INT

510

Figure 4. Output Load—bq3285EC

+5V

1.15k

130pF

INT

Figure 5. Output Load—bq3285EC

bq3285EC/LC

July 1996

AC Test Conditions—bq3285LC

Parameter Test Conditions

Input pulse levels 0 to 2.3 V, VCC=3V

Input rise and fall times 5 ns Input and output timing reference levels 1.2V (unless otherwise specified) Output load (including scope and jig) See Figures 6 and 7

Note: 1. For 5V timing,please refer to bq3285EC.

+3.3V

1238

50pF

For all outputs

except INT

1164

Figure 6. Output Load—bq3285LC

+3.3V

1.45k

130pF

INT

Figure 7. Output Load B—bq3285LC

bq3285EC/LC

July 1996

Read/Write Timing—bq3285EC (T

A=TOPR,VCC

=5V±10%)

Symbol Parameter Minimum Typical Maximum Unit Notes

CYC

Cycle time 160 - - ns

DSL

DS low or RD/WR high time 80 - - ns

DSH

DS high or RD/WR low time 55 - - ns

RWH

R/W hold time 0 - - ns

RWS

R/W setup time 10 - - ns

Chip select setup time 5 - - ns

Chip select hold time 0 - - ns

DHR

Read data hold time 0 - 25 ns

DHW

Write data hold time 0 - - ns

Address setup time 20 - - ns

Address hold time 5 - - ns

DAS

Delay time, DS to AS rise 10 - - ns

ASW

Pulse width, AS high 30 - - ns

ASD

Delay time, AS to DS rise (RD/WR fall)

35 - - ns

Output data delay time from DS rise (RD fall)

- - 50 ns

Write data setup time 30 - - ns

BUC

Delay time before update cycle - 244 -

Periodic interrupt time interval ----SeeTable 3

Time of update cycle - 1 -

bq3285EC/LC

July 1996

Read/Write Timing—bq3285LC (T

A=TOPR,VCC

=3V±10%)

Symbol Parameter Minimum Typical Maximum Unit Notes

CYC

Cycle time 270 - - ns

DSL

DS low or RD/WR high time 135 - - ns

DSH

DS high or RD/WR low time 90 - - ns

RWH

R/W hold time 0 - - ns

RWS

R/W setup time 15 - - ns

Chip select setup time 8 - - ns

Chip select hold time 0 - - ns

DHR

Read data hold time 0 - 40 ns

DHW

Write data hold time 0 - - ns

Address setup time 30 - - ns

Address hold time 15 - - ns

DAS

Delay time, DS to AS rise 15 - - ns

ASW

Pulse width, AS high 50 - - ns

ASD

Delay time, AS to DS rise (RD/WR fall) 55 - - ns

Output data delay time from DS rise (RD fall)

- - 100 ns

Write data setup time 50 - - ns

BUC

Delay time before update cycle - 244 -

Periodic interrupt time interval ----SeeTable 3

Time of update cycle - 1 -

bq3285EC/LC

July 1996

Motorola Bus Read/Write Timing—bq3285EC/LC

bq3285EC/LC

July 1996

Intel Bus Write—bq3285EC/LC

Intel Bus Read Timing—bq3285EC/LC

bq3285EC/LC

July 1996

Power-Down/Power-Up Timing—bq3285EC (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Conditions

VCCslew from 4.5V to 0V 300 - -

VCCslew from 0V to 4.5V 100 - -

CSR

CS at VIHafter power-up 20 - 200 ms

Internal write-protection period after VCCpasses V

PFD

on power-up.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Power-Down/Power-Up Timing—bq3285EC

bq3285EC/LC

July 1996

Power-Down/Power-Up Timing—bq3285LC

Power-Down/Power-Up Timing—bq3285LC (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Conditions

VCCslew from 2.7V to 0V 300 - -

VCCslew from 0V to 2.7V 100 - -

CSR

CS at VIHafter power-up 20 - 200 ms

Internal write-protection period after VCCpasses V

PFD

on power-up.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

bq3285EC/LC

July 1996

Interrupt Delay Timing—bq3285EC/LC

(TA=T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit

RSW

Reset pulse width 5 - -

IRR

INT release from RST --2

IRD

INT release from DS - - 2

July 1996

bq3285EC/LC

24-Pin SOIC (S)

.004

24-Pin S(0.300" SOIC

)

Dimension

Inches Millimeters

Min. Max. Min. Max.

A 0.095 0.105 2.41 2.67

A1 0.004 0.012 0.10 0.30

B 0.013 0.020 0.33 0.51 C 0.008 0.013 0.20 0.33 D 0.600 0.615 15.24 15.62 E 0.290 0.305 7.37 7.75

e 0.045 0.055 1.14 1.40 H 0.395 0.415 10.03 10.54 L 0.020 0.040 0.51 1.02

24-Pin SS(0.150" SSOP

)

Dimension

Inches Millimeters

Min. Max. Min. Max.

A 0.061 0.068 1.55 1.73

A1 0.004 0.010 0.10 0.25

B 0.008 0.012 0.20 0.30 C 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99

e .025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20

L 0.016 0.035 0.41 0.89

24-Pin SSOP (SS)

July 1996

bq3285EC/LC

Ordering Information

bq3285EC/LC -

PackageOption:

SS= 24-pin SSOP (0.150)

Device:

bq3285EC Real-Time Clock with 242

bytes of general storage or bq3285LC Real-Time Clock with 242

bytes of general storage

(3V operation)

Temperature:

blank = Commercial (0 to +70°C)

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Texas Instruments BQ3285ECSSTR, BQ3285ECSS, BQ3285LCSSTR, BQ3285LCSS Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual