Texas Instruments BQ3285ECSSTR, BQ3285ECSS, BQ3285LCSSTR, BQ3285LCSS Datasheet

Features

➤ Direct clock/calendar replace-

ment for IBM

®

AT-compatible

computers and other applications

➤ 2.7–5.5V operation (bq3285LC);

4.5–5.5V operation (bq3285EC)

➤ 242 bytes of general nonvolatile

storage

➤ Dedicated 32.768kHz output pin
➤ System wake-up capability—

alarm interrupt output active in
battery-backup mode

➤ Less than 0.5µA load under bat-

tery operation

➤ Selectable Intel or Motorola bus

timing

➤ 24-pin plastic SOIC or SSOP

General Description

The CMOS bq3285EC/LC is a low­power microprocessor peripheral pro­viding a time-of-day clock and 100­year calendar with alarm features
and battery operation. The architec­ture is based on the bq3285/7 RTC
with added features: low-voltage op­eration, 32.768kHz output, and an
extra 128bytes of CMOS.

A 32.768kHz output is available for
sustaining power-management ac­tivities. The bq3285EC 32kHz out­put is always on whenever V

CC

is
valid. For the bq3285LC, the output
is on when the oscillator is turned
on. In VCCstandby mode, the
32kHz is active, and the bq3285LC
typically draws 100µA while the
bq3285EC typically draws 300µA.
Wake-up capability is provided by
an alarm interrupt, which is active

in battery-backup mode. In battery
backup mode, current drain is less
than 500nA.

The bq3285EC/LC write-protects the
clock, calendar , and storage registers
during power failure. A backup
battery then maintains data and oper­ates the clockand calendar.

The bq3285EC/LC is a fully com­patible real-time clock for IBM AT­compatible computers and other ap­plications. The only external compo­nents are a 32.768kHz crystal and a
backup battery.

The bq3285EC is intended for use in
5V systems. The bq3285LC is in­tended for use in 3V systems; the
bq3285LC, however, may also oper­ate at 5V and then go into a 3V
power-down state, write-protecting
as if in a 3V system.

1

1

PN3285EC.eps

24-Pin SSOP

2
3

4
5
6
7
8

24
23

22
21
20
19
18

17
9
10

16

15
11
12

14

13

V

CC
32k
EXTRAM

BC
INT
RST
DS
V

SS
R/W

AS
CS

MOT

X1
X2

AD

0

AD

1

AD

2

AD

3

AD

4

AD

5

AD

6

AD

7

V

SS

RCL

bq3285EC/LC

Pin Connections Pin Names

July 1996

AD0–AD7Multiplexed address/

data input/output

MOT Bus type select input

CS Chip select input

AS Address strobe input

DS Data strobe input

R/W Read/write input

INT Interrupt request output

RST Reset input

32K 32.768kHz output

EXTRAM Extended RAM enable

RCL RAM clear input

BC 3V backup cell input

X1–X2 Crystal inputs

V

CC

Power supply

V

SS

Ground

Real-Time Clock(RTC

)

Block Diagram

Pin Descriptions

MOT Bus type select input

MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCCfor Motorola timing or to VSSfor
Intel timing (see Table 1). The setting
should not be changed during system opera­tion. MOT is internally pulled low by a 30K

Ω

resistor.

AD0–AD7Multiplexed address/data

input/output

The bq3285EC/LC bus cycle consists of two
phases: the address phase and the data­transfer phase. The address phase pre­cedes the data-transfer phase. During the
address phase, an address placed on
AD0–AD7and EXTRAM is latched into the
bq3285EC/LC on the falling edge of the AS
signal. During the data-transfer phase of
the bus cycle, the AD0–AD7pins serve as a
bidirectional data bus.

AS Address strobe input

AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad­dress on AD0–AD7and EXTRAM. This de­multiplexing process is independent of the
CS signal. For DIP and SOIC packages
with MOT = VSS, the AS input is provided a
signal similar to ALE in an Intel-based sys­tem.

2

bq3285EC/LC

Bus

Type

MOT

LevelDSEquivalent

R/W

EquivalentASEquivalent

Motorola V

CC

DS,E,or

Φ

2

R/W

AS

Intel V

SS

RD,
MEMR,or
I/OR

WR,
MEMW,or
I/OW

ALE

Table 1. Bus Setup

BD328501.eps

P

Bus

I/F

µ

Power-

Fail

Control

Storage Registers

(114 Bytes)

User Buffer

(14 Bytes)

V

OUT

Clock/Calendar, Alarm

and Control Bytes

Time­Base

Oscillator

Control/Status

Registers

÷ 8 ÷ 64 ÷ 64

16 1 MUX

:

Interupt

Generator

Control/Calendar

Update

V

CC

DS

AD0–AD

7

CS

MOT

32K

INT

X

1

X

2

3

4

RST

R/W

AS

Storage Registers

(128 Bytes)

RCL

EXTRAM

Write
Protect

CS

BC

32K

Driver

July 1996

DS Data strobe input

When MOT = VCC, DS controls data trans­fer during a bq3285EC/LC bus cycle. Dur­ing a read cycle, the bq3285EC/LC drives
the bus after the rising edge on DS. During
a write cycle, the falling edge on DS is used
to latch write data into the chip.

When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.

R/W

Read/write input

When MOT = VCC, the level on R/W identi­fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.

When MOT = VSS, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel­based system. The rising edge on R/W
latches data into the bq3285EC/LC.

CS Chip select input

CS should be driven low and held stable
during the data-transfer phase of a bus cy­cle accessing the bq3285EC/LC.

INT Interrupt request output

INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, connect INT
through a resistor to a power supply other
than VCC. INT is asserted low when any
event flag is set and the corresponding
event enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).

32K 32.768 kHz output

32K provides a buffered 32.768 kHz output.
The frequency remains on and fixed at

32.768kHz as long as VCCis valid.

EXTRAM Extended RAM enable

Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30k

Ω

pull-down resistor. To access the RTC regis­ters,EXTRAM must be low.

RCL

RAM clear input

A low level on the RCL pin causes the con­tents of each of the 242 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCC. Us­ing RAM clear does not affect the battery
load. This pin is connected internally to a
30kΩpull-up resistor.

BC 3V backup cell input

BC should be connected to a 3V backup cell
for RTC operation and storage register non­volatility in the absence of system power.
When VCCslews down past VBC(3V typi­cal), the integral control circuitry switches
the power source to BC. When VCCreturns
above VBC, the power source is switched to
VCC.

Upon power-up, a voltage within the V

BC

range must be present on the BC pin for
the oscillator to start up.

RST Reset input

The bq3285EC/LC is reset when RST is
pulled low. When reset, INT becomes high
impedance, and the bq3285EC/LC is not ac­cessible. Table 4 in the Control/Status Reg­isters section lists the register bits that are
cleared by a reset.

Reset may be disabled by connecting RST
to VCC. This allows the control bits to re­tain their states through power­down/power-upcycles.

X1–X2 Crystal inputs

The X1–X2 inputs are provided for an ex­ternal 32.768kHz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci­tance. A trimming capacitor may be neces­sary for extremely precise time-base gen­eration.

In the absence of a crystal, a 32.768kHz
waveformcan befed intothe X1input.

3

bq3285EC/LC

July 1996

Functional Description

Address Map

The bq3285EC/LC provides 14 bytes of clock and con­trol/status registers and 242 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq3285EC/LC.

Update Period

The update period for the bq3285EC/LC is one second.
The bq3285EC/LC updates the contents of the clock and
calendar locations during the update cycle at the end of

each update period (see Figure 2). The alarm flag bit
may also be set during the update cycle.

The bq3285EC/LC copies the local register updates into
the user buffer accessed by the host processor. When a 1
is written to the update transfer inhibit bit (UTI) in reg­ister B, the user copy of the clock and calendar bytes re­mains unchanged, while the local copy of the same bytes
continues to be updated every second.

The update-in-progress bit (UIP) in register A is set
t

BUC

time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.

4

Figure 1. Address Map

Figure 2. Update Period Timing and UIP

bq3285EC/LC

July 1996

Programming the RTC

The time-of-day, alarm, and calendar bytes can be writ­ten in either the BCD or binary format (see Table 2).

These steps may be followed to program the time, alarm,
and calendar:

1. Modify the contents of register B:
a. Writea1totheUTIbittoprevent trans-

fers between RTC bytes and user buffer.

b. Write the appropriate value to the data

format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.

c. Write the appropriate value to the hour

format (HF) bit.

2. Write new values to all the time, alarm, and
calendar locations.

3. Clear the UTI bit to allow update transfers.

On the next update cycle, the RTC updates all 10 bytes
in the selected format.

5

bq3285EC/LC

Address RTC Bytes

Range

Decimal Binary

Binary-Coded

Decimal

0 Seconds 0–59 00H–3BH 00H–59H
1 Seconds alarm 0–59 00H–3BH 00H–59H
2 Minutes 0–59 00H–3BH 00H–59H
3 Minutes alarm 0–59 00H–3BH 00H–59H

4

Hours, 12-hour format 1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours, 24-hour format 0–23 00H–17H 00H–23H

5

Hours alarm, 12-hour format 1–12

01H–OCH AM;

81H–8CH PM

01H–12H AM;

81H–92H PM

Hours alarm, 24-hour format 0–23 00H–17H 00H–23H
6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H
7 Day of month 1–31 01H–1FH 01H–31H
8 Month 1–12 01H–0CH 01H–12H
9 Year 0–99 00H–63H 00H–99H

Table 2. Time,Alarm, and Calendar Formats

July 1996

32kHz Output

The bq3285EC/LC provides for a 32.768kHz output. For
the bq3285EC,the output is always active whenever V

CC

is valid (V

PFD+tCSR

). The bq3285EC output is not af­fected by the bit settings in Register A. Time-keeping
aspects, however, still require setting OS0-OS2. The
bq3285LC output is active when the oscillator is turned
on by setting the OSC0-OSC2 bits in Register A.

Interrupts

The bq3285EC/LC allows three individually selected in­terrupt events to generate an interrupt request. These
three interrupt events are:

n

The periodic interrupt, programmable to occur once
every 122µs to 500ms.

n

The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.

n

The update-ended interrupt, which occurs at the end
of each update cycle.

Each of the three interrupt events is enabled by an indi­vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre­sponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT

high-impedance.

Two methods can be used to process bq3285EC/LC in­terrupt events:

n

Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.

n

Do not enable the interrupts and use a polling
routine to periodically check the status of the flag
bits.

The individual interrupt sources are described in detail
in the following sections.

6

bq3285EC/LC

Register A Bits Periodic Interrupt

OSC2 OSC1 OSC0 RS3 RS2 RS1 RS0 Period Units

0100000None
0100001 3.90625 ms
0100010 7.8125 ms
0100011 122.070

µ

s

0100100 244.141

µ

s

0100101 488.281

µ

s

0100110 976.5625

µ

s
0100111 1.95315 ms
0101000 3.90625 ms
0101001 7.8125 ms
0101010 15.625 ms
0101011 31.25 ms
0101100 62.5 ms
0101101 125 ms
0101110 250 ms
0101111 500 ms

011XXXX

same as above defined

by RS3–RS0

Table 3. Periodic Interrupt Rate

July 1996

PeriodicInterrupt

If the periodic interrupt event is enabled by writing a 1
to the periodic interrupt enable bit (PIE) in register C,
an interrupt request is generated once every 122µsto
500ms. The period between interrupts is selected with
bits RS3-RS0 in register A (see Table3).

Alarm Interrupt

The alarm interrupt is active in battery-backup mode,
providing a “wake-up” capability. During each update
cycle, the RTC compares the hours, minutes, and sec­onds bytes with the three corresponding alarm bytes. If
a match of all bytes is found, the alarm interrupt event
flag bit, AF in register C, is set to 1. If the alarm event
is enabled, an interrupt request is generated.

An alarm byte may be removed from the comparison by
setting it to a “don't care” state. An alarm byte is set to
a “don't care” state by writinga1toeachofitstwo
most-significant bits. A “don't care” state may be used to
select the frequency of alarm interrupt events as follows:

n

If none of the three alarm bytes is “don't care,” the
frequency is once per day, when hours, minutes, and
seconds match.

n

If only the hour alarm byte is “don't care,” the
frequency is once per hour, when minutes and
seconds match.

n

If only the hour and minute alarm bytes are “don't
care,” the frequency is once per minute, when seconds
match.

n

If the hour, minute, and second alarm bytes are
“don't care,” the frequency is once per second.

Update Cycle Interrupt

The update cycle ended flag bit (UF) in register C is set to
a 1 at the end of an update cycle. If the update interrupt
enable bit (UIE) of register B is 1, and the update transfer
inhibit bit (UTI) in register B is 0, then an interrupt re­quest is generated at the end of each update cycle.

Accessing RTC bytes

The EXTRAM pin must be low to access the RTC regis­ters. Time and calendar bytes read during an update
cycle may be in error. Three methods to access the time
and calendar bytes without ambiguity are:

n

Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).

n

Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of t

BUC

time to access the clock bytes (see Figure 3).

n

Use the periodic interrupt event to generate
interrupt requests every tPItime, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2+t

BUC

time to access the clock bytes (see Figure 3).

Oscillator Control

When power is first applied to the bq3285LC and VCCis
above V

PFD

, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on
but keeps the frequency divider disabled. Any other pat­tern to these bits keeps the oscillator off. A pattern of
010 must be set for the bq3285EC/LC to keep time in
battery backup mode.

7

bq3285EC/LC

Figure 3. Update-Ended/Periodic Interrupt Relationship

July 1996

Power-Down/Power-Up Cycle

The bq3285EC and bq3285LC power-up/power-down cy­cles are different. The bq3285LC continuously monitors
VCCfor out-of-tolerance. During a power failure, when
VCCfalls below V

PFD

(2.53V typical), the bq3285LC write­protects the clock and storage registers. The power source
is switched to BC when VCCis less than V

PFD

and BC is

greater than V

PFD

, or when VCCis less than VBCand V

BC

is less than V

PFD

. RTC operation and storage data are
sustained by a valid backup energy source. When VCCis
above V

PFD

, the power source is VCC. Write-protection con-

tinues for t

CSR

time after VCCrises above V

PFD

.

The bq3285EC continuously monitors V

CC

for out-of­tolerance. During a power failure, when VCCfalls below
V

PFD

(4.17V typical), the bq3285EC write-protects the
clock and storage registers. When VCCis below VBC(3V
typical), the power source is switched to BC. RTC opera­tion and storage data are sustained by a valid backup
energy source. When VCCis above VBC, the power
source is VCC. Write-protection continues for t

CSR

time

after VCCrises above V

PFD

.

Control/Status Registers

The four control/status registers of the bq3285EC/LC
are accessible regardless of the status of the update cy­cle (see Table4).

Register A

Register A programs:

n

The frequency of the periodic event rate.

n

Oscillator operation.

n

Time-keeping

Register A provides:

n

Status of the update cycle.

RS0–RS3 - Frequency Select

These bits select the periodic interrupt rate, as shown in
Table3.

OS0–OS2 - Oscillator Control

These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op­eration by turning on the oscillator and enabling the fre­quency divider. This pattern must be set to turn the os­cillator on for the bq3285LC and to ensure that the
bq3285EC/LC will keep time in battery-backup mode. A
pattern of 11X turns the oscillator on, but keeps the fre­quency divider disabled. When 010 is written, the RTC
begins its first update after 500ms.

UIP - Update Cycle Status

This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.

8

bq3285EC/LC

Register A Bits

76543210

UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0

76543210

----RS3RS2RS1RS0

76543210

-OS2OS1OS0----

76543210

UIP-------

July 1996

Reg.

Loc.

(Hex) Read Write

Bit Name and State on Reset

7 (MSB) 6 5 4 3 2 1 0 (LSB)

A 0A Yes Yes

1

UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na
B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 - 0 DF na HF na DSE na
C 0C Yes No INTF 0 PF 0 AF 0 UF 0 - 0 - na - 0 - 0
D0DYesNoVRTna-0-0-0 - 0-0-0-0

Notes: na = not affected.

1. Except bit 7.

Table 4. Control/Status Registers