Texas Instruments BQ2203ASNTR, BQ2203ASN, BQ2203APN Datasheet

Features

ä

Power monitoring and switching
for nonvolatile control of SRAMs

ä

Write-protect control

ä

Battery-low and battery-fail indi­cators

ä

Reset output for system power-on
reset

ä

Input decoder for control of up to
2 banks of SRAM

ä

3-volt primary cell input

ä

3-volt rechargeable battery in­put/output

General Description

The CMOS bq2203A SRAM Nonvolatile
Controller With Battery Monitor pro­vides all the necessary functions for con­verting one or two banks of standard
CMOS SRAM into nonvolatile
read/write memory. The bq2203A is
compatible with the Personal Computer
Memory Card International Association
(PCMCIA) recommendations for
battery-backed static RAM memory
cards.

A precision comparator monitors the 5V
V

CC

input for an out-of-tolerance condi­tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect
banks of SRAM.

Power for the external SRAMs is
switched from the VCCsupply to the
battery-backup supply as VCCde­cays. On a subsequent power-up, the
V

OUT

supply is automatically
switched from the backup supply to
the VCCsupply. The external SRAMs
are write-protected until a power­valid condition exists. The reset out­put provides power-fail and power-on
resets for the system. The battery
monitor indicates battery-low and
battery-fail conditions.

During power-valid operation, the
input decoder selects one of two
banks of SRAM.

1

1

PN220301.eps

16-Pin Narrow DIP or SOIC

2

3

4

5

6

7
8

16

15

14

13

12

11

10

9

V

CC

BC

S

CE

CE

CON1

CE

CON2

BCL

RST
NC

V

OUT
BC

P

NC

A

BCF

NC

THS
V

SS

bq2203A

Nov.1994 B

Pin Connections

Two banks of CMOS static RAM can be battery-backed us­ing the V

OUT

and the conditioned chip-enable output pins
from the bq2203A. As the voltage input VCCslews down
during a power failure, the two conditioned chip-enable
outputs, CE

CON1

and CE

CON2

, are forced inactive

independent of the chip-enable input CE.
This activity unconditionally write-protects external SRAM

as V

CC

falls to an out-of-tolerance threshold V

PFD.VPFD

is
selected by the threshold select input pin, THS. If THS is
tied to VSS, the power-fail detection occurs at 4.62V typical
for 5% supply operation.

If THS is tied to VCC, power-fail detection occurs at

4.37V typical for 10% supply operation. The THS pin
must be tied to VSSor VCCfor proper operation.

If a memory access is in process to any of the two exter­nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t

WPT

(150µs maximum), the two chip-enable
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.

Functional Description

NV Controller With Battery Monitor

Pin Names

V

OUT

Supply output
RST Reset output
THS Threshold select input
CE chip-enable active low input
CE

CON1

, Conditioned chip-enable outputs

CE

CON2

A Bank select input
BCF Battery fail push-pull output
BCL Battery low push-pull output
BC

P

3V backup supply input
BC

S

3V rechargeable backup supply input/output
NC No connect
V

CC

5-volt supply input
V

SS

Ground

As the supply continues to fall past V

PFD

, an internal

switching device forces V

OUT

to the external backup en-

ergy source. CE

CON1

and CE

CON2

are held high by the

V

OUT

energy source.

During power-up, V

OUT

is switched back to the 5V sup­ply as VCCrises above the backup cell input voltage
sourcing V

OUT

. Outputs CE

CON1

and CE

CON2

are held

inactive for time t

CER

(120ms maximum) after the

power supply has reached V

PFD

, independent of the CE

input,toallowforprocessorstabilization.
During power-valid operation, the CE

input is passed

through to one of the two CE

CON

outputs with a propaga­tion delay of less than 10ns. The CE input is output on
one of the two CE

CON

output pins depending on the level

of bank select input A,asshownintheTruthT able .
Bank select input A is usually tied to a high-order ad-

dress pin so that a large nonvolatile memory can be de­signed using lower-density memory devices. Nonvolatil­ity and decoding are achieved by hardware hookup as
shown in Figure 1.

The reset output (RST) goes active within t

PFD

(150µs

maximum) after V

PFD,

and remains active for a mini­mum of 40ms (120ms maximum) after power returns
valid. The RST output can be used as the power-on re­set for a microprocessor. Access to the external RAM
may begin when RST returns inactive.

Energy Cell Inputs—BCP,BC

S

Two backup energy source inputs are provided on the
bq2203A—a primary cell BC

P

and a secondary cell BCS.
The primary cell input is designed to accept any 3V pri­mary battery (non-rechargeable), typically some type of
lithium chemistry.If a primary cell is not to be used, the
BCPpin should be tied to VSS. The secondary cell input
BCSis designed to accept constant-voltage current­limited rechargeable cells.

During normal 5V power valid operation, 3.3V typical is out­put on the BC

S

pin and is current-limited internally . Al­though this charging method can be used with various 3V
secondary cells, it is specifically designed for a Panasonic VL
(vanadium-lithium) series of rechargeable cells.

2

FG220301.eps

CE
BC

P

THS
V

SS

V

OUT

bq2203A

V

CC

CE

CMOS
SRAM

V

CC

5V

From Address

Decoder

CE

CON2

BC

S

CE

CON1

A

RST

V

CC

CE

CMOS
SRAM

To Microprocessor

3V Secondary
Cell

3V Primary

Cell

BCL

BCF

Figure 1. Hardware Hookup (5% Supply Operation)

Nov.1994 B

bq2203A

If a secondary cell is not to be used, the BCSpin must be
tied directly to VSS.

V

CC

falling below V

PFD

starts the comparison of BC

S

and BCP. The BC input comparison continues until V

CC

rises above VSO. Power to V

OUT

begins with BCSand
switches to BCPonly when BCSis less than BCPminus
V

BSO

. The controller alternates to the higher BC voltage
when the difference between the BC input voltages is
greater than V

BSO

. Alternating the backup batteries al­lows one-at-a-time battery replacement and efficient use
of both backup batteries.

To prevent battery drain when there is no valid data to
retain, V

OUT

,CE

CON1

, and CE

CON2

are internally iso-

lated from BCPand BCSby either of two methods:

■

Initial connection of a battery to BCPor BCS(V

CC

grounded) or

■

Presentation of an isolation signal on CE.

A valid isolation signal requires CE

low as VCCcrosses

both V

PFD

and VSOduring a power-down. See Figure

2. Between these two points in time, CE must be
brought to V

CC

*

(0.48 to 0.52) and held for at least 700ns.

The isolation signal is invalid if CE exceeds V

CC

*

0.54 at

any point between VCCcrossing V

PFD

and VSO.

The isolation function is terminated and the appropriate
battery is connected to V

OUT

,CE

CON1

, and CE

CON2

by

powering VCCup through V

PFD

.

Battery Monitor—BCL, BCF

As VCCrises past V

PFD

, the battery voltage on BCPis
compared with a dual-voltage reference. The result of
this comparison is latched internally, and output after
tBCwhen VCCrises past V

PFD

. If the battery voltage on
BCPis below VBL, then BCL is asserted low. If the bat­tery is below VBF, then BCL and BCF are asserted low.
The results of this comparison remain latched until V

CC

falls below V

PFD

.

3

TD220101.eps

V

CC

CE

V

PFD

V

SO

0.5 V

CC

700ns

Figure 2. Battery Isolation Signal

Truth Table

Input Output

CE

ACE

CON1

CE

CON2

HXHH
LLLH
LHHL

Nov.1994 B

bq2203A

4

Recommended DC Operating Conditions (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

Supply voltage

4.75 5.0 5.5 V THS = V

SS

4.50 5.0 5.5 V THS = V

CC

V

BCP

Backup cell input voltage

2.0 - 4.0 V VCC<V

BC

V

BCS

2.0 - 4.0 V VCC<V

BC

V

SS

Supply voltage 0 0 0 V

V

IL

Input low voltage -0.3 - 0.8 V

V

IH

Input high voltage 2.2 - VCC+ 0.3 V

THS Threshold select -0.3 - VCC+ 0.3 V

Note: Typical values indicate operation at TA= 25°C, VCC=5V.

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

V

CC

DC voltage applied on VCCrelative to V

SS

-0.3 to +7.0 V

V

T

DC voltage applied on any pin excluding V

CC

relative to V

SS

-0.3 to +7.0 V V

T

≤

V

CC

+ 0.3

T

OPR

Operating temperature

0 to 70 °C Commercial

-40 to +85 °C “N” Industrial

T

STG

Storage temperature -55 to +125 °C

T

BIAS

Temperature under bias -40 to +85 °C

T

SOLDER

Soldering temperature 260 °C For 10 seconds

I

OUT

V

OUT

current 200 mA

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo­sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

Nov.1994 B

bq2203A