Texas Instruments BQ2202SNTR, BQ2202SN-NTR, BQ2202SN-N, BQ2202SN, BQ2202PN-N Datasheet

Features

ä

Power monitoring and switching
for nonvolatile control of SRAMs

ä

Write-protect control

ä

Input decoder allows control of
up to 2 banks of SRAM

ä

3-volt primary cell input

ä

3-volt rechargeable battery in­put/output

ä

Reset output for system power-on
reset

ä

Less than 10ns chip enable
propagation delay

ä

5% or 10% supply operation

General Description

The CMOS bq2202 SRAM Nonvolatile
Controller With Reset provides all the
necessary functions for converting one
or two banks of standard CMOS
SRAM into nonvolatile read/write
memory.

A precision comparator monitors the
5V V

CC

input for an out-of-tolerance
condition. When out-of-tolerance is
detected, the two conditioned
chip-enable outputs are forced inac­tive to write-protect both banks of
SRAM.

Power for the external SRAMs is
switched from the VCCsupply to the
battery-backup supply as VCCde­cays. On a subsequent power--up, the
V

OUT

supply is automatically
switched from the backup supply to
the VCCsupply. The external SRAMs
are write-protected until a power­valid condition exists. The reset out­put provides power-fail and power-on
resets for the system.

During power-valid operation, the
input decoder selects one of two
banks of SRAM.

1

Pin Names

V

OUT

Supply output

RST

Reset output
THS Threshold select input
CE

Chip enable active low input
CE

CON1

, Conditioned chip enable outputs

CE

CON2

A Bank select input
BC

P

3V backup supply input
BC

S

3V rechargeable backup supply input/output
NC No connect
V

CC

+5 volt supply input
V

SS

Ground

Two banks of CMOS static RAM can be battery-backed
using the V

OUT

and conditioned chip-enable output pins
from the bq2202. As the voltage input VCCslews down
during a power failure, the two conditioned chip enable
outputs, CE

CON1

and CE

CON2

, are forced inactive

independent of the chip enable input CE.
This activity unconditionally write-protects external

SRAM as V

CC

falls to an out-of-tolerance threshold

V

PFD.VPFD

is selected by the threshold select input pin,
THS. If THS is tied to VSS, the power-fail detection oc­curs at 4.62V typical for 5% supply operation.

If THS is tied to V

CC

, power-fail detection occurs at

4.37V typical for 10% supply operation. The THS pin
must be tied to VSSor VCCfor proper operation.

If a memory access is in process to any of the two exter­nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t

WPT

(150µsec maximum), the two chip en­able outputs are unconditionally driven high, write­protecting the controlled SRAMs.

SRAM NV Controller With Reset

bq2202

Sept. 1997D

1

PN220201.eps

16-Pin Narrow DIP or SOIC

2

3

4

5

6

7
8

16

15

14

13

12

11

10

9

V

CC

BC

S
CE

CE

CON1
CE

CON2
NC

RST
NC

V

OUT
BC

P

NC

A

NC

NC

THS
V

SS

Functional Description

Pin Connections

As the supply continues to fall past V

PFD

, an internal

switching device forces V

OUT

to the internal backup en-

ergy source. CE

CON1

and CE

CON2

are held high by the

V

OUT

energy source.

During power-up, V

OUT

is switched back to the 5V sup­ply as VCCrises above the backup cell input voltage
sourcing V

OUT

. Outputs CE

CON1

and CE

CON2

are held

inactive for time t

CER

(120ms maximum) after the

power supply has reached V

PFD

, independent of the CE

input,toallowforprocessorstabilization.
During power-valid operation, the CE

input is passed

through to one of the two CE

CON

outputs with a propa­gation delay of less than 10ns. The CE input is output on
one of the two CE

CON

output pins; depending on the
level of bank select input A, as shown in the Truth Ta­ble.

Bank select input A is usually tied to a high-order ad­dress pin so that a large nonvolatile memory can be de­signed using lower-density memory devices.Nonvolatility
and decoding are achieved by hardware hookup as shown
in Figure 1.

The reset output (RST) goes active within t

PFD

(150µsec

maximum) after V

PFD,

and remains active for a minimum
of 40ms (120ms maximum) after power returns valid. The
RST output can be used as the power-on reset for a micro­processor . Access to the external RAM may begin when
RST returns inactive.

Energy Cell Inputs—BCP,BC

S

Two backup energy source inputs are provided on the
bq2202—a primary cell BC

P

and a secondary cell BCS.
The primary cell input is designed to accept any 3V pri­mary battery (non-rechargeable), typically some type of
lithium chemistry.If a primary cell is not to be used, the
BCPpin should be grounded. The secondary cell input
BCSis designed to accept constant-voltage current­limited rechargeable cells.

During normal 5V power valid operation, 3.3V is output
on the BC

S

pin and is current-limited internally.

2

FG220201.eps

V

CC

CE
BC

P

THS
V

SS

V

OUT

bq2202

V

CC

CE

CMOS
SRAM

5V

From Address

Decoder

CE

CON2

BC

S

RST

CE

CON1

A

V

CC

CE

CMOS
SRAM

To Microprocessor

Figure 1. Hardware Hookup (5% Supply Operation)

Sept. 1997D

bq2202

If a secondary cell is not to be used, the BCSpin must be
tied directly to VSS. If both inputs are used, during
power failure the V

OUT

and CE

CON

outputs are forced

high by the secondary cell so long as it is greater than

2.5V. Only the secondary cell is loaded by the data reten­tion current of the SRAM until the voltage at the BC

S

pin falls below 2.5V. When and if the voltage at BC

S

falls below 2.5V, an internal isolation switch automati­cally transfers the load from the secondary cell to the
primary cell.

To prevent battery drain when there is no valid data to
retain, V

OUT

,CE

CON1

, and CE

CON2

are internally iso-

lated from BCPand BCSby either:

■

Initial connection of a battery to BCPor BCSor

■

Presentation of an isolation signal on CE.

A valid isolation signal requires CE

low as VCCcrosses

both V

PFD

and VSOduring a power-down. See Figure

2. Between these two points in time, CE must be
brought to V

CC ∗

(0.48 to 0.52) and held for at least

700ns. The isolation signal is invalid if CE exceeds V

CC

*

0.54 at any point between VCCcrossing V

PFD

and VSO.

The battery is connected to V

OUT

,CE

CON1

, and

CE

CON2

immediately on subsequent application and

removal of VCC.

3

TD220201.eps

V

CC

CE

V

PFD

V

SO

0.5 V

CC

700ns

Figure 2. Battery Isolation Signal

Truth Table

Input Output

CE ACE

CON1

CE

CON2

HXHH
LLLH
LHHL

Sept. 1997D

bq2202