Texas Instruments 74AC11245PWLE, 74AC11245NT, 74AC11245DWR, 74AC11245DW, 74AC11245DBR Datasheet
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74AC11245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS010B – JULY 1987 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
3-State Outputs Drive Bus Lines Directly
D
Flow-Through Architecture Optimizes
PCB Layout
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, and Standard Plastic 300-mil
DIPs (NT)
description
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements.
The device allows noninverted data transmission from the A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to
disable the device so that the buses are effectively isolated.
The 74AC11245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
OUTPUT
ENABLE
OE
DIRECTION
CONTROL
DIR
OPERATION
L L B data to A bus
L H A data to B bus
H X Isolation
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
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2
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4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
DIR
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
OE
DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
74AC11245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS010B – JULY 1987 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
B8
B7
B6
B5
B4
B3
B2
B1
14
15
16
17
20
21
22
23
A8
A7
A6
A5
A4
A3
A2
A1
DIR
OE
12
11
10
9
4
3
2
1
24
13
2
1
3 EN2 [AB]
3 EN1 [BA]
G3
logic diagram (positive logic)
A8
A7
A6
A5
A4
A3
A2
A1
DIR
B8
B7
B6
B5
B4
B3
B2
B1
OE
14
15
16
17
20
21
22
23
13
12
11
10
9
4
3
2
1
24
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