Texas Instruments 74AC11244DBR, 74AC11244DBLE, 74AC11244PWR, 74AC11244PWLE, 74AC11244NT Datasheet
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74AC11244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS ) 1-µm Process
D
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D
Flow-Through Architecture Optimizes PCB
Layout
D
Center-Pin VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, and Standard Plastic DIPs (NT)
description
The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and
density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The
device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-enable (OE
) inputs.
When OE
is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The 74AC11244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each driver)
INPUTS
OUTPUT
OE A
Y
L H H
L LL
HXZ
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Y1
1Y2
1Y3
1Y4
GND
GND
GND
GND
2Y1
2Y2
2Y3
2Y4
1OE
1A1
1A2
1A3
1A4
V
CC
V
CC
2A1
2A2
2A3
2A4
2OE
DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
74AC11244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
1OE
23
1A1
22
1A2
21
1A3
20
1A4
EN
24
1Y1
1
1Y2
2
1Y3
3
1Y4
4
2OE
17
2A1
16
2A2
15
2A3
14
2A4
EN
13
2Y1
9
2Y2
10
2Y3
11
2Y4
12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
23
22
21
20
13
17
16
15
14
12
11
10
9
4
3
2
1
1A1
1A2
1A3
1A4
1Y1
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
1OE
2OE
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
74AC11244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
V
CC
Supply voltage 3 5 5.5 V
VCC = 3 V 2.1
V
IH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V 3.85
VCC = 3 V 0.9
V
IL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V 1.65
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
VCC = 3 V –4
I
OH
High-level output current
VCC = 4.5 V –24
mA
VCC = 5.5 V –24
VCC = 3 V 12
I
OL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V 24
∆t/∆v Input transition rise or fall rate 0 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX
MIN
MAX
UNIT
3 V 2.9 2.9
IOH = –50 µA
4.5 V 4.4 4.4
5.5 V 5.4 5.4
V
OH
IOH = –4 mA 3 V 2.58 2.48
V
4.5 V 3.94 3.8
IOL = –24 mA
5.5 V 4.94 4.8
IOH = –75 mA
†
5.5 V 3.85
3 V 0.1 0.1
IOL = 50 µA
4.5 V 0.1 0.1
5.5 V 0.1 0.1
V
OL
IOL = 12 mA 3 V 0.36 0.44
V
4.5 V 0.36 0.44
I
OL
=
24 mA
5.5 V 0.36 0.44
IOL = 75 mA
†
5.5 V 1.65
I
I
VI = VCC or GND 5.5 V ±0.1 ±1 µA
I
OZ
VO = VCC or GND 5.5 V ±0.5 ±5 µA
I
CC
VI = VCC or GND, IO = 0 5.5 V 8 80 µA
C
i
VI = VCC or GND 5 V 4 pF
C
o
VO = VCC or GND 5 V 10 pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
74AC11244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX
MIN
MAX
UNIT
t
PLH
1.5 7.1 9.3 1.5 10.2
t
PHL
A
Y
1.5 6.3 8.6 1.5 9.5
ns
t
PZH
1.5 8 10.7 1.5 11.8
t
PZL
OE
Y
1.5 7.9 10.6 1.5 11.9
ns
t
PHZ
1.5 5.9 7.9 1.5 8.3
t
PLZ
OE
Y
1.5 7.2 9.4 1.5 9.9
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX
MIN
MAX
UNIT
t
PLH
1.5 4.9 6.7 1.5 7.3
t
PHL
A
Y
1.5 4.5 6.4 1.5 6.9
ns
t
PZH
1.5 5.4 7.7 1.5 8.5
t
PZL
OE
Y
1.5 5.4 7.6 1.5 8.5
ns
t
PHZ
1.5 5.2 7 1.5 7.3
t
PLZ
OE
Y
1.5 5.8 7.8 1.5 8.2
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
p
p
p
Outputs enabled
p
27
p
CpdPower dissipation capacitance per buffer/driver
Outputs disabled
C
L
= 50 pF,
f
= 1 MHz
9
pF
74AC11244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
50%
50%
50% 50%
[
V
CC
V
CC
0 V
50% V
CC
50% V
CC
V
OH
V
OL
0 V
50% V
CC
20% V
CC
50% V
CC
80% V
CC
[
0 V
V
CC
GND
Open
Input
Output
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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