Tektronix TCS101 Primary User

Instruction Manual

TCS101 SPI-3 and SPI-4.2 Bus Software Support

071-1171-01

www.tektronix.com

Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this public ation supercedes that in all previously published material. Specifications and price c hange privileges reserved.

Tektronix, Inc., P.O. Box 500, Beaverton, OR 97077

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

SOFTWARE WARRANTY

Tektronix warrants that the media on which this software product is furnished and the encoding of the programs on the media will be free from defects in materials and workmanship for a period of three (3) months from the date of shipment. If a medium or encoding proves defective during the warranty period, Tektronix will provide a replacement in exchange for the defective medium. Except as to the media on which this software product is furnished, this software product is provided “as is” without warranty of any kind, either express or implied. Tektronix does not warrant that the functions contained in this software product will meet Customer’s requirements or that the operation of the programs will be uninterrupted or error-free.

In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the warranty period. If Tektronix is unable to provide a replacement that is free from defects in materials and workmanship within a reasonable time thereafter, Customer may terminate the license for this software product and return this software product and any associated materials for credit or refund.

THIS WARRANTY IS GIVEN BY TEKTRONIX IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO REPLACE DEFECTIVE MEDIA OR REFUND CUSTOMER’S PAYMENT IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES.

Getting Started

Preface ix...................................................

Manual Conventions ix..............................................

Contacting Tektronix x.............................................

Support Package Descri ption 1--1.......................................

Disassembly Support 1--1..........................................

Triggering Support 1--2...........................................

Logic Analyzer Software Compatibility 1--2..............................

Logic Analyzer Configuration 1--2......................................

Module Requirements 1--2.........................................

Probe Requirements 1--3..........................................

Requirements and Restrictions 1--3......................................

Hardware Reset 1--4..............................................

Clock Rate 1--4..................................................

Setup/Hold Time Requirements 1--4.................................

Nonintrusive Acquisition 1--4......................................

Limitations of the Support 1--4.........................................

Connecting the Logic Analyzer to a Target System 1--5.....................

Labeling P6880 and P6860 Probes 1--5...................................

Operating Basics

Setting Up the Support 2--1.....................................

Installing the Support Software 2--1.....................................

Support Package Setups 2--2...........................................

Clocking Options 2--2................................................

SPI3_TX and SPI3_RX 2--2........................................

SPI4 and SPI4_LVTTL 2--3........................................

Acquiring and Viewing Disassembled Data 2--5....................

Acquiring Data 2--5..................................................

Changing How Data is Displayed 2--5...................................

Optional Display Selections 2--6....................................

Bus Specific Fields 2--6...........................................

Labels for Bus Cycles 2--9.............................................

Viewing Disassembled Data 2--11........................................

All Display Format in SPI3_TX and SPI3_RX 2--11.....................

Packet Display Format in SPI3_TX and SPI3_RX 2--11...................

All Display Format in SPI4 and SPI4_LVTTL 2--12......................

Packet & Control Display Format in SPI4 and SPI4_LVTTL 2--12..........

Packet Only Display Format in SPI4 and SPI4_LVTTL 2--13..............

Trigger Programs 2--15..........................................

Loading Trigger Programs 2--15.........................................

SPI-3 Trigger Programs 2--15........................................

SPI-4.2 Trigger Programs 2--16......................................

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Table of Contents

Reference

SPI-4.2 Setup/Hold Time Adjustments 2--17........................

SPI4 Configurations and Settings 2--18....................................

SPI4 AutoDeskew Setup 2--18......................................

SPI4_LVTTL Configurations and Settings 2--18............................

SPI4_LVTTL AutoDeskew Setup 2--18...............................

Channel Group Definitions 3--1..................................

Channel Groups 3--1.................................................

Symbol and Channel Assignment Tables 3--5......................

Symbol Tables 3--5..................................................

Channel Assignment Tables 3--9........................................

SPI3_TX Channel Group Assignments 3--9............................

SPI3_RX Channel Group Assignments 3--14............................

SPI4 and SPI4_LVTTL Channel Group Assignments 3--18................

EasyTrigger Channel Assignments 3--29...............................

Clock and Qualifier Channel Assignments 3--35.........................

Signals Required for Clocking and Disassembly 3--37....................

Signal Source To Probe Connections 3--39.................................

Connections for SPI3_TX Support 3--40...............................

Connections for SPI3_RX Support 3--42...............................

Connections for SPI4 and SPI4_LVTTL Supports 3--44...................

Signal Acquisition 3--49.........................................

Signal Acquisition in SPI-3 3--49.....................................

Signal Acquisition in SPI-4.2 3--50...................................

Specifications

Index

Specification Table 4--1...............................................

TCS101 SPI-3 and SPI-4.2 Bus Software Support

List of Figures

Table of Contents

Figure 2--1: Example of All display format for the SPI4

support package 2--12.......................................

Figure 2--2: Example of Packet & Control display format for the

SPI4 support package 2--13...................................

Figure 2--3: Example of Packet Only display format for the SPI4

support package 2--14.......................................

Figure 3--1: Sample of P6860 High-Density probe land footprint 3--40..

Figure 3--2: Sample of P6880 Differential probe land footprint 3--45....

Figure 3--3: Example of a timing diagram for the transmit bus with

clocking option “Active Cycles” selected 3--49...................

Figure 3--4: Example of a timing diagram for the receive bus with

clocking option “Active Cycles” selected 3--50...................

Figure 3--5: Example of a timing diagram for the SPI-4.2 bus 3--51.....

TCS101 SPI-3 and SPI-4.2 Bus Software Support

iii

Table of Contents

List of Tables

Table 1--1: Module requirements for the TCS101 product 1--3.......

Table 1--2: Probe requirements for the TCS101 product 1--3.........

Table 1--3: Setup/Hold time requirements for the TCS101

product 1--4..............................................

Table 2--1: Logic analyzer disassembly display options for SPI3_TX

and SPI3_RX support packages 2--6..........................

Table 2--2: Logic analyzer disassembly display options for SPI4 and

SPI4_LVTTL support packages 2--6..........................

Table 2--3: Bus specific fields for SPI3_TX and SPI3_RX support

packages 2--6.............................................

Table 2--4: Bus specific fields for SPI4 and SPI4_LVTTL support

packages 2--8.............................................

Table 2--5: Labels in Packet/Cell Details column for SPI3_TX and

SPI3_RX support packages 2--9..............................

Table 2--6: Labels in Packet/Cell Details column for SPI4 and

SPI4_LVTTL support packages 2 --10..........................

Table 2--7: Labels in FIFO Status column for SPI4 and

SPI4_LVTTL support packages 2 --10..........................

Table 3--1: SPI3_TX channel group names 3--1....................

Table 3--2: SPI3_RX channel group names 3--1....................

Table 3--3: SPI4 and SPI4_LVTTL channel group names 3--2........

Table 3--4: SPI3_TX_Ctrl group symbol table definitions 3--5........

Table 3--5: SPI3_TX_Trig_Ctrl group symbol table definitions 3--6...

Table 3--6: SPI3_TX Parity group symbol table definitions 3--6.......

Table 3--7: SPI3_RX_Ctrl group symbol table definitions 3--6........

Table 3--8: SPI3_RX_Trig_Ctrl group symbol table definitions 3--7...

Table 3--9: SPI3_RX Parity group symbol table definitions 3--8.......

Table 3--10: SPI4_Ctrl/SPI4_LVTTL_Ctrl group symbol table

definitions 3--8............................................

Table 3--11: Address group assignments for SPI3_TX support

package 3--10..............................................

Table 3--12: DAT group assignments for SPI3_TX support

package 3--10..............................................

Table 3--13: Control group assignments for SPI3_TX support

package 3--11..............................................

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Table of Contents

Table 3--14: DTPA group assignments for SPI3_TX support

package 3--12..............................................

Table 3--15: Misc group assignments for SPI3_TX support

package 3--12..............................................

Table 3--16: Trig_Control group assignments for SPI3_TX support

package 3--12..............................................

Table 3--17: Trig_DAT[7:0] group assignments for SPI3_TX

support package 3--13.......................................

Table 3--18: Trig_DAT[31:0] group assignments for SPI3_TX

support package 3--13.......................................

Table 3--19: DAT group assignments for SPI3_RX support

package 3--14..............................................

Table 3--20: Control group assignments for SPI3_RX support

package 3--16..............................................

Table 3--21: Trig_Control group assignments for SPI3_RX support

package 3--16..............................................

Table 3--22: Trig_DAT[7:0] group assignments for SPI3_RX support

package 3--16..............................................

Table 3--23: Trig_DAT[31:0] group assignments for SPI3_RX support

package 3--17..............................................

Table 3--24: $CTL group assignments for SPI4 and SPI4_LVTTL

support packages 3--19......................................

Table 3--25: $DAT0 group assignments for SPI4 and SPI4_LVTTL

support packages 3--19......................................

Table 3--26: $DAT1 group assignments for SPI4 and SPI4_LVTTL

support packages 3--20......................................

Table 3--27: $DAT2 group assignments for SPI4 and SPI4_LVTTL

support packages 3--20......................................

Table 3--28: $DAT3 group assignments for SPI4 and SPI4_LVTTL

support packages 3--20......................................

Table 3--29: $DAT4 group assignments for SPI4 and SPI4_LVTTL

support packages 3--21......................................

Table 3--30: $DAT5 group assignments for SPI4 and SPI4_LVTTL

support packages 3--21......................................

Table 3--31: $DAT6 group assignments for SPI4 and SPI4_LVTTL

support packages 3--21......................................

Table 3--32: $DAT7 group assignments for SPI4 and SPI4_LVTTL

support packages 3--22......................................

Table 3--33: $DAT8 group assignments for SPI4 and SPI4_LVTTL

support packages 3--22......................................

Table 3--34: $DAT9 group assignments for SPI4 and SPI4_LVTTL

support packages 3--22......................................

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Table of Contents

Table 3--35: $DAT10 group assignments for SPI4 and SPI4_LVTTL

support packages 3--23......................................

Table 3--36: $DAT11 group assignments for SPI4 and SPI4_LVTTL

support packages 3--23......................................

Table 3--37: $DAT12 group assignments for SPI4 and SPI4_LVTTL

support packages 3--23......................................

Table 3--38: $DAT13 group assignments for SPI4 and SPI4_LVTTL

support packages 3--24......................................

Table 3--39: $DAT14 group assignments for SPI4 and SPI4_LVTTL

support packages 3--24......................................

Table 3--40: $DAT15 group assignments for SPI4 and SPI4_LVTTL

support packages 3--24......................................

Table 3--41: $STAT0 group assignments for SPI4 support

package 3--25..............................................

Table 3--42: $STAT1 group assignments for SPI4 support

package 3--25..............................................

Table 3--43: DATA group assignments for SPI4 and SPI4_LVTTL

support packages 3--25......................................

Table 3--44: CTL[1:0] group assignments for SPI4 and SPI4_LVTTL

support packages 3--27......................................

Table 3--45: STAT group channel assignments for SPI4 support

package 3--27..............................................

Table 3--46: STAT group channel assignments for SPI4_LVTTL

support package 3--27.......................................

Table 3--47: STAT_A group channel assignments for SPI4 support

package 3--28..............................................

Table 3--48: STAT_B group channel assignments for SPI4 support

package 3--28..............................................

Table 3--49: SCLK group channel assignments for SPI4_LVTTL

support package 3--28.......................................

Table 3--50: CTL_TYPE_A group EasyTrigger channel assignments

for SPI4 and SPI4_LVTTL support packages 3--29..............

Table 3--51: CTL_TYPE_B group EasyTrigger channel assignments

for SPI4 and SPI4_LVTTL support packages 3--29..............

Table 3--52: CTL_TYPE_AB group EasyTrigger channel assignments

for SPI4 and SPI4_LVTTL support packages 3--30..............

Table 3--53: DAT_PORT_A group EasyTrigger channel assignments

for SPI4 and SPI4_LVTTL support packages 3--30..............

Table 3--54: DAT_PORT_B group EasyTrigger channel assignments

for SPI4 and SPI4_LVTTL support packages 3--31..............

Table 3--55: DAT_AB group EasyTrigger channel assignments for

SPI4 and SPI4_LVTTL support packages 3--31.................

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Table of Contents

Table 3--56: DAT_BA group EasyTrigger channel assignments for

SPI4 and SPI4_LVTTL support packages 3--32.................

Table 3--57: DAT_A group channel EasyTrigger assignments for

SPI4 and SPI4_LVTTL support packages 3--34.................

Table 3--58: DAT_B group EasyTrigger channel assignments for SPI4

and SPI4_LVTTL support packages 3--34......................

Table 3--59: Clock channel assignments for SPI3_TX support

package 3--35..............................................

Table 3--60: Qualifier channel assignments for SPI3_TX support

package 3--35..............................................

Table 3--61: Clock channel assignments for SPI3_RX support

package 3--36..............................................

Table 3--62: Qualifier channel assignments for SPI3_RX support

package 3--36..............................................

Table 3--63: Clock and qualifier channel assignments for SPI4

support package 3--36.......................................

Table 3--64: Clock and qualifier channel assignments for

SPI4_LVTTL support package 3--36...........................

Table 3--65: SPI-3 transmit signals required for clocking and

disassembly 3--37...........................................

T able 3--66: SPI-3 receive signals required for clocking and

disassembly 3--37...........................................

Table 3--67: SPI-4.2 signals required for clocking and disassembly

for SPI4 support package 3--37...............................

Table 3--68: SPI-4.2 signals required for clocking and disassembly

for SPI4_LVTTL support package 3-- 38........................

Table 3--69: Recommended pin assignments for a Mictor connector

(component side) 3--39.......................................

Table 3--70: Pin connections for SPI3_TX support package 3--40......

Table 3--71: Pin connections for SPI3_RX support package 3--42......

Table 3--72: Pin connections for SPI4 and SPI4_LVTTL support

packages (Probe#3) 3--45....................................

Table 3--73: Pin connections for SPI4 and SPI4_LVTTL support

packages (Probe#2) 3--46....................................

Table 3--74: Pin connections for SPI4 support package for FIFO

Status LVDS signals (Probe#1) 3--47...........................

Table 3--75: Pin connections for SPI4_LVTTL support package for

FIFO Status LVTTL signals (P6880) 3--47......................

Table 3--76: Pin connections for SPI4_LVTTL support package for

FIFO Status LVTTL signals (P6860) 3--48......................

T able 4--1: Electrical specifications 4--1...........................

TCS101 SPI-3 and SPI-4.2 Bus Software Support

vii

Table of Contents

viii

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Preface

This instruction manual contains specific information about the TCS101 software product for the SPI-3 and SPI-4.2 buses and is part of a set of information on how to operate this product on compatible Tektronix logic analyzers.

If you are familiar with operating bus support packages on the logic analyzer for which the TCS101 product was purchased, you will probably only need this instruction manual to set up and run the support.

If you are not familiar with operating bus support packages, you will need to supplement this instruction manual with information on basic operations to set up and run the support.

Information on basic operations of bus support packages is included with each product. Each logic analyzer includes basic information that describes how to perform tasks common to support packages on that platform. This information can be in the form of logic analyzer online help, an installation manual, or a user manual.

This manual provides detailed information on the following topics:

H Connecting the logic analyzer to the target system

Manual Conventions

H Setting up the logic analyzer to acquire data from the target system

H Acquiring and viewing disassembled data

This manual uses the following conventions:

H The term “disassembler” refers to the software that disassembles bus cycles

into packets and control information.

H The phrase “basic operations” refers to the logic analyzer online help, or the

user manual that covers the basic operations of the bus support.

H The phrase “logic analyzer” refers to the Tektronix logic analyzer for which

this product was purchased.

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Contacting Tektronix

Preface

Phone 1-800-833-9200*

Address Tektronix, Inc.

Department or name (if known) 14200 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 USA

Web site www.tektronix.com

Sales support 1-800-833-9200, select option 1*

Service support 1-800-833-9200, select option 2*

Technical support Email: techsupport@tektronix.com

1-800-833-9200, select option 3*

6:00 a.m. -- 5:00 p.m. Pacific time

* This phone number is toll free in North America. After office hours, please leave a

voice mail message. Outside North America, contact a Tektronix sales office or distributor; see the Tektronix web site for a list of offices.

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Getting Started

This section contains information on the TCS101 product and information on connecting your logic analyzer to your target system.

Support Package Description

The TCS101 product acquires, decodes and displays the SPI-3 and SPI-4.2 bus cycles. The support package allows you to acquire bus cycles with minimal impact on the environment of the system.

The TCS101 product contains four acquisition support packages that have their own setup software and disassemblers. A description of each support package is listed here.

H SPI3_TX, for the SPI-3 Transmit Interface

H SPI3_RX, for the SPI-3 Receive Interface

H SPI4, for the SPI-4.2 Transmit and Receive interfaces with LVDS FIFO

Status signals

Disassembly Support

H SPI4_LVTTL, for the SPI-4.2 Transmit and Receive interfaces with LVTTL

FIFO Status signals

The disassembler decodes transmit and receive bus information of SPI-3 and SPI-4.2 buses.

The SPI3_TX and SPI3_RX support packages acquire and decode bus behavior at each clock cycle or at active clock cycles (see page 2--3). For SPI4 and SPI4_LVTTL support packages, the bus behavior is acquired at all clock cycles and decoded.

The disassembler decodes data in the following stages.

H Packet related information — start of packet, end of packet, payload (packet

data), physical port address, packet continuation and packet error (DIP-4)

H Control information, Training, and Idle information

H FIFO Status decoding in SPI4 and SPI4_LVTTL with DIP-2

The payloads are indexed with byte counts corresponding to a port address, so that you can know how many bytes of data have been transmitted by or received at a port.

TCS101 SPI-3 and SPI-4.2 Bus Software Support

1-- 1

Getting Started

The ASCII characters corresponding to the payloads can be viewed by choosing “Decode Payload as ASCII” option (on pages 2--8 and 2--9) in the bus specific fields.

The SPI3_TX and SPI3_RX support packages display the calculated parity bit for each valid 8-bit or 32-bit data on the data bus.

After acquisition, the TCS101 product supports filtering based on the physical port address (see pages 2--7 and 2--8).

To use this support package efficiently refer to the following documents:

H System Packet Interface Level 3 (SPI-3): OC-48 System Interface for

Physical and Link Layer Devices {Optical Internetwork Forum, June 2000, OIF-SPI3-01.0}

H POS-PHY Level 3, Saturn Compatible Packet Over SONET Interface

Specification for Physical and Link Layer Devices {PMC -Sierra Inc., Issue 4: June 2000, PMC-1980495}

H System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface

for Physical and Link Layer Devices {Optical Internetwork Forum, January 2001, OIF-SPI4-02.0}

H POS-PHY Level 4, A Saturn Packet and Cell Interface Specification for

OC192 SONET/SDH and 10 Gigabit Ethernet {PMC-Sierra Inc., Issue 6: February 2001, PMC-1991635}

Triggering Support

The SPI3_TX and SPI3_RX support packages provide an EasyTrigger library to trigger on Port Address, control signals like Start -of-Packet and End-of-Packet, Erroneous Packet, and 8-bit or 32-bit Packet Data. The SPI4 and SPI4_LVTTL support packages provide an EasyTrigger library to trigger on control words and packet data.

Logic Analyzer Software Compatibility

The label on the bus support CD-ROM states which version of logic analyzer software this support package is compatible with.

Logic Analyzer Configuration

The TCS101 product allows a choice of required minimum module configurations.

Module Requirements

1-- 2 TCS101 SPI-3 and SPI-4.2 Bus Software Support

Table 1--1 shows the module requirements for the TCS101 product.

Getting Started

Table 1--1: Module requirements for the TCS101 product

Bus Module requirements Remarks

SPI-3 One module of :

TLA7xx logic analyzer module at 200 MHz — 68 channel and above

TLA6xx series logic analyzer at 200 MHz — 68 channel and above

TLA7Axx series logic analyzer at 120 MHz — 68 channel and above

SPI-4.2 One module of :

TLA7Axx logic analyzer module at 450 MHz — 102 channel and above

* You cannot use a single 102 or 136 channel module for loading the TX and RX

interfaces together as the SPI3_TX and SPI3_RX support packages assume independent clocks.

Minimum of one 68-channel logic analyzer module each for Transmit and Receive interfaces

Minimum of one 102 channel TLA7Axx module Two 102 channel modules are required for a Transmit and Receive pair

Probe Requirements

Table 1--2 shows the probe requirements for the TCS101 product.

Table 1--2: Probe requirements for the TCS101 product

Bus

SPI-3 Two P6434 or P6860 probes -

SPI-4.2 Two or three P6880 probes Two P6880 probes are

Requirements and Restrictions

Review the electrical specifications in the Specifications section on page 4--1 in this manual as they pertain to your target system, as well as the following descriptions of TCS101 product requirements and restrictions.

Probes for TX or RX interface

Description

required for data One optional probe for FIFO status — either a P6880 probe for LVDS or LVTTL Status or a P6860 probe for LVTTL Status

TCS101 SPI-3 and SPI-4.2 Bus Software Support

1-- 3

Getting Started

Hardware Reset

Clock Rate

FIFO Status Decoding

Setup/Hold Time

Requirements

If a hardware reset occurs in your target system during an acquisition, the application disassembler might acquire an invalid sample.

The TCS101 product can acquire data from the SPI-3 bus operating at 104 MHz. The TCS101 product can acquire data from the SPI-4.2 bus operating at

350 MHz

In the SPI4 and SPI4_LVTTL support packages, the FIFO Status decoding is displayed correctly only under the following conditions.

H Port Address Filter option is set to “No” in the disassembly properties tab

H Show option is set to “All” in the disassembly properties tab

H Filter Idles option is set to “Is False” for the EasyTrigger that was used to

acquire the data

Table 1--3 lists the setup/hold time requirements for the different support packages. For correct acquisition, the target system must provide a data valid window meeting these requirements.

Table 1--3: Setup/Hold time requirements for the TCS101 product

Support package name

SPI3_TX, SPI3_RX TLA6xx/7xx 2.5 ns 0ns

SPI3_TX, SPI3_RX TLA7Axx 750 ps 0ps

SPI4, SPI4_LVTTL TLA7Axx 750 ps 0ps

For SPI-4.2 supports, some of the target systems may require an adjustment in the Setup/Hold time settings of logic analyzer to match their data valid window.

Nonintrusive Acquisition

The TCS101 product acquires bus cycles nonintrusively from the target system. That is, the TCS101 product does not intercept, modify, or present signals back to the target system.

Limitations of the Support

The TCS101 product does not decode the embedded protocols.

Logic analyzer/ module

Setup time Hold time

1-- 4

Specification at time of printing. Contact your Tektronix sales representative for current information on the fastest bus supported.

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Getting Started

Connecting the Logic Analyzer to a Target System

You can use the channel probes and clock probes to make the connections between the logic analyzer and your target system.

To connect the probes to the SPI-3 and SPI-4.2 bus signals described in the TCS101 product channel assignment to the target system, follow the steps:

1. Power off your target system. It is not necessary to power off the logic

analyzer.

CAUTION. To prevent static damage, handle the target systems, probes, and the logic analyzer module in a static-free environment. Static discharge can damage these components.

Always wear a grounding wrist strap, heel strap, or similar device while handling the target system.

2. Place the target system on a horizontal, static-free surface.

3. Use Tables 3--69 through 3--76 starting on page 3--39 to connect the channel

probes to the SPI-3 and SPI-4.2 signals in the target system.

Labeling P6880 and P6860 Probes

The TCS101 product relies on the channel mapping and labeling scheme for the P6880 and P6860 Probes. Apply labels, using the instructions described in the P6810, P6860, and P6880 Logic Analyzer Probes Instruction manual.

TCS101 SPI-3 and SPI-4.2 Bus Software Support

1-- 5

Getting Started

1-- 6

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Operating Basics

Setting Up the Support

This section provides information on how to set up the software support and covers the following topics:

H Installing the support software

H Support package setups

H Clocking options

The information in this section pertains to the specific operations and functions of the TCS101 product on a Tektronix logic analyzer for which the support can be used.

Before you acquire and display disassembled data, you need to load the support package and specify the setups for clocking and triggering as described in the logic analyzer online help under “Microprocessor support”. The support package provides default values for each of these setups, but you can change the setups as needed.

Installing the Support Software

NOTE. Before you install any software, it is recommended you verify that the bus support software is compatible with the logic analyzer software.

To install the TCS101 product on your Tektronix logic analyzer, follow these steps:

1. Insert the CD-ROM in the CD drive.

2. Click the Windows Start button, point to Settings, and click Control Panel.

3. In the Control Panel window, double-click Add/Remove Programs.

4. Follow the instructions on the screen for installing the software from the

CD-ROM. A copy of the instruction manual is available on the CD-ROM.

To remove or uninstall software, follow the above instructions and select Uninstall. You need to close all windows before you uninstall any software.

The TCS101 product installs four different support packages.

TCS101 SPI-3 and SPI-4.2 Bus Software Support

2-- 1

Setting Up the Support

Support Package Setups

The TCS101 product installs four acquisition support packages that have their own setup software and disassemblers. A description of each support package is listed here.

H SPI3_TX: Use this support package to acquire SPI-3 transmit bus traffic. The

H SPI3_RX: Use this support package to acquire SPI-3 receive bus traffic. The

H SPI4: Use this support package to acquire SPI-4.2 bus traffic. The support

H SPI4_LVTTL: Use this support package to acquire SPI-4.2 bus traffic. The

support package decodes the acquired data and labels the bus cycles in a packet style display. The package supports 8-bit and 32-bit buses.

package acquires the FIFO Status bus using LVDS signaling. It can be used with the transmit or receive interfaces. It decodes the acquired data and labels the bus cycles in a packet style display.

support package acquires the FIFO Status bus using LVTTL signaling. It can be used with the transmit or receive interfaces. It decodes the acquired data and labels the bus cycles in a packet style display.

Clocking Options

SPI3_TX and SPI3_RX

The TCS101 product adds these four selections to the “Load Support Package” dialog box, under the File pulldown menu.

A special custom clocking program is loaded into the module every time you load one of the SPI3_TX, SPI3_RX, SPI4, and SPI4_LVTTL support packages from the TCS101 product. Each support package offers different clocking options. You may use the default clocking option or choose an alternate by clicking the “More...” button in the logic analyzer setup window.

The software provides two custom clocking options for the SPI3_TX and SPI3_RX support packages.

Cycles. The Cycles option provides the following choices:

H “All” is for storing data on every clock cycle (default).

H “Active Only” is for storing data only when the data bus is valid.

2-- 2

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Setting Up the Support

Physical Port. The Physical Port option provides the following choices:

H “Single-No InBand Addr” is for a single physical port without TSX or RSX

signals (default).

H “Single With InBand Addr” is for a single physical port with TSX or RSX

signals.

H “Multiple” is for multiple physical port interfaces. This option uses TSX or

RSX and PTPA signals, including byte level and packet level transfer modes.

SPI4 and SPI4_LVTTL

The software provides one custom clocking option for SPI4 and SPI4_LVTTL support packages:

All Cycles. “All Cycles” is for storing data on every clock cycle.

TCS101 SPI-3 and SPI-4.2 Bus Software Support

2-- 3

Setting Up the Support

2-- 4

TCS101 SPI-3 and SPI-4.2 Bus Software Support

Acquiring and Viewing Disassembled Data

This section describes how to acquire data and view it disassembled. The following information covers these topics and tasks:

H Acquiring data

H Changing the way data is displayed

H Labels for bus cycles

H Viewing disassembled data in various display formats

Acquiring Data

The TCS101 product for the SPI-3 and SPI-4.2 bus installs four different supports: SPI3_TX, SPI3_RX, SPI4, and SPI4_LVTTL.

Once you load the support package, choose a clocking mode, and specify the trigger, you are ready to acquire and disassemble data.

If you have any problems acquiring data, refer to information on basic operations in your logic analyzer online help.

Changing How Data is Displayed

Common fields and features allow you to further modify displayed data to fit your needs. You can make common and optional display selections in the Disassembly property page.

You can make selections unique to the support package from the TCS101 product to do the following tasks:

H Change how data is displayed across all display formats

H Change the interpretation of disassembled cycles

TCS101 SPI-3 and SPI-4.2 Bus Software Support

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Acquiring and Viewing Disassembled Data

Optional Display

Selections

Tables 2--1 through 2--2 show the disassembly display options for the SPI-3 and SPI-4.2 support packages.

Table 2--1: Logic analyzer disassembly display options for SPI3_TX and SPI3_RX support packages

Description Option

Show All (default)

Packet

Highlight All (default)

Disassemble Across Gaps Yes

No (default)

Table 2--2: Logic analyzer disassembly display options for SPI4 and SPI4_LVTTL support packages

Description Option

Show All (default)

Packet & Control Packet Only

Highlight All (default)

Bus Specific Fields

Disassemble Across Gaps Yes

No (default)

You can make optional selections for disassembled data. In addition to the common selections (described in the information on basic operations), you can change the displayed data in the following ways.

Table 2--3 lists the bus specific fields for SPI3_TX and SPI3_RX support packages.

Table 2--3: Bus specific fields for SPI3_TX and SPI3_RX support packages

Field Definition

Port Address Filter Choose whether to filter the acquired data sent

to or received from a port

Port Address Enter the port address in hexadecimal

Physical Port Configuration Select the physical port configuration

Cycles Select cycles to decode data

Data Bus Width Select the data bus width in bits

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TCS101 SPI-3 and SPI-4.2 Bus Software Support

+ 76 hidden pages

Tektronix TCS101 Primary User

Specifications and Main Features

Frequently Asked Questions

User Manual

SOFTWARE WARRANTY

Table of Contents

List of Figures

List of Tables

Preface

Manual Conventions

Contacting Tektronix

Getting Started

Support Package Description

Logic Analyzer Software Compatibility

Logic Analyzer Configuration

Requirements and Restrictions

Limitations of the Support

Connecting the Logic Analyzer to a Target System

Labeling P6880 and P6860 Probes

Setting Up the Support

Installing the Support Software

Support Package Setups

Clocking Options

Acquiring and Viewing Disassembled Data

Acquiring Data

Changing How Data is Displayed