Supermicro X9DRG-OF-CPU, X9DRG-O-PCIE, X9DRG-OTF-CPU User Manual

USER’S MANUAL

Revision 1.0

X9DRG-OF-CPU

X9DRG-OTF-CPU

X9DRG-OF Platform

including:

X9DRG-O-PCIE

Manual Revision 1.0

Release Date: February 28, 2014

Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document.

Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.

Copyright © 2014 by Super Micro Computer, Inc.
All rights reserved.

Printed in the United States of America

The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
and makes no commitment to update or to keep current the information in this manual, or to notify
any person or organization of the updates. Please Note: For the most up-to-date version of this

manual, please see our Website at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software and docu­mentation, is the property of Supermicro and/or its licensors, and is supplied only under a license.
Any use or reproduction of this product is not allowed, except as expressly permitted by the terms
of said license.

IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE
USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC.
SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED
WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between the manufacturer and the customer shall be governed by the laws of
Santa Clara County in the State of California, USA. The State of California, County of Santa Clara
shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for
all claims will not exceed the price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”.

WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.

Preface

This manual is written for system integrators, IT professionals, and

knowledgeable end-users. It provides information for the installation and use of the

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform, which includes the X9DRG-O(T)F-

CPU board and the X9DRG-O-PCIE card.

About the X9DRG-O(T)F Platform

The Super X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform supports dual Intel® E5-

2600 Series Processors (Socket R) which offer QPI (Intel QuickPath Interface)

Technology (V.1.1) providing point-to-point connection with a transfer speed of up

to 8.0 GT/s. With the PCH C602 chipset built in, the X9DRG-OF Platform supports

Intel® Intelligent Power Node Manager, Management Engine (ME), Rapid Storage

Technology, Digital Media Interface (DMI), PCI-E Gen. 3.0 and up to 1600 MHz

DDR3 memory. This motherboard is ideal for GPU (Graphics Processing Unit)

server platforms. Please refer to our website (http://www.supermicro.com) for CPU

and memory support updates.

Manual Organization

Chapter 1 describes the features, specications and performance of the mother-

board, and provides detailed information about the Intel PCH C602 chipset.

Chapter 2 provides hardware installation instructions. Read this chapter when in-

stalling the processor, memory modules and other hardware components into the

system. If you encounter any problems, see Chapter 3, which describes trouble-

shooting procedures for video, memory, and system setup stored in CMOS.

Chapter 4 includes an introduction to the BIOS, and provides detailed information

on running the CMOS Setup utility.

Appendix A provides BIOS Error Beep Codes.

Appendix B lists Software Installation Instructions.

Preface

iii

iv

Conventions Used in the Manual

Pay special attention to the following symbols to ensure proper system installation

and to prevent damage to the system or injury to yourself:

Warning: Important information given to ensure proper system installation or to prevent

damage to the components

Note: Additional information given to differentiate between various models

or provides information for correct system setup.

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Preface

v

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

Web Site: www.supermicro.com

Europe

Address: Super Micro Computer B.V.

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

[e-mail] (Customer Support)

Web Site: www.supermicro.com

Asia-Pacic

Address: Super Micro Computer, Inc.

3F, No. 150, Jian 1st Rd.

Zhonghe Dist., New Taipei City 235

Taiwan (R.O.C)

Tel: [phone]

Fax: [phone]

Email: [e-mail]

Tel: [phone]

Web Site: www.supermicro.com.tw

vi

Table of Contents

Preface

Chapter 1 Overview

1-1 Overview ......................................................................................................... 1-1

1-2 Processor and Chipset Overview.................................................................. 1-17

1-3 Special Features ........................................................................................... 1-18

1-4 PC Health Monitoring .................................................................................... 1-18

1-5 ACPI Features ............................................................................................... 1-19

1-6 Power Supply ................................................................................................ 1-19

1-7 UART ............................................................................................................. 1-19

1-8 Advanced Power Management ..................................................................... 1-20

Intel® Intelligent Power Node Manager (NM) ................................................ 1-20

Management Engine (ME) ............................................................................ 1-20

1-9 Overview of the Nuvoton WPCM450 Controller ........................................... 1-20

WPCM450R DDR2 Memory Interface .......................................................... 1-21

WPCM450R PCI System Interface ............................................................... 1-21

Other Features Supported by the WPCM BMC Controller ........................... 1-21

Chapter 2 Installation

2-1 Standardized Warning Statements ................................................................. 2-1

Battery Handling .............................................................................................. 2-1

Product Disposal ............................................................................................. 2-3

2-2 Static-Sensitive Devices .................................................................................. 2-4

Precautions ..................................................................................................... 2-4

Unpacking ....................................................................................................... 2-4

2-3 System Overview ............................................................................................ 2-5

Removing and Installing the PCIE Card ........................................................ 2-6

2-4 Processor and Heatsink Installation................................................................ 2-7

Installing the LGA2011 Processor ................................................................. 2-7

Installing a Passive CPU Heatsink ................................................................2-11

Removing the Heatsink ................................................................................. 2-12

2-5 Installing and Removing the Memory Modules ............................................. 2-13

Installing & Removing DIMMs ....................................................................... 2-13

Removing Memory Modules ......................................................................... 2-13

2-6 Control Panel Connectors and I/O Ports ...................................................... 2-18

Back Panel Connectors and I/O Ports .......................................................... 2-18

Back Panel I/O Port Locations and Denitions ........................................... 2-18

Universal Serial Bus (USB) ...................................................................... 2-19

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

vii

Table of Contents

Video Connection ..................................................................................... 2-19

Ethernet Ports .......................................................................................... 2-20

Unit Identier Switch ................................................................................ 2-21

Front Control Panel ....................................................................................... 2-22

Front Control Panel Pin Denitions............................................................... 2-23

NMI Button ............................................................................................... 2-23

Power LED .............................................................................................. 2-23

HDD LED/UID Switch ............................................................................... 2-24

NIC1/NIC2 LED Indicators ....................................................................... 2-24

Overheat (OH)/Fan Fail/PWR Fail/UID LED ............................................ 2-25

Power Fail LED ........................................................................................ 2-25

Reset Button ........................................................................................... 2-26

Power Button ........................................................................................... 2-26

2-7 Connecting Cables ........................................................................................ 2-27

Power Connectors ................................................................................... 2-27

Fan Headers ............................................................................................. 2-28

Chassis Intrusion ..................................................................................... 2-28

Serial Ports ............................................................................................... 2-29

TPM Header/Port 80 ................................................................................ 2-30

Overheat LED/Fan Fail ............................................................................ 2-30

T-SGPIO1/2/-S1 Headers ......................................................................... 2-31

Speaker Header ....................................................................................... 2-32

DOM Power Connector ............................................................................ 2-32

2-8 Jumper Settings ............................................................................................ 2-33

Explanation of Jumpers ................................................................................ 2-33

GLAN Enable/Disable .............................................................................. 2-33

CMOS Clear ............................................................................................. 2-34

Watch Dog Enable/Disable ...................................................................... 2-34

VGA Enable .............................................................................................. 2-35

BMC Enable ............................................................................................ 2-35

Management Engine (ME) Recovery ...................................................... 2-36

Manufacture Mode Select ........................................................................ 2-36

2-9 Onboard LED Indicators ............................................................................... 2-37

LAN LEDs ................................................................................................. 2-37

IPMI Dedicated LAN LEDs ....................................................................... 2-37

Onboard Power LED ............................................................................... 2-38

BMC Heartbeat LED ................................................................................ 2-38

2-10 Serial ATA Connections ................................................................................. 2-39

Serial ATA Ports........................................................................................ 2-39

viii

Chapter 3 Troubleshooting

3-1 Troubleshooting Procedures ........................................................................... 3-1

3-2 Technical Support Procedures ........................................................................ 3-5

3-3 Battery Removal and Installation .................................................................... 3-6

3-4 Frequently Asked Questions ........................................................................... 3-7

3-5 Returning Merchandise for Service................................................................. 3-8

Chapter 4 BIOS

4-1 Introduction ...................................................................................................... 4-1

4-2 Main Setup ...................................................................................................... 4-2

4-3 Advanced Setup Congurations...................................................................... 4-4

4-4 Event Logs .................................................................................................... 4-25

4-5 IPMI ............................................................................................................... 4-27

4-6 Boot ............................................................................................................... 4-29

4-7 Security ......................................................................................................... 4-31

4-8 Save & Exit ................................................................................................... 4-32

Appendix A BIOS Error Beep Codes

A-1 BIOS Error Beep Codes .................................................................................A-1

Appendix B Software Installation Instructions

B-1 Installing Software Programs ..........................................................................B-1

B-2 Installing SuperDoctor® 5 ...............................................................................B-2

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Chapter 1: Overview

1-1

Chapter 1

Overview

1-1 Overview

Checklist

Congratulations on purchasing your computer motherboard from an acknowledged

leader in the industry. Supermicro boards are designed with the utmost attention to

detail to provide you with the highest standards in quality and performance.

This motherboard was designed to be used in an SMC-proprietary server as a part

of an integrated system platform.

Note: For your system to work properly, please follow the links below to

download all necessary drivers/utilities and the user's manual for your

motherboard.

•Supermicro product manuals: http://www.supermicro.com/support/manuals/

•Product Drivers and utilities: ftp://ftp.supermicro.com/

•If you have any questions, please contact our support team at support@su-

permicro.com.

Warning: For safety considerations, please refer to the complete list of safety warn-

ings posted on the Supermicro website at http://www.supermicro.com/about/policies/

safety_information.cfm.

1-2

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

X9DRG-O(T)F-CPU Board Image

Note: All graphics shown in this manual were based upon the latest PCB

Revision available at the time of publishing of the manual. The CPU board

and the PCI-E card you've received may or may not look exactly the same

as the graphics shown in this manual.

Chapter 1: Overview

1-3

X9DRG-O(T)F-CPU Board Layout

Note 1: For the latest CPU/Memory updates, please refer to our website

at http://www.supermicro.com/products/motherboard/ for details.

Note 2: Changing BMC log-in information is recommended during initial

system power-on. The default username is ADMIN and password is

ADMIN. For BMC best practices, please refer to: http://www.supermicro.

com/products/nfo/les/IPMI/Best_Practices_BMC_Security.pdf.

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

1-4

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

X9DRG-O-PCI-E Card Image

Chapter 1: Overview

1-5

X9DRG-O-PCI-E Card Layout

J9

FAN25

FAN24

FAN23

FAN22

FAN21

LE5

LE17

LE16

LE15

LE14

LE13

LE12

LE3

LE9

LE11

LE10

LE2

LE8

LE7

LE6

LE4

BAR CODE

CPU1

SLOT11 PCI-E 3.0 X16

CPU1

SLOT10 PCI-E 3.0 X16

CPU1

SLOT9 PCI-E 3.0 X16

CPU1

SLOT8 PCI-E 3.0 X16

PCH

SLOT7 PCI-E 2.0 X4 (IN X16)

CPU1

SLOT6 PCI-E 3.0 X8 (IN X16)

CPU2

SLOT5 PCI-E 3.0 X8 (IN X16)

CPU2

SLOT4 PCI-E 3.0 X16

CPU2

SLOT3 PCI-E 3.0 X16

CPU2

SLOT2 PCI-E 3.0 X16

CPU2

SLOT1 PCI-E 3.0 X16

REV:1.00

X9DRG-O-PCIE

J33

J34

J31

J32

1-6

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

X9DRG-O(T)F-CPU Quick Reference

Note 1: See Chapter 2 for detailed information on jumpers, I/O ports and

JF1 front panel connections.

Note 2: " " indicates the location of "Pin 1".

Note 3: Jumpers/LED Indicators not indicated are for testing only.

Note 4: Use only the correct type of onboard CMOS battery as specied

by the manufacturer. Do not install the onboard battery upside down to

avoid possible explosion

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Chapter 1: Overview

1-7

X9DRG-O(T)F-CPU Board Jumpers

Jumper

Description Default Setting

JBR1 BIOS Recovery Pins 1-2 (Normal)

JBT1 Clear CMOS See Chapter 2

JPB1 BMC Enabled Pins 1-2 (Enabled)

JPG1 VGA Enabled Pins 1-2 (Enabled)

JPL1 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)

JPME1 Management Engine (ME)

Recovery Mode

Pins 1-2 (Normal)

JPME2 Management Engine (ME)

Manufacture Mode

Pins 1-2 (Normal)

JWD1 Watch Dog Timer Enable Pins 1-2 (Reset)

X9DRG-O(T)F-CPU Connectors

Connectors Description

BT1 Onboard CMOS Battery (See Chpt. 3 for Used Battery Disposal)

COM1 Serial Port (COM1) Header

FAN1-8 CPU/System Cooling Fans

J21 X9DRG-O(T)F-CPU CPLD Programming

J31/32/33/34 Slot for Riser Card (RSC-X9DRG-O)

JF1 Front Panel Control Header

JL1 Chassis Intrusion

JOH1 Overheat LED Header

JPW3-JPW7,
JPW12-JPW16

PCIe Add-on Card AUX Power Connector

JPW17-JPW18 HDD Backplane Power Connector (See warning on next page)

JPW21/22/23/24 Power Supply Power Connector

JSD1/JSD2 SATA DOM (Devices on Module) Power Connectors

JTPM1 TPM (Trusted Platform Module)/Port 80

LAN1/LAN2 X540_based 10G Ethernet LAN Ports 1/2 (X9DRG-OTF-CPU); I350_based

1G LAN Ports 1/2 (X9DRG-OF-CPU)

(IPMI) LAN IPMI_Dedicated LAN

I-SATA 0-5 SATA 3.0 Connectors (I-SATA 0/1), SATA 2.0 Connectors (I-SATA 2-5) from

AHCI

S-SATA 1-4 SATA 2.0 connectors from SCU (S-SATA 1-4)

SP1 Onboard Speaker Header

SW1 UID Switch

T-SGPIO1/2 Serial_Link General Purpose I/O Header 1 for I-SATA Ports 0~3

Serial_Link General Purpose I/O Header 2 for I-SATA Ports 4~5

1-8

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

T-SGPIO-S1 Serial_Link General Purpose I/O Header for S-SATA Ports 1-4

USB 0/1, 2/3 Back Panel USB 0/1, 2/3

USB 6 USB Internal Type A connector

USB 8/9 USB x2 Header

USB 10/11 USB x2 Header

VGA1 VGA output port

X9DRG-O(T)F-CPU LED Indicators

LED Description State Status

DM1 BMC Heartbeat LED Green BMC Normal

LE1 Standby PWR LED Green: On SB Power On

LE4 UID Switch LED Blue: On Unit Identied

Warning: To provide adequate power supply to the system, be sure to connect all

onboard power connectors to the power supply.

Chapter 1: Overview

1-9

X9DRG-O-PCIE Quick Reference

J9

FAN25

FAN24

FAN23

FAN22

FAN21

LE5

LE17

LE16

LE15

LE14

LE13

LE12

LE3

LE9

LE11

LE10

LE2

LE8

LE7

LE6

LE4

BAR CODE

CPU1

SLOT11 PCI-E 3.0 X16

CPU1

SLOT10 PCI-E 3.0 X16

CPU1

SLOT9 PCI-E 3.0 X16

CPU1

SLOT8 PCI-E 3.0 X16

PCH

SLOT7 PCI-E 2.0 X4 (IN X16)

CPU1

SLOT6 PCI-E 3.0 X8 (IN X16)

CPU2

SLOT5 PCI-E 3.0 X8 (IN X16)

CPU2

SLOT4 PCI-E 3.0 X16

CPU2

SLOT3 PCI-E 3.0 X16

CPU2

SLOT2 PCI-E 3.0 X16

CPU2

SLOT1 PCI-E 3.0 X16

REV:1.00

X9DRG-O-PCIE

J33

J34

J31

J32

Note: Jumpers/LED Indicators not indicated are for testing only.

1-10

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

X9DRG-O-PCIE Connectors

Connector Description

JPCIE1 CPU2 Slot1 3.0 x16

JPCIE2 CPU2 Slot2 3.0 x16

JPCIE3 CPU2 Slot3 3.0 x16

JPCIE4 CPU2 Slot4 3.0 x16

JPCIE5 CPU2 Slot5 3.0 x8 (in x16)

JPCIE6 CPU1 Slot6 3.0 x8 (in x16)

JPCIE7 PCH Slot7 2.0 x4 (in x16)

JPCIE8 CPU1 Slot8 3.0 x8 (in x16)

JPCIE9 CPU1 Slot9 3.0 x16

JPCIE10 CPU1 Slot10 3.0 x16

JPCIE11 CPU1 Slot11 3.0 x16

X9DRG-O-PCIE LED Indicators

LED Description State Status

LE2 CPU1 Port2 Fatal Error Indicator Static Red Fatal error

LE3 CPU1 Port3 Fatal Error Indicator Static Red Fatal error

LE4 CPU2 Port2 Fatal Error Indicator Static Red Fatal error

LE5 CPU2 Port3 Fatal Error Indicator Static Red Fatal error

LE6

CPU1 Port2 Link Error Indicator
(Uptream port status of CPU1 Slot 8/9)

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE7 CPU1 Slot8 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE8 CPU1 Slot9 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE9

CPU1 Port3 Link Status Indictor
(Uptream port status of CPU1 Slot 10/11)

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

Chapter 1: Overview

1-11

LED Description State Status

LE10 CPU1 Slot10 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE11 CPU1 Slot11 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE12

CPU2 Port2 Link Status Indicator
(Uptream port status of CPU2 Slot 3/4)

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE13 CPU2 Slot3 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE14 CPU2 Slot4 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE15

CPU2 Port3 Link Status Indicator
(Uptream port status of CPU2 Slot 1/2)

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE16 CPU2 Slot1 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

LE17 CPU2 Slot2 Link Status Indicator

Off
1HZ Green Blinking
2HZ Green Blinking
Static Green On

Link is down

2.5GT/s
5GT/s
8GT/s

1-12

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Motherboard Features

CPU

• Dual Intel

®

E5-2600(V2) Series (Socket R LGA 2011)

processors; each processor supports two full-width

Intel QuickPath Interconnect (QPI) links (with Data

Transfer Rate of up to 8.0 GT/s per QPI).

Note: For Intel E5-2600(v2) processor support,

BIOS version 3.0 or above is required.

Memory

• Integrated memory controller supports up to 1.5 TB of

LRDIMM, 768 GB of RDIMM, or 128 GB of UDIMM

ECC/Non-ECC DDR3 800/1066/1333/1600/1866

MHz 240-pin 4-channel memory modules in 24 DIMM

slots.

Note 1: 1866 MHz memory speed is dependent

on Intel E5-2600v2 CPUs.

Note 2: For the latest memory updates, please

refer to the Tested Memory List posted on our

website (http://www.supermicro.com/products/

motherboard).

Chipset

• Intel

®

C602 PCH

Expansion

• Ten (10) PCI-E 2.0/3.0 slots: eight (8) x16, two (2) x8

(all in x16 slot)

• One (1) PCI-E 2.0 x4 in x16 slot (from PCH)

Slots

Graphics

• Nuvoton BMC Video Controller (Matrox G200)

Network

• One Intel I350 Gigabit (10/100/1000 Mb/s) Ethernet

Dual-Channel Controller for LAN 1/LAN 2 ports (for

X9DRG-OF-CPU)

• One Intel X540 Dual-Channel Controller for 10G-

based-T LAN 1/LAN 2 ports (for X9DRG-OTF-CPU)

Chapter 1: Overview

1-13

I/O Devices

SATA Connections

• SATA Ports Two (2): SATA 3.0 Ports (I-

SATA0/1)

Eight (8) SATA 2.0 Ports (I-SA-

TA2~5 from AHCI, S-SATA1-4

from SCU)

• RAID RAID 0, 1, 5, 10

IPMI 2.0

• IPMI 2.0 supported by the Nuvoton WPCM450R BMC

Serial (COM) Port

• One (1) Fast UART 16550 Connection: 9-pin RS-232

Header

VGA Port

• One (1) VGA output port

Peripheral
Devices

USB Devices

• Four (4) USB 2.0 ports on the rear I/O panel

• One (1) USB Internal Type A. Two (2) USB 2.0 header,

two ports/header

BIOS

• 16MB SPI AMI BIOS

®

SM Flash BIOS

• APM 1.2, PCI 2.3, ACPI 1.0/2.0/3.0, USB Keyboard,

Plug & Play (PnP) and SMBIOS 2.5

Power

• ACPI/ACPM Power Management

Management

• Main switch override mechanism

• Keyboard Wake-up from Soft-Off

• Power-on mode for AC power recovery

• Intel

®

Intelligent Power Node Manager (Available

when the supporting rmware and the power supply

cable are installed on the motherboard.)

• Management Engine

PC Health

CPU Monitoring

Monitoring

• Onboard voltage monitors for CPU Cores, +1.1V,

+1.5V, +3.3V, +5V, +12V, +3.3V Standby, +5V Stand-

by, VBAT, and Memory Voltages.

• CPU Thermal Design Power (TDP): support up to

150W (See Note 1 on the next page).

1-14

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

• CPU 6+1 Phase switching voltage regulator

• CPU/System overheat LED and control

• CPU Thermal Trip support

• Thermal Monitor 2 (TM2) support

Fan Control

• Fan status monitoring with rmware thermal manage-

ment via IPMI interface

• Low noise fan speed control

System
Management

• PECI (Platform Environment Conguration Interface)

2.0 support

• System resource alert via SuperDoctor5

• SuperDoctor5, Watch Dog, NMI

• Chassis Intrusion Header and Detection

Dimensions

• 17" x 19" (431.8mm x 482.6mm)

Note 1: CPU Maximum Thermal Design Power (TDP) is subject to chassis

and heatsink cooling restrictions. For proper thermal management, please

check the chassis and heatsink specications for proper CPU TDP sizing.

Note 2: For IPMI Conguration Instructions, please refer to the Embedded

IPMI Conguration User's Guide available @ http://www.supermicro.com/

support/manuals/.

Chapter 1: Overview

1-15

System Block Diagram

Note: This is a general block diagram and may not exactly represent the

features on your motherboard. See the Motherboard Features pages for

the actual specications of each motherboard.

CPU2

CPU1

i350/X540

LAN

#D-3

#C-3

#B-3

#A-3

#4

#5

i_SATA

#E-3

#F-3

#0

#1

#G-3

#H-3

#2

#3

6+1 PHASE

150W

USB 2.0

USB

4 in Rear IO
1 internal Type A
possible

2 inernal headers

3.0 Gb/S

For PORT 2~5

6.0 Gb/S

For PORT 0~1

PORTs #0~3

DDRIII

P1

P1

P0

VR12

P0

#B-1

#A-1

QPI
8G

DDR3
VDDQ

VRM

PCH
PATSBURG

DDR3
VDDQ
VRM

DDR3
VTT
VRM

DDR3
VTT
VRM

PORTs #0~1

PCI-E X16 Gen3

SATA

DMI2

SPI

DMI2

i_SATA

SATA3

SATA2

BMC
WPCM450

PCI-E X24

PCI-E X16 Gen3

PCI

DMI2

#A-2

DDR-III

DDR-III

QPI

8G

PCI-E X24

PCI-E X24

6+1 PHASE

150W

VR12

VGA

PCI-E X8 Gen3

PCI-E X24

SAS

PCI-E X8 Gen3

PCI-E X16 Gen3

PCI-E X16 Gen3

#2

Internal

COM Port

Header

#B-2

#C-1

#C-2

#D-1

#D-2

DDRIII

#F-1

#E-1

#E-2

#G-1

#F-2

#H-2

#H-1

#G-2

PORTs #2~5

SATA

PCI

S_SATA

3.0 Gb/S

For PORT 6~9

SATA2

#6

#7

#8

#9

PCI-E X4 Gen2

PCI-E X4 Gen2

DMI2

#3

#1

Dedicated LAN

VGA Port

#1

#2

#3

CPU Board Block Diagram

1-16

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

PCIE Card Block Diagram

Note: This is a PCIE Card block diagram and may not exactly represent

the features on your card.

CPU1CPU2

PCH

10G

X540
LOM

PEX8747

slot
1

slot
2

slot
3

slot
5

slot
6

slot
4

slot7slot

8

slot
9

slot
10

slot
11

PEX8747PEX8747PEX8747

Gen3

X16

port 3

port 2

Gen2

X4

re-

driver

port 1

re-

driver

port 2

port 3

port 1

RSC-X9DRG-ORSC-X9DRG-O

Gen3
X16

Gen3

X16

Gen3
X16

Gen3

X16

Gen3
X16

Gen3

X16

Gen3
X8

Gen3
X16

Gen3

X8

Gen2

X4

Gen3

X16

Gen3

X16

Gen3

X16

Gen3

X16

Gen3

X8

Gen3
X8

PCIE Card Block Diagram

Chapter 1: Overview

1-17

1-2 Processor and Chipset Overview

Built upon the functionality and the capability of Intel® E5-2600 Series Proces-

sors (Socket R) and the C602 chipset, the X9DRG-O(T)F-CPU/X9DRG-O-PCIE

Platform provides the performance and feature sets required for dual_processor-

based 4U GPU server platforms.

With support of Intel QuickPath interconnect (QPI) Technology, the X9DRG-O(T)

F-CPU/X9DRG-O-PCIE Platform offers point-to-point serial interconnect interface

with a transfer speed of up to 8.0 GT/s, providing superb system performance.

The PCH chipset provides extensive IO support, including the following functions

and capabilities:

•PCI-Express Rev. 2.0 support

•ACPI Power Management Logic Support Rev. 3.0b or Rev. 4.0

•USB host interface backplane and front access support

•Intel Rapid Storage Technology supported

•Intel Virtualization Technology for Directed I/O (Intel VT-d) supported

•Intel Trusted Execution Technology supported

•Serial Peripheral Interface (SPI) Supported

•Digital Media Interface (DMI) supported

•Advanced Host Controller Interface (AHCI) supported

Note: For Intel E5-2600(v2) processor support, BIOS version 3.0 or

above is required.

1-18

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

1-3 Special Features

Recovery from AC Power Loss

The Basic I/O System (BIOS) provides a setting that determines how the system will

respond when AC power is lost and then restored to the system. You can choose for

the system to remain powered off (in which case you must press the power switch

to turn it back on), or for it to automatically return to the power-on state. See the

Advanced BIOS Setup section for this setting. The default setting is Last State.

1-4 PC Health Monitoring

This section describes the features of PC health monitoring of the motherboard.

This motherboard has an onboard System_Hardware_Monitor chip that supports

PC health monitoring. An onboard voltage monitor will scan the following onboard

voltages continuously:Onboard voltage monitors for +3.3V, 3.3VSB, +5V, +5V Dual,

+12V, HT, CPU Core, Memory, and Battery Voltages. Once a voltage becomes

unstable, a warning is given, or an error message is sent to the screen. The user

can adjust the voltage thresholds to dene the sensitivity of the voltage monitor.

Environmental Temperature Control

A thermal control sensor monitors the CPU temperature in real time and will turn

on the thermal control fan whenever the CPU temperature exceeds a user-dened

threshold. The overheat circuitry runs independently from the CPU. Once it detects

that the CPU temperature is too high, it will automatically turn on the thermal fan

control to prevent the CPU from overheating. The onboard chassis thermal circuitry

can monitor the overall system temperature and alert the user when the chassis

temperature is too high.

Note: To avoid possible system overheating, please be sure to provide

adequate airow to your system.

System Resource Alert

This feature is available when used with SuperDoctor® III in the Windows OS

environment or used with SuperDoctor II in Linux. SuperDoctor is used to notify

the user of certain system events. For example, you can congure SuperDoctor

to provide you with warnings when the system temperature, CPU temperatures,

voltages, and fan speeds go beyond a predened range.

Chapter 1: Overview

1-19

1-5 ACPI Features

ACPI stands for Advanced Conguration and Power Interface. The ACPI specica-

tion denes a exible and abstract hardware interface that provides a standard

way to integrate power management features throughout a PC system, including

its hardware, operating system and application software. This enables the system

to automatically turn on and off peripherals such as CD-ROMs, network cards, hard

disk drives and printers.

In addition to operating_system-directed power management, ACPI also provides

a generic system event mechanism for Plug and Play, and an operating system-

independent interface for conguration control. ACPI leverages the Plug and Play

BIOS data structures, while providing a processor architecture-independent imple-

mentation that is compatible with Windows 7, Windows Vista and Windows 2008

Operating Systems.

Slow Blinking LED for Suspend-State Indicator

When the CPU goes into a suspend state, the chassis power LED will start blinking

to indicate that the CPU is in suspend mode. When the user presses any key, the

CPU will "wake up," and the LED will automatically stop blinking and remain on.

1-6 Power Supply

As with all computer products, a stable power source is necessary for proper and

reliable operation. It is even more important for processors that have high CPU

clock rates.

The X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform supports SMC-Proprietary pow-

er connectors. In areas where noisy power transmission is present, you may choose

to install a line lter to shield the computer from noise. It is recommended that you

also install a power surge protector to help avoid problems caused by power surges.

Note: Please use SMC-proprietary power supply as specied as above.

This motherboard does not support any power supply manufactured by

other manufacturer.

1-7 UART

The COM port is a 16550 compatible serial communication header (UART). The

UART includes a 16-byte send/receive FIFO, a programmable baud rate generator,

complete modem control capability, and a processor interrupt system. The UART

provides legacy speed with baud rate of up to 115.2 Kbps.

1-20

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

1-8 Advanced Power Management

The new advanced power management features supported by this motherboard

include IPNM and ME. Please note that you will need to do the following to use

these two new features:

•Use a power supply that supports PMBus 1.1 or 1.2,

•Install the NMView software in your system. NMView is optional and can be

purchased from Supermicro.

Intel® Intelligent Power Node Manager (NM)

The Intel® Intelligent Power Node Manager (IPNM) provides your system with

real-time thermal control and power management for maximum energy efciency.

Although IPNM is supported by the BMC (Baseboard Management Controller),

your system must also have IPNM-compatible Management Engine (ME) rmware

installed in your system for IPNM support.

Note: Support for IPNM Specication Version 1.5 or Version 2.0 depends

on the power supply used in the system.

Management Engine (ME)

The Management Engine, which is an ARC controller embedded in the PCH, pro-

vides Server Platform Services (SPS) to your system. The services provided by

SPS are different from those provided by the ME on client platforms.

1-9 Overview of the Nuvoton WPCM450 Controller

The Nuvoton WPCM450R Controller, a Baseboard Management Controller (BMC),

supports 2D/VGA-compatible Graphic Cores with PCI interface, creating multi-media

virtualization via Keyboard/Video/Mouse Redirection (KVMR). The WPCM450R

Controller is ideal for remote system management.

The WPCM450R Controller interfaces with the host system via PCI connections

to communicate with the graphics cores. It supports USB 2.0 and 1.1 for remote

keyboard/mouse/virtual media emulation. It also provides LPC interface support to

communicate with the BMC. The WPCM450R Controller is connected to the network

via an external Ethernet PHY module or shared NCSI connections.

The WPCM450R communicates with onboard components via six SMBus inter-

faces, PECI (Platform Environment Control Interface) buses, and General Purpose

I/O ports.

Chapter 1: Overview

1-21

WPCM450R DDR2 Memory Interface

The WPCM450R supports a 16-bit DDR2 memory module with a speed of up to 220

MHz. For best signal integrity, the WPCM450R provides point-to-point connection.

WPCM450R PCI System Interface

The WPCM450R provides 32-bit, 33 MHz 3.3V PCI interface, which is compliant

with the PCI Local Bus Specication Rev. 2.3. The PCI system interface connects

to the onboard PCI Bridge used by the graphics controller.

Other Features Supported by the WPCM BMC Controller

The WPCM450R supports the following features:

•IPMI 2.0

•Serial over LAN

•KVM over LAN

•LAN Alerting-SNMP Trap

•Event Log

•X-Bus parallel interface for I/O expansion

•Multiple ADC inputs, Analog and Digital Video outputs

•SPI Flash Host BIOS and rmware bootstrap program supported

•Reduced Media Independent Interface (RMII)

•OS (Operating System) Independency

•Provides remote Hardware Health Monitoring via IPMI.

•Provides Network Management Security via remote access/console redirection.

•Supports the following Management tools: IPMIView, CLI (Command Line

Interface)

•RMCP+ protocol supported

1-22

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Note 1: For more information on IPMI conguration, please refer to the

IPMI User's Guide posted on our website at http://www.supermicro.com/

support/manuals/.

Note 2: The term "IPMI controller" and the term "BMC controller" can be

used interchangeably in this section.

Chapter 2: Installation

2-1

Chapter 2

Installation

2-1 Standardized Warning Statements

The following statements are industry-standard warnings provided to warn the user

of situations when potential bodily injury may occur. Should you have questions or

experience difculty, contact Supermicro's Technical Support department for assis-

tance. Only certied technicians should attempt to install or congure components.

Read this section in its entirety before installing or conguring components in the

system.

Battery Handling

Warning! There is a danger of explosion if the battery is replaced incor-

rectly. Replace the battery only with the same or equivalent type recom-

mended by the manufacturer. Dispose of used batteries according to the

manufacturer's instructions. (Refer to Chapter 3 for more information on

used battery disposal.

Warnung

Bei Einsetzen einer falschen Batterie besteht Explosionsgefahr. Ersetzen Sie die Bat-

terie nur durch den gleichen oder vom Hersteller empfohlenen Batterietyp. Entsorgen

Sie die benutzten Batterien nach den Anweisungen des Herstellers.

¡Advertencia!

Existe peligro de explosión si la batería se reemplaza de manera incorrecta. Reem-

plazar la batería exclusivamente con el mismo tipo o el equivalente recomendado por

el fabricante. Desechar las baterías gastadas según las instrucciones del fabricante.

2-2

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Attention

Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer que

par une pile de type semblable ou équivalent, recommandée par le fabricant. Jeter les

piles usagées conformément aux instructions du fabricant.

Waarschuwing

Er is ontplofngsgevaar indien de batterij verkeerd vervangen wordt. Vervang de batterij

slechts met hetzelfde of een equivalent type die door de fabrikant aanbevolen wordt.

Gebruikte batterijen dienen overeenkomstig fabrieksvoorschriften afgevoerd te worden.

هناك خطر من انفجار في حالة استبدال البطارية بطريقة غير صحيحة فعليك

استبدال البطارية

فقط بنفس النوع أو ما يعادلها كما أوصت به الشركة المصنعة

تخلص من البطاريات المستعملة وفقا لتعليمات الشركة الصانعة

Chapter 2: Installation

2-3

Product Disposal

Warning! Ultimate disposal of this product should be handled according

to all national laws and regulations.

Waarschuwing

De uiteindelijke verwijdering van dit product dient te geschieden in overeenstemming

met alle nationale wetten en reglementen.

Attention

La mise au rebut ou le recyclage de ce produit sont généralement soumis à des lois

et/ou directives de respect de l'environnement. Renseignez-vous auprès de l'organisme

compétent.

¡Advertencia!

Al deshacerse por completo de este producto debe seguir todas las leyes y regla-

mentos nacionales.

Warnung

Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen des

Landes erfolgen.

التخلص النهائي من هذا المنتج ينبغي التعامل معه وفقا لجميع القوانين

واللوائح الوطنية عند

2-4

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

2-2 Static-Sensitive Devices

Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid dam-

aging your system board, it is important to handle it very carefully. The following

measures are generally sufcient to protect your equipment from ESD.

Precautions

•Use a grounded wrist strap designed to prevent static discharge.

•Touch a grounded metal object before removing the board from the antistatic

bag.

•Handle the board by its edges only; do not touch its components, peripheral

chips, memory modules or gold contacts.

•When handling chips or modules, avoid touching their pins.

•Put the motherboard and peripherals back into their antistatic bags when not

in use.

•For grounding purposes, make sure that your system chassis provides excellent

conductivity between the power supply, the case, the mounting fasteners and

the motherboard.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage. When

unpacking the board, make sure that the person handling it is protected against

static.

Chapter 2: Installation

2-5

2-3 System Overview

The bare bone system you purchased comes with the X9DRG-O(T)F CPU board,

X9DRG-PCIE Card, and four Riser cards preinstalled in the chassis. You will need

to install the processors, memory modules, and other components on your own.

To install any components on the CPU board, you need to remove the PCIE Card

from the CPU board.

Chassis

PCIE Card

Motherboard

Riser Cards

(4 connected under the PCIE Card)

Note: Images displayed are for illustration only. Your chassis or compo-

nents may look different from those shown in this manual..

2-6

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Screw

Screwdriver Icon

Thumb Grip

"PULL" Handle

Removing and Installing the PCIE Card

1. Locate the 10 screws with the screwdriver icon next to them and unscrew

them.

2. To remove the PCIE Card, place one hand on the "PULL" handle and the

other hand on the thumb grip and pull the card up until it is detached from the

board.

3. Install components on the CPU board. Refer to section 2-4 for processor

installation and section 2-5 for memory installation. After you are nished

installing the components, install the PCIE Card back on the CPU board.

Chapter 2: Installation

2-7

OPEN 1st

WARNING!

2-4 Processor and Heatsink Installation

Warning: When handling the processor package, avoid placing direct pressure on

the label area.

Notes:

•Always connect the power cord last, and always remove it before adding,

removing or changing any hardware components. Make sure that you install

the processor into the CPU socket before you install the CPU heatsink.

•If you buy a CPU separately, make sure that you use an Intel-certied multi-

directional heatsink only.

•Make sure to install the system board into the chassis before you install

the CPU heatsink.

•When receiving a server board without a processor pre-installed, make sure

that the plastic CPU socket cap is in place and none of the socket pins are

bent; otherwise, contact your retailer immediately.

•Refer to the Supermicro website for updates on CPU support.

Press down

on

Load Lever

labeled 'Open 1st'.

Installing the LGA2011 Processor

1. There are two load levers on the LGA2011 socket. To open the socket cover,

rst press and release the load lever labeled 'Open 1st'.

OPEN 1st

WARNING!

1

2

2-8

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Gently push
down to pop the
load plate open.

2. Press the second load lever labeled 'Close 1st' to release the load plate that

covers the CPU socket from its locking position.

3. With the lever labeled 'Close 1st' l fully retracted, gently push down on the

lever labeled 'Open 1st' to open the load plate. Lift the load plate to open it

completely.

OPEN 1st

WARNING!

OPEN 1st

WARNING!

1

2

Press down on

Load

Lever labeled 'Close 1st'

WARNING!

OPEN 1st

WARNING!

1

Pull lever away from
the socket

2

Chapter 2: Installation

2-9

1. Use your index nger and your thumb to loosen the lever and open the load

plate.

Socket Keys

CPU Keys

Warning: You can only install the CPU

inside the socket in one direction.

Make sure that it is properly inserted

into the CPU socket before closing the

load plate. If it doesn't close properly,

do not force it as it may damage your

CPU. Instead, open the load plate

again and double-check that the CPU

is aligned properly.

WARNING!

2. Use your thumb and index nger to hold the CPU on its edges. Align the CPU

keys, which are semi-circle cutouts, against the socket keys.

3. Once they are aligned, carefully lower the CPU straight down into the socket.

(Do not drop the CPU on the socket. Do not move the CPU horizontally or

vertically. Do not rub the CPU against the surface or against any pins of the

socket to avoid damaging the CPU or the socket.)

2-10

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

4. With the CPU inside the socket, inspect the four corners of the CPU to make

sure that the CPU is properly installed.

OPEN 1st

OPEN 1st

OPEN 1st

Lever Lock

Lever Lock

Push down and lock the

lever labeled 'Open 1st'

Push down and lock the lever

labeled 'Close 1st'.

Gently close the load plate.

1 2

3

4

5. Close the load plate with the CPU inside the socket. Lock the lever labeled

'Close 1st' rst, then lock the lever labeled 'Open 1st' second. Use your

thumb to gently push the load levers down to the lever locks.

Chapter 2: Installation

2-11

Installing a Passive CPU Heatsink

1. Apply the proper amount of thermal grease to the heatsink.

2. Place the heatsink on top of the CPU so that the two mounting holes on the

heatsink are aligned with those on the retention mechanism.

3. Insert two push-pins on the sides of the heatsink through the mounting holes

on the motherboard, and turn the push-pins clockwise to lock them.

OPEN 1st

Motherboard

Screw#1

Screw#2

Mounting Holes

Notes: 1. For optimized airow, please follow your chassis airow direction

to install the correct CPU heatsink direction. 2. Graphic drawings included

in this manual are for reference only. They might look different from the

components installed in your system.

2-12

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Removing the Heatsink

Warning: We do not recommend that the CPU or the heatsink be removed. However,

if you do need to uninstall the heatsink, please follow the instructions below to uninstall

the heatsink to prevent damage done to the CPU or the CPU socket.

1. Unscrew the heatsink screws from the motherboard in the sequence as

shown in the illustration below.

2. Gently wriggle the heatsink to loosen it from the CPU. (Do not use excessive

force when wriggling the heatsink!)

3. Once the CPU is loosened, remove the CPU from the CPU socket.

4. Remove the used thermal grease and clean the surface of the CPU and the

heatsink, Reapply the proper amount of thermal grease on the surface before

reinstalling the CPU and the heatsink. (Do not reuse old thermal grease.)

Loosen screws
in sequence as
shown.

Screw#2

Motherboard

Screw#1

Screw#3

Screw#4

Chapter 2: Installation

2-13

Release Tabs

Notches

2-5 Installing and Removing the Memory Modules

Note: Check Supermicro's website for recommended memory modules.

CAUTION

Exercise extreme care when installing or removing DIMM

modules to prevent any possible damage.

Installing & Removing DIMMs

1. Insert the desired number of DIMMs into the memory slots, starting with P1-

DIMMA1. (For best performance, please use the memory modules of the

same type and speed in the same bank.)

2. Push the release tabs outwards on both ends of the DIMM slot to unlock it.

Removing Memory Modules

3. Align the key of the DIMM module with the receptive point on the memory

slot.

4. Align the notches on both ends of the module against the receptive points on

the ends of the slot.

5. Use two thumbs together to press the notches on both ends of the module

straight down into the slot until the module snaps into place.

6. Press the release tabs to the locking positions to secure the DIMM module

into the slot.

Press both notches straight

down into the memory slot at

the same time.

Press both notches on the ends of the DIMM module to unlock it. Once the DIMM

module is loosened, remove it from the memory slot.

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC
1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

2-14

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Memory Support for the X9DRG-O(T)F Motherboard

The X9DRG-O(T)F-CPU/X9DRG-O-PCIE motherboard supports up to 1.5 TB of

Load Reduced (LRDIMM), 768 Gb of Registered (RDIMM) or 128 GB of Unbuffered

(UDIMM) ECC/Non-ECC DDR3 800/1066/1333/1600/1866 MHz of 240-pin 4-chan-

nel memory in 24 DIMM slots.

Note: For the latest memory updates, please refer to the Tested Memory

List posted on our website (http://www.supermicro.com/products/mother-

board).

Processor & Memory Module Population Conguration

For memory to work properly, follow the tables below for memory population.

Processors and their Corresponding Memory Modules

CPU# Corresponding DIMM Modules

CPU 1

P1-DIMM

A1 A2 A3 B1 B2 B3 C1 C2 C3 D1 D2 D3

CPU2

P2-DIMM

E1 E2 E3 F1 F2 F3 G1 G2 G3 H1 H2 H3

Processor and Memory Module Population

Number of

CPUs+DIMMs

CPU and Memory Population Conguration Table

(*For memory to work properly, please follow the instructions below.)

1 CPU &
2 DIMMs

CPU1
P1-DIMMA1/P1-DIMMB1

1 CPU &
4 DIMMs

CPU1
P1-DIMMA1/P1-DIMMB1, P1-DIMMC1/P1-DIMMD1

1 CPU &

5~8 DIMMs

CPU1
P1-DIMMA1/P1-DIMMB1, P1-DIMMC1/P1-DIMMD1, P1-DIMMA2/P1-DIMMB2, P1­DIMMC2/P1-DIMMD2

1 CPU &

9~12 DIMMs

CPU1
P1-DIMMA1/P1-DIMMB1, P1-DIMMC1/P1-DIMMD1, P1-DIMMA2/P1-DIMMB2, P1­DIMMC2/P1-DIMMD2, P1-DIMMA3/P1-DIMMB3, P1-DIMMC3/P1-DIMMD3

2 CPUs &

4 DIMMs

CPU1 + CPU2
P1-DIMMA1/P1-DIMMB1, P2-DIMME1/P2-DIMMF1

2 CPUs &

6 DIMMs

CPU1 + CPU2
P1-DIMMA1/P1-DIMMB1, P2-DIMME1/P2-DIMMF1, P1-DIMMC1/P1-DIMMD1

2 CPUs &

8 DIMMs

CPU1 + CPU2
P1-DIMMA1/P1-DIMMB1, P2-DIMME1/P2-DIMMF1, P1-DIMMC1/P1-DIMMD1, P2­DIMMG1/P2-DIMMH1

2 CPUs &

9~12 DIMMs

CPU1/CPU2
P1-DIMMA1/P1-DIMMB1, P2-DIMME1/P2-DIMMF1, P1-DIMMC1/P1-DIMMD1, P2­DIMMG1/P2-DIMMH1, P1-DIMMA2/P1-DIMMB2, P2-DIMME2/P2-DIMMF2

2 CPUs &

13 DIMMs~24

DIMMs

CPU1/CPU
P1-DIMMA1/P1-DIMMB1, P2-DIMME1/P2-DIMMF1, P1-DIMMC1/P1-DIMMD1, P2­DIMMG1/P2-DIMMH1, P1-DIMMA2/P1-DIMMB2, P2-DIMME2/P2-DIMMF2,
P1-DIMMC2/P1-DIMMD2, P2-DIMMG2/P2-DIMMH2, P1-DIMMA3/P1-DIMMB3, P2­DIMME3/P2-DIMMF3, P1-DIMMC3/P1-DIMMD3, P2-DIMMG3/P2-DIMMH3

Chapter 2: Installation

2-15

Populating UDIMM (ECC/Non-ECC) Memory Modules

Intel E5-2600(v2) Series Processor UDIMM Memory Support

Ranks

Per

DIMM

& Data

Width

Memory Capacity

Per DIMM

(See the Note below)

Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and

DIMM Per Channel (DPC)

2 Slots Per Channel 3 Slots Per Channel

1DPC 2DPC 1DPC 2DPC

1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5v

SRx8

Non­ECC

1GB 2GB 4GB NA 1066,

1333,
1600,

1866

NA 1066,

1333,
1600

N/A 1066,

1333,
1600,

1866

N/A 1066,

1333,

1600

DRx8

Non­ECC

2GB 4GB 8GB NA 1066,

1333,
1600,

1866

NA 1066,

1333,
1600

N/A 1066,

1333,
1600,

1866

N/A 1066,

1333,

1600

SRx16

Non­ECC

512MB 1GB 2GB NA 1066,

1333,
1600,

1866

NA 1066,

1333,
1600

N/A 1066,

1333,
1600,

1866

N/A 1066,

1333,

1600

SRx8

ECC

1GB 2GB 4GB 1066,

1333

1066,
1333,
1600,

1866

1066,

1333

1066,
1333,
1600

1066,
1333

1066,
1333,
1600,

1866

1066,
1333

1066,
1333,

1600

DRx8

ECC

2GB 4GB 8GB 1066,

1333

1066,
1333,
1600,

1866

1066,

1333

1066,
1333,
1600

1066,
1333

1066,
1333,
1600,

1866

1066,
1333

1066,
1333,

1600

Note: For detailed information on memory support and updates, please refer to the SMC Recommended
Memory List posted on our website at http://www.supermicro.com/support/resources/mem.cfm.

Populating UDIMM (ECC/Non-ECC) Memory Modules

Intel E5-2600 Series Processor UDIMM Memory Support

Ranks

Per

DIMM

& Data

Width

Memory Capacity

Per DIMM

(See the Note below)

Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and

DIMM Per Channel (DPC)

2 Slots Per Channel 3 Slots Per Channel

1DPC 2DPC 1DPC 2DPC

1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5v

SRx8

Non-

ECC

1GB 2GB 4GB NA 1066,

1333

NA 1066,

1333

N/A 1066,

1333,

N/A 1066,

1333

DRx8

Non-

ECC

2GB 4GB 8GB NA 1066,

1333

NA 1066,

1333

N/A 1066,

1333,

N/A 1066,

1333

SRx16

Non-

ECC

512MB 1GB 2GB NA 1066,

1333

NA 1066,

1333

N/A 1066,

1333

N/A 1066,

1333

SRx8

ECC

1GB 2GB 4GB 1066,

1333

1066,

1333

1066 1066,

1333

1066 1066,

1333,

1066,
1333

1066,

1333

DRx8

ECC

2GB 4GB 8GB 1066,

1333

1066,

1333

1066 1066,

1333

1066 1066,

1333,

1066,
1333

1066,

1333

Note: For detailed information on memory support and updates, please refer to the SMC Recommended
Memory List posted on our website at http://www.supermicro.com/support/resources/mem.cfm.

Notes: 1866 MHz memory speed is dependent on Intel E5-2600v2 CPUs.

For Intel E5-2600(v2) processor support, BIOS version 3.0 or above is

required.

2-16

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Populating RDIMM (ECC) Memory Modules

Intel E5-2600 Series Processor RDIMM Memory Support

Ranks

Per

DIMM

&

Data

Width

Memory Capacity

Per DIMM

(See the Note Below)

Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel

(DPC)

2 Slots Per Channel 3 Slots Per Channel

1DPC 2DPC 1 DPC 2DPC 3DPC

1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5v

SRx8 1GB 2GB 4GB 1066,

1333

1066,
1333,

1600

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

N/A 800,

1066

DRx8 2GB 4GB 8GB 1066,

1333

1066,
1333,

1600

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

N/A 800,

1066

SRx4 2GB 4GB 8GB 1066,

1333

1066,
1333,

1600

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

N/A 800,

1066

DRx4 4GB 8GB 16GB 1066,

1333

1066,
1333,

1600

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

1066,
1333

1066,
1333,

1600

N/A 800,

1066

QRx4 8GB 16GB 32GB 800 1066 800 800 800 1066 800 800 N/A N/A

QRx8 4GB 8GB 16GB 800 1066 800 800 800 1066 800 800 N/A N/A

Note: For detailed information on memory support and updates, please refer to the SMC Recommended Memory List posted on

our website at http://www.supermicro.com/support/resources/mem.cfm.

Populating RDIMM (ECC) Memory Modules

Intel E5-2600(v2) Series Processor RDIMM Memory Support

Ranks

Per

DIMM

&

Data

Width

Memory Capacity

Per DIMM

(See the Note Below)

Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel

(DPC)

2 Slots Per Channel 3 Slots Per Channel

1DPC 2DPC 1 DPC 2DPC 3DPC

1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5v

SRx8 1GB 2GB 4GB 1066,

1333

1066,
1333,
1600,

1866

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,
1600,

1866

1066,
1333

1066,
1333,
1600

800 800,

1066

DRx8 2GB 4GB 8GB 1066,

1333

1066,
1333,
1600,

1866

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,
1600,

1866

1066,
1333

1066,
1333,
1600

800 800,

1066

SRx4 2GB 4GB 8GB 1066,

1333

1066,
1333,
1600,

1866

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,
1600,

1866

1066,
1333

1066,
1333,
1600

800 800,

1066

DRx4 4GB 8GB 16GB 1066,

1333

1066,
1333,
1600,

1866

1066,

1333

1066,
1333,

1600

1066,
1333

1066,
1333,
1600,

1866

1066,
1333

1066,
1333,
1600

800 800,

1066

QRx4 8GB 16GB 32GB 800 800

1066

800 800 800 800,

1066

800 800 N/A N/A

QRx8 4GB 8GB 16GB 800 800

1066

800 800 800 800,

1066

800 800 N/A N/A

Note: For detailed information on memory support and updates, please refer to the SMC Recommended Memory List posted on
our website at http://www.supermicro.com/support/resources/mem.cfm.

Chapter 2: Installation

2-17

Populating LRDIMM (ECC) Memory Modules

Intel E5-2600(v2) Series Processor LRDIMM Memory Support

Ranks

Per

DIMM

&

Data

Width

Memory

Capacity

Per DIMM

(See the Note

Below)

Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per

Channel (DPC)

2 Slots Per Channel 3 Slots Per Channel

1DPC 2DPC 1DPC 2DPC 3DPC

1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V

QRx4

(DDP)

16GB 32GB 1066,

1333,

1600

1066,
1333,
1600,
1866

1066,
1333,

1600

1066,
1333,

1600

1066,
1333,

1600

1066,
1333,
1600,

1866

1066,
1333,

1600

1066,
1333,

1600

1066 1066

8Rx4

(QDP)

32GB 64GB 1066 1066 1066 1066 1066 1066 1066 1066 1066 1066

Note: For detailed information on memory support and updates, please refer to the SMC Recommended Memory
List posted on our website at http://www.supermicro.com/support/resources/mem.cfm.

Intel E5-2600 Series Processor LRDIMM Memory Support

Ranks

Per

DIMM

&

Data

Width

Memory

Capacity

Per DIMM

(See the Note

Below)

Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per

Channel (DPC)

2 Slots Per Channel 3 Slots Per Channel

1DPC 2DPC 1DPC 2DPC 3DPC

1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V 1.35V 1.5V

QRx4

(DDP)

16GB 32GB 1066 1066,

1333

1066 1066,

1333

1066 1066,

1333

1066 1066,

1333

1066 1066

QRx8

(QDP)

8GB 16GB 1066 1066,

1333

1066 1066,

1333

1066 1066 1066 1066 1066 1066

Note: For detailed information on memory support and updates, please refer to the SMC Recommended Memory
List posted on our website at http://www.supermicro.com/support/resources/mem.cfm.

Other Important Notes and Restrictions

•For the memory modules to work properly, please install DIMM modules of the same

type, same speed and same operating frequency on the motherboard. Mixing of

RDIMMs, UDIMMs or LRDIMMs is not allowed. Do not install both ECC and Non-ECC

memory modules on the same motherboard.

•Using DDR3 DIMMs with different operating frequencies is not allowed. All channels

in a system will run at the lowest common frequency.

2-18

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

2-6 Control Panel Connectors and I/O Ports

The I/O ports are color coded in conformance with the industry standards. See

the picture below for the colors and locations of the various I/O ports.

Back Panel Connectors and I/O Ports

Back Panel I/O Port Locations and Denitions

1. IPMI LAN

2. Back Panel USB Port 0/1

3. Back Panel USB Port 2/3

4. LAN1

5. LAN2

6. VGA port (Blue)

7. UID Switch

1

2

3

4

5

6

7

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC
1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Chapter 2: Installation

2-19

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Video Connection

A Video (VGA1) port is located next

to LAN2 on the I/O backplane. Refer

to the board layout below for the

location.

1. BP USB0/1

2. BP USB2/3

3. VGA port

Universal Serial Bus (USB)

Four Universal Serial Bus ports (USB

0/1, 2/3) are located on the I/O back

panel to provide USB connections.

(Cables are not included). See the

tables on the right for pin denitions.

Backplane

USB

Pin Denitions

Pin# Denition

1 +5V

2 PO-

3 PO+

4 Ground

5 NA

1

2

3

2-20

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

1. LAN1

2. LAN2

Ethernet Ports

Two Ethernet ports (LAN1, LAN2) are located on the I/O backplane on the mother-

board. These LAN ports support 10G LAN (for X9DRG-OTF-CPU) or 1G LAN (for

X9DRG-OF-CPU). These ports accept RJ45 type cables. Please refer to the LED

Indicator Section for LAN LED information.

1

2

Chapter 2: Installation

2-21

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC
1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

1. UID Switch

2. Rear UID LED (LE4)

3. Front UID LED

Unit Identier Switch

A Unit Identier (UID) Switch and two LED In-

dicators are located on the motherboard. The

UID Switch is located next to LAN2 port on the

backplane. The Rear UID LED (LE4) is located

next to the UID Switch. The Front Panel UID

LED is located at pins 7/8 of the Front Control

Panel at JF1. Connect a cable to pin 8 on JF1

for Front Panel UID LED indication. When you

press the UID switch, both Rear UID LED and

Front Panel UID LED Indicators will be turned

on. Press the UID switch again to turn off both

LED Indicators. These UID Indicators provide

easy identication of a system unit that may

be in need of service.

Note: UID can also be triggered via

IPMI on the motherboard. For more

information on IPMI, please refer to

the IPMI User's Guide posted on our

website @ http://www.supermicro.

com.

UID LED (LE)

Status

Color/State OS Status

Blue: On Windows OS Unit Identied

Blue:
Blinking

Linux OS Unit Identied

1

2

3

Power Button

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

ID_UID_SW/3/3V Stby

Red+ (Blue LED Cathode)

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

2-22

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE

BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally lo-

cated on a control panel at the front of the chassis. These connectors are designed

specically for use with Supermicro's server chassis. See the gure below for the

descriptions of the various control panel buttons and LED indicators. Refer to the

following section for descriptions and pin denitions.

JF1 Header Pins

Power Button

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

ID_UID_SW/3/3V Stby

Red+ (Blue LED Cathode)

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

Chapter 2: Installation

2-23

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC
1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Power Button

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

ID_UID_SW/3/3V Stby

Red+ (Blue LED Cathode)

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

Power LED

The Power LED connection is located

on pins 15 and 16 of JF1. Refer to the

table on the right for pin denitions.

NMI Button

The non-maskable interrupt button

header is located on pins 19 and 20

of JF1. Refer to the table on the right

for pin denitions.

NMI Button

Pin Denitions (JF1)

Pin# Denition

19 Control

20 Ground

Power LED

Pin Denitions (JF1)

Pin# Denition

15 3.3V

16 PWR LED

Front Control Panel Pin Denitions

A. NMI

B. PWR LED

A

B

2-24

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Power Button

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

ID_UID_SW/3/3V Stby

Red+ (Blue LED Cathode)

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

B

NIC1/NIC2 LED Indicators

The NIC (Network Interface Controller) LED con-

nection for LAN port 1 is located on pins 11 and

12 of JF1, and the LED connection for LAN Port 2

is located on pins 9 and 10. Attach the NIC LED

cables here to display network activity. Refer to

the table on the right for pin denitions.

C

A. HDD LED/UID Switch

B. NIC1 LED

C. NIC2 LED

A

HDD LED/UID Switch

The HDD/UID Switch connection is located on pins

13 and 14 of JF1. Attach a hard drive LED cable

here to display HDD activities, including Serial ATA

activities. Connect a UID switch cable to use UID

switch connection. The front UID switch works in

conjunction with UID LED located at pins 7/8 and

rear UID LED (LE4). Also refer to page 2-21 for

more UID switch/LED information. See the table

on the right for pin denitions.

HDD LED/UID Switch

Pin Denitions (JF1)

Pin# Denition

13 UID Switch/3,3V

14 HDD Active

GLAN1/2 LED

Pin Denitions (JF1)

Pin# Denition

9 NIC 2 Act. LED

10 NIC 2 Link LED

11 NIC 1 Act. LED

12 NIC 1 Link LED

Chapter 2: Installation

2-25

Power Button

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

ID_UID_SW/3/3V Stby

Red+ (Blue LED Cathode)

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

Power Fail LED

The Power Fail LED connection is lo-

cated on pins 5 and 6 of JF1. Refer to the

table on the right for pin denitions.

A. OH/Fail/PWR Fail LED/UID LED

B. Blue LED Cathode

C. PWR Supply Fail

PWR Fail LED

Pin Denitions (JF1)

Pin# Denition

5 3.3V

6 PWR Supply Fail

B

A

Overheat (OH)/Fan Fail/PWR Fail/UID
LED

Connect an LED cable to pins 7 and 8

of Front Control Panel to use the Over-

heat/Fan Fail/Power Fail and UID LED

connections. The Red LED on pin 7 pro-

vides warnings of overheat, fan failure

or power failure. The Blue LED on pin 8

works as the front panel UID LED indi-

cator. The Red LED takes precedence

over the Blue LED by default. Refer to

the tables on the right for pin denitions.

OH/Fan Fail/ PWR Fail/Blue_UID

LED Pin Denitions (JF1)

Pin# Denition

7 Red_LED-Cathode/OH/Fan Fail/

Power Fail

8 Blue_UID LED

OH/Fan Fail/PWR Fail

LED Status (Red LED)

State Denition

Off Normal

On Overheat

Flashing Fan Fail

C

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC
1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

2-26

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC
1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Power Button

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

ID_UID_SW/3/3V Stby

Red+ (Blue LED Cathode)

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

Power Button

The Power Button connection is located

on pins 1 and 2 of JF1. Momentarily

contacting both pins will power on/off

the system. This button can also be con-

gured to function as a suspend button

(with a setting in the BIOS - See Chapter

4). To turn off the power when the system

is in suspend mode, press the button for

4 seconds or longer. Refer to the table on

the right for pin denitions.

Power Button

Pin Denitions (JF1)

Pin# Denition

1 Signal

2 Ground

Reset Button

The Reset Button connection is located

on pins 3 and 4 of JF1. Attach it to a

hardware reset switch on the computer

case. Refer to the table on the right for

pin denitions.

Reset Button

Pin Denitions (JF1)

Pin# Denition

3 Reset

4 Ground

A. Reset Button

B. PWR Button

A

B

Chapter 2: Installation

2-27

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE

BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Warning: To ensure adequate power supply to your motherboard, be sure to connect

all the power connectors mentioned above to your power supply for proper system

operation.

2-7 Connecting Cables

A. HDD Backplane Power Connectors

B. PCIe Add-on Card AUX Power Connectors

B

Power Connectors

To provide adequate power supply to the motherboard, the X9DRG-O(T)F-CPU/

X9DRG-O-PCIE platform contains the following components. See the tables below

for 8-pin power connector pin denitions.

•Two (2) HDD Backplane Power Connectors (JPW17, JPW18)

•Ten (10) PCIe Add-on Card AUX Power Connectors (JPW3-JPW7, JPW12-

JPW16)

8-Pin PCIe AUX

Power Con-

nector

Pin Denitions

Pins Denition

1~3 +12V

4~8 Ground

8-pin HDD

backplane Power

Connector

Pin Denitions

Pins Denition

1~4 Ground

5~6 +12V

7~8 +5V

A

B

2-28

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Chassis Intrusion

A Chassis Intrusion header is located

at JL1 on the motherboard. Attach an

appropriate cable from the chassis to

inform you of a chassis intrusion when

the chassis is opened.

Chassis Intrusion

Pin Denitions

Pin# Denition

1 Intrusion Input

2 Ground

C

A. Fan 1

B. Fan 2

C. Fan 3

D. Fan 4

E. Fan 5

F. Fan 6

G. Fan 7

H. Fan 8

I. Chassis Intrusion

D

Fan Headers

This motherboard has eight fan headers

for CPU/system use. All these 4-pin fans

headers are backward compatible with

the traditional 3-pin fans. However, fan

speed control is only available for 4-pin

fans via IPMI thermal management. See

the table on the right for pin denitions.

Fan Header

Pin Denitions

Pin# Denition

1 Ground

2 +12V

3 Tachometer

4 Pulse Width

Modulation

G

H

I

E

F

A

B

Chapter 2: Installation

2-29

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Serial Ports

A COM port header is located next

to the BMC controller on the mother-

board. See the table on the right for

pin denitions.

Serial (COM) Ports

Pin Denitions

Pin # Denition Pin # Denition

1 DCD 6 DSR

2 RXD 7 RTS

3 TXD 8 CTS

4 DTR 9 RI

5 Ground 10 N/A

A. COM1

A

2-30

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC
1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

A. TPM/Port 80 Header

B. JOH1

TPM Header/Port 80

Trusted Platform Module/Port 80

header, located at JTPM1, provides

TPM support and Port 80 connection.

Use this header to enhance system

performance and data security. See

the table on the right for pin deni-

tions.

TPM/Port 80 Header

Pin Denitions

Pin # Denition Pin # Denition

1 LCLK 2 GND

3 LFRAME# 4 <(KEY)>

5 LRESET# 6 +5V (X)

7 LAD3 8 LAD2

9 +3.3V 10 LAD1

11 LAD0 12 GND

13 SMB_CLK(X) 14 SMB_DAT(X)

15 +3V_DUAL 16 SERIRQ

17 GND 18 CLKRUN# (X)

19 LPCPD#(X) 20 LDRQ# (X)

Overheat LED/Fan Fail

The JOH1 header is used to connect

an LED indicator to provide warnings

of chassis overheating and fan failure.

This LED will blink when a fan failure

occurs. Refer to the tables on right for

pin denitions.

Overheat LED

Pin Denitions

Pin# Denition

1 P3V3

2 OH Active

Low Signal

OH/Fan Fail LED

Status

State Message

Solid Overheat

Blinking (1Hz) Fan Fail

Blinking (0.25Hz) PWRFail

A

B

Chapter 2: Installation

2-31

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

A. T-SGPIO1

B. T-SGPIO2

C. T-SGPIO-S1

T-SGPIO1/2/-S1 Headers

Two T-SGPIO (Serial-Link General Pur-

pose Input/Output) headers (T-SGPIO1/2/-

S1) are located on the motherboard.

These headers support Serial_Link inter-

face for onboard SATA connections. See

the table on the right for pin denitions.

Note: NC= No Connection

T-SGPIO

Pin Denitions

Pin# Denition Pin Denition

1 NC 2 NC

3 Ground 4 Data

5 Load 6 Ground

7 Clock 8 NC

A

B

C

2-32

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE

BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Speaker Header

The speaker header (JSPK1) for a

buzzer can be used to provide audible

indications for various beep codes.

See the table on the right for pin de-

nitions. Refer to the layout below for

the locations of the speaker header.

Speaker Header

Pin Denition

Pin# Denitions

Pin 1 Pos. (+) 5V

Pin 2 Neg. (-) Alarm

Speaker

A

B

DOM Power Connector

The power connectors for SATA

DOM (Disk_On_Module) devices are

located at JSD1 and JSD2. Connect

an appropriate cable here to provide

backup power support for your SATA

DOM devices to retain cache data

during power outage. See the table

on the right for pin denitions.

DOM PWR

Pin Denitions

Pin# Denition

1 +5V

2 Ground

3 Ground

A. Onboard Speaker Header

B. SATA DOM PWR

Chapter 2: Installation

2-33

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

2-8 Jumper Settings

Explanation of Jumpers

To modify the operation of the mother-

board, jumpers can be used to choose

between optional settings. Jumpers create

shorts between two pins to change the

function of the connector. Pin 1 is identied

with a square solder pad on the printed

circuit board. See the motherboard layout

pages for jumper locations.

Note: On two-pin jumpers,

"Closed" means the jumper is

on and "Open" means the jumper

is off the pins.

Connector

Pins

Jumper

Cap

Setting

Pin 1-2 short

3 2 1

3 2 1

GLAN Enable/Disable

JPL1 enables or disables the LAN Port1/

LAN Port2 on the motherboard. See the

table on the right for jumper settings. The

default setting is Enabled.

LAN Enable

Jumper Settings

Jumper Setting Denition

1-2 Enabled (default)

2-3 Disabled

A. GLAN1/GLAN2 Enable

A

2-34

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

CMOS Clear

JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads

to prevent accidental clearing of CMOS. To clear CMOS, use a metal object such

as a small screwdriver to touch both pads at the same time to short the connection.

Always remove the AC power cord from the system before clearing CMOS.

Note 1: For an ATX power supply, you must completely shut down the

system, remove the AC power cord, and then short JBT1 to clear CMOS.

Note 2: Be sure to remove the onboard CMOS Battery before you short

JBT1 to clear CMOS.

Note 3: Clearing CMOS will also clear all passwords.

A. Clear CMOS

B. Watch Dog Enable

Watch Dog Enable/Disable

Watch Dog (JWD1) is a system monitor that will re-

boot the system when a software application hangs.

Close pins 1-2 to reset the system if an application

hangs. Close pins 2-3 to generate a non-maskable

interrupt signal for the application that hangs. See

the table on the right for jumper settings. Watch

Dog must also be enabled in the BIOS.

Watch Dog

Jumper Settings

Jumper Setting Denition

Pins 1-2 Reset (default)

Pins 2-3 NMI

Open Disabled

B

A

Chapter 2: Installation

2-35

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE

BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

A. VGA Enabled

B. BMC Enabled

VGA Enable

Jumper JPG1 allows the user to enable

the onboard VGA connector. The default

setting is 1-2 to enable the connection.

See the table on the right for jumper

settings.

VGA Enable

Jumper Settings

Jumper Setting Denition

1-2 Enabled (Default)

2-3 Disabled

BMC Enable

Jumper JPB1 allows you to enable the

embedded BMC (Baseboard Manage-

ment) Controller to provide IPMI/KVM

support on the motherboard. See the

table on the right for jumper settings.

BMC Enable

Jumper Settings

Jumper Setting Denition

Pins 1-2 BMC Enabled (Default)

Pins 2-3 Disabled

A

B

2-36

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE

BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Management Engine (ME) Recovery

Use Jumper JPME1 to select ME Firm-

ware Recovery mode, which will limit

resource allocation for essential system

operation only in order to maintain nor-

mal power operation and management.

In the single operation mode, online

upgrade will be available via Recovery

mode. See the table on the right for

jumper settings.

ME Recovery

Jumper Settings

Jumper Setting Denition

1-2 Normal (Default)

2-3 ME Recovery

Manufacture Mode Select

Close pins 2 and 3 of Jumper JPME2 to

bypass SPI ash security and force the

system to operate in the Manufacture

Mode, allowing the user to flash the

system rmware from a host server for

system setting modications. See the

table on the right for jumper settings.

ME Mode Select

Jumper Settings

Jumper Setting Denition

1-2 Normal (Default)

2-3 Manufacture Mode

A. JPME1

B. JPME2

A

B

Chapter 2: Installation

2-37

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE

BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

2-9 Onboard LED Indicators

A. LAN1/2 LEDs

B. IPMI LAN LEDs

IPMI Dedicated LAN LEDs

In addition to LAN 1/LAN 2, an IPMI Dedicated

LAN is also located on the I/O Backplane of

the motherboard. The amber LED on the

right indicates activity, while the green LED

on the left indicates the speed of the con-

nection. See the table on the right for more

information.

Link LED Activity LED

IPMI LAN

IPMI LAN Link LED (Left) &

Activity LED (Right)

Color/State Denition

Link (Left) Green: Solid 100 Mbps

Activity (Right) Amber: Blinking Active

LAN LEDs

There are two LAN ports on the motherboard. Each Ethernet LAN port has two

LEDs. The Yellow LED on the right indicates activity. The LED on the left is the Link

LED, which can be green, amber or off to indicate the speed of the connection. See

the tables below for more information.

Activity LED

Link LED

GLAN/10G LAN (TLAN) Activity

LED Settings (Right)

Color Status Denition

Green Flashing Active

Rear View (when facing the
rear side of the chassis)

A

B

LAN 1/LAN 2 Link LED

(Left) LED State

LED Color Denition

Off 10 Mbps, 100

Mbps, or No
Connection

Amber 1 Gbps

Green 10 Gbps

2-38

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE
10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

Onboard Power LED

An Onboard Power LED is located at LE1

on the motherboard. When this LED is on,

the system is on. Be sure to turn off the

system and unplug the power cord before

removing or installing components. See

the table on the right for more information.

Onboard PWR LED Indicator (LE1)

LED Settings

LED Color Denition

Off System Off (PWR cable

not connected)

Green System On

Green:
Flashing
Quickly

ACPI S1 State

Green:
Flashing
Slowly

ACPI S3 (STR) State

A. PWR LED

B. BMC Heartbeat LED

BMC Heartbeat LED

A BMC Heartbeat LED is located at DM1

on the motherboard. When DM1 is blink-

ing, BMC functions normally. See the

table on the right for more information.

BMC Heartbeat LED

Status

Color/State Denition

Green:
Blinking

BMC: Normal

A

B

Chapter 2: Installation

2-39

SW1

JPW10

J21

SP1

JBT1

JITP0

JSD2

JSD1

JTPM1

I_SATA1

I-SATA0

I-SATA2

I_SATA3

JF1

JWD1

JBR1

JPME1

JPL1

JPG1

J29

JPB1

J30

LE1

LE4

DM1

FAN8

FAN6

FAN7

FAN5

FAN1

FAN3

FAN4

JSPK1

JL1

JOH1

JPLD1

JPW18

JPW17

JPW6

JPW12

JPW4

JPW5

JPW3

JPW13

JPW14

JPW15

JPW16

T-SGPIO2

T-SGPIO1

T-SGPIO-S1

BT1

JPW24

JPW23

JPW22

JPW21

BIOS
LICENSE

10G MAC CODE

10G SAN MAC

1G MAC CODE

IPMI CODE
BAR CODE

P2-DIMME1

P2-DIMME2

P2-DIMME3

P2-DIMMF1

P2-DIMMF2

P2-DIMMF3

USB10/11

USB2/3

CPU1

P1-DIMMC1

P1-DIMMC2

P1-DIMMC3

P1-DIMMD1

P1-DIMMD2

P1-DIMMD3

LAN2

LAN1

CPU2

P1-DIMMB3

P1-DIMMB2

VGA1

P1-DIMMB1

P2-DIMMH3

COM1

P1-DIMMA3

P1-DIMMA2

P2-DIMMH2

P1-DIMMA1

P2-DIMMH1

IPMI_LAN

P2-DIMMG3

USB0/1

P2-DIMMG2

P2-DIMMG1

REV:1.00

X9DRG-OF-CPU

S_SATA1

FAN2

JPW7

I_SATA4

I_SATA5

S_SATA2

S_SATA2

S_SATA3

JPME2

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

USB8/9

PCH

BIOS

LAN
CTRL

BMC

BMC Firmware

CLK Chip

USB6

J34

J33

J32

J31

J

Note: For more information on SATA HostRAID conguration, please refer

to the Intel SATA HostRAID User's Guide posted on our website @ http://

www.supermicro.com.

Serial ATA

Pin Denitions

Pin# Denition

1 Ground

2 TX_P

3 TX_N

4 Ground

5 RX_N

6 RX_P

7 Ground

A. I-SATA0

B. I-SATA1

C. I-SATA2

D. I-SATA3

E. I-SATA4

F. I-SATA5

G. S-SATA1

H. S-SATA2

I. S-SATA3

J. S-SATA4

Serial ATA Ports

There are two SATA 3.0 Ports

(I-SATA0/1) and four SATA 2.0 ports

(I-SATA2-I-SATA5) on the moth-

erboard. There are also four S-

SATA 2.0 ports (S-SATA1-S-SATA4).

These ports provide serial-link signal

connections, which are faster than

the connections of Parallel ATA.

See the table on the right for pin

denitions.

2-10 Serial ATA Connections

I

C

A

B

E

D

F

G

H

2-40

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Notes

3-1

Chapter 3: Troubleshooting

Chapter 3

Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all

of the procedures below and still need assistance, refer to the ‘Technical Support

Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.

Note: Always disconnect the power cord before adding, changing or installing any

hardware components.

Before Power On

1. Make sure that there are no short circuits between the motherboard and

chassis.

2. Disconnect all ribbon/wire cables from the motherboard, including those for

the keyboard and mouse.

3. Remove all add-on cards.

4. Install CPU 1 rst (making sure it is fully seated) and connect the front panel

connectors to the motherboard.

No Power

1. Make sure that there are no short circuits between the motherboard and the

chassis.

2. Make sure that the ATX power connectors are properly connected

3. Check that the 115V/230V switch on the power supply is properly set, if avail-

able.

4. Turn the power switch on and off to test the system, if applicable.

5. The battery on your motherboard may be old. Check to verify that it still sup-

plies ~3VDC. If it does not, replace it with a new one.

3-2

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

No Video

1. If the power is on, but you have no video, remove all the add-on cards and

cables.

2. Use the speaker to determine if any beep codes exist. Refer to Appendix A

for details on beep codes.

System Boot Failure

If the system does not display POST or does not respond after the power is turned

on, check the following:

1. Check for any error beep from the motherboard speaker.

•If there is no error beep, try to turn on the system without DIMM modules in-

stalled. If there is still no error beep, try to turn on the system again with only

one processor installed in CPU Socket#1. If there is still no error beep, replace

the motherboard.

•If there are error beeps, clear the CMOS settings by unplugging the power

cord and contacting both pads on the CMOS Clear Jumper (JBT1). (Refer to

Chapter 2.)

2. Remove all components from the motherboard, especially the DIMM mod-

ules. Make sure that the system's power is on, and memory error beeps are

activated.

3. Turn on the system with only one DIMM module installed. If the system

boots, check for bad DIMM modules or slots by following the Memory Errors

Troubleshooting procedure in this Chapter.

Losing the System’s Setup Conguration

1. Make sure that you are using a high quality power supply. A poor quality

power supply may cause the system to lose the CMOS setup information.

Refer to Chapter 2 for details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still sup-

plies ~3VDC. If it does not, replace it with a new one.

3. If the above steps do not x the Setup Conguration problem, contact your

vendor for repairs.

3-3

Chapter 3: Troubleshooting

Memory Errors

When a No-Memory Beep Code is issued by the system, check the following:

1. Make sure that the memory modules are compatible with the system and that

the DIMM modules are properly and fully installed. (For memory compatibility,

refer to the Memory Compatibility Chart posted on our website @ http://www.

supermicro.com.)

2. Check if different speeds of DIMMs have been installed. It is strongly recom-

mended that you use the same RAM speed for all DIMMs in the system.

3. Make sure that you are using the correct type of Registered (RDIMM)/Load

Reduced (LRDIMM) ECC or Unbuffered (UDIMM) ECC/Non-ECC DDR3

800/1066/1333/1600/1600 MHz 4-channel memory modules recommended by

the manufacturer.

4. modules recommended by the manufacturer.

5. Check for bad DIMM modules or slots by swapping a single module among

all memory slots and check the results.

6. Make sure that all memory modules are fully seated in their slots. Follow the

instructions given in section 2-5 of Chapter 2.

7. Please follow the instructions given in the DIMM Population Tables listed in

Section 2-5 to install your memory modules.

When the System Becomes Unstable

A. The system becomes unstable during or after OS installation

When the system becomes unstable during or after OS installation, check the fol-

lowing:

1. CPU/BIOS support: Make sure that your CPU is supported, and you have the

latest BIOS installed in your system.

2. Memory support: Make sure that the memory modules are supported by test-

ing the modules using memtest86 or a similar utility.

Note: Refer to the product page on our website http://www.supermicro.

com for memory and CPU support and updates.

3. HDD support: Make sure that all hard disk drives (HDDs) work properly. Re-

place the bad HDDs with good ones.

3-4

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

4. System cooling: Check system cooling to make sure that all heatsink fans,

and CPU/system fans, etc., work properly. Check Hardware Monitoring set-

tings in the BIOS to make sure that the CPU and System temperatures are

within the normal range. Also check the front panel Overheat LED, and make

sure that the Overheat LED is not on.

5. Adequate power supply: Make sure that the power supply provides adequate

power to the system. Make sure that all power connectors are connected.

Please refer to our website for more information on minimum power require-

ment.

6. Proper software support: Make sure that the correct drivers are used.

B. The system becomes unstable before or during OS installation

When the system becomes unstable before or during OS installation, check the

following:

1. Source of installation: Make sure that the devices used for installation are

working properly, including boot devices such as CD/DVD disc, CD/DVD-

ROM.

2. Cable connection: Check to make sure that all cables are connected and

working properly.

3. Using minimum conguration for troubleshooting: Remove all unnecessary

components (starting with add-on cards rst), and use minimum conguration

(with a CPU and a memory module installed) to identify the trouble areas.

Refer to the steps listed in Section A above for proper troubleshooting proce-

dures.

4. Identifying bad components by isolating them: If necessary, remove a compo-

nent in question from the chassis, and test it in isolation to make sure that it

works properly. Replace a bad component with a good one.

5. Check and change one component at a time instead of changing several

items at the same time. This will help isolate and identify the problem.

6. To nd out if a component is good, swap this component with a new one to

see if the system will work properly. If so, then the old component is bad.

You can also install the component in question in another system. If the new

system works, the component is good and the old system has problems.

3-5

Chapter 3: Troubleshooting

3-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, please

note that as a motherboard manufacturer, Supermicro also sells motherboards

through its channels, so it is best to rst check with your distributor or reseller for

troubleshooting services. They should know of any possible problem(s) with the

specic system conguration that was sold to you.

1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked

Question' (FAQ) sections in this chapter or see the FAQs on our website

(http://www.supermicro.com/) before contacting Technical Support.

2. BIOS upgrades can be downloaded from our website (http://www.supermicro.

com).

3. If you still cannot resolve the problem, include the following information when

contacting Supermicro for technical support:

•Motherboard model and PCB revision number

•BIOS release date/version (This can be seen on the initial display when your

system rst boots up.)

•System conguration

4. An example of a Technical Support form is on our website at (http://www.

supermicro.com).

•Distributors: For immediate assistance, please have your account number ready

when placing a call to our technical support department. We can be reached by

e-mail at [e-mail].

3-6

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Proper Battery Disposal

Warning: Please handle used batteries carefully. Do not damage the battery in any

way; a damaged battery may release hazardous materials into the environment. Do

not discard a used battery in the garbage or a public landll. Please comply with the

regulations set up by your local hazardous waste management agency to dispose of

your used battery properly.

Battery Installation

1. To install an onboard battery, follow the steps 1 & 2 above and continue

below:

2. Identify the battery's polarity. The positive (+) side should be facing up.

3. Insert the battery into the battery holder and push it down until you hear a

click to ensure that the battery is securely locked.

Warning: When replacing a battery, be sure to only replace it with the same type.

3-3 Battery Removal and Installation

Battery Removal

To remove the onboard battery, follow the steps below:

1. Power off your system and unplug your power cable.

2. Locate the onboard battery as shown below.

3. Using a tool such as a pen or a small screwdriver, push the battery lock out-

wards to unlock it. Once unlocked, the battery will pop out from the holder.

4. Remove the battery.

OR

3-7

Chapter 3: Troubleshooting

3-4 Frequently Asked Questions

Question: What are the various types of memory that my motherboard can

support?

Answer: The motherboard supports Registered (RDIMM)/Load Reduced (LRDIMM)

ECC or Unbuffered (UDIMM) ECC/Non-ECC DDR3 4-channel memory. To enhance

memory performance, do not mix memory modules of different speeds and sizes.

Please follow all memory installation instructions given on Section 2-4 in Chapter 2.

Question: How do I update my BIOS?

It is recommended that you do not upgrade your BIOS if you are not experiencing

any problems with your system. Updated BIOS les are located on our website

at http://www.supermicro.com. Please check our BIOS warning message and the

information on how to update your BIOS on our website. Select your motherboard

model and download the BIOS le to your computer. Also, check the current BIOS

revision to make sure that it is newer than your BIOS before downloading. You can

choose from the zip le and the .exe le. If you choose the zip BIOS le, please

unzip the BIOS le onto a bootable USB device. Run the batch le using the format

AMI.bat lename.rom from your bootable USB device to ash the BIOS. Then, your

system will automatically reboot.

Warning: Do not shut down or reset the system while updating the BIOS to prevent

possible system boot failure!)

Note: The SPI BIOS chip used on this motherboard cannot be removed.

Send your motherboard back to our RMA Department at Supermicro for

repair. For BIOS Recovery instructions, please refer to the AMI BIOS

Recovery Instructions posted at http://www.supermicro.com.

Question: How do I handle the used battery?

Answer: Please handle used batteries carefully. Do not damage the battery in any

way; a damaged battery may release hazardous materials into the environment. Do

not discard a used battery in the garbage or a public landll. Please comply with the

regulations set up by your local hazardous waste management agency to dispose

of your used battery properly. (Refer to Section 3-3 on Page 3-6.)

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

3-5 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before

any warranty service will be rendered. You can obtain service by calling your ven-

dor for a Returned Merchandise Authorization (RMA) number. When returning the

motherboard to the manufacturer, the RMA number should be prominently displayed

on the outside of the shipping carton, and the shipping package is mailed prepaid

or hand-carried. Shipping and handling charges will be applied for all orders that

must be mailed when service is complete. For faster service, you can also request

a RMA authorization online (http://www.supermicro.com/RmaForm/).

This warranty only covers normal consumer use and does not cover damages in-

curred in shipping or from failure due to the alternation, misuse, abuse or improper

maintenance of products.

During the warranty period, contact your distributor rst for any product problems.

Chapter 4: AMI BIOS

4-1

Chapter 4

BIOS

4-1 Introduction

This chapter describes the AMI BIOS setup utility for the X9DRG-O(T)F-CPU/

X9DRG-O-PCIE Platform. It also provides the instructions on how to navigate the

AMI BIOS setup utility screens. The AMI ROM BIOS is stored in a Flash EEPROM

and can be easily updated.

Starting BIOS Setup Utility

To enter the AMI BIOS setup utility screens, press the <Del> key while the system

is booting up.

Note: In most cases, the <Del> key is used to invoke the AMI BIOS setup

screen. There are a few cases when other keys are used, such as <F3>,

<F4>, etc.

Each main BIOS menu option is described in this manual. The Main BIOS setup

menu screen has two main frames. The left frame displays all the options that can

be congured. Grayed-out options cannot be congured. Options in blue can be

congured by the user. The right frame displays the key legend. Above the key

legend is an area reserved for informational text related to the option currently

selected in the left frame.

Note: The AMI BIOS has default informational messages built in. The

manufacturer retains the option to include, omit, or change any of these

informational messages.

The AMI BIOS setup utility uses a key-based navigation system called "hot keys."

Most of the AMI BIOS setup utility "hot keys" can be used at any time during setup

navigation. These keys include <F3>, <F4>, <Enter>, <ESC>, arrow keys, etc.

Note 1: In this section, options printed in Bold are default settings.

Note 2: <F3> is used to load optimal default settings. <F4> is used to save

the settings and exit the setup utility.

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

How To Change the Conguration Data

The conguration data that determines the system parameters may be changed by

entering the AMI BIOS setup utility. This setup utility can be accessed by pressing

<Delete> at the appropriate time during system boot.

Note: For AMI UEFI BIOS Recovery, please refer to the UEFI BIOS Recov-

ery User Guide posted @ http://www.supermicro.com/support/manuals/.

Starting the Setup Utility

Normally, the only visible Power-On Self-Test (POST) routine is the memory test.

As the memory is being tested, press the <Delete> key to enter the main menu of

the AMI BIOS setup utility. From the main menu, you can access the other setup

screens. An AMI BIOS identication string is displayed at the left bottom corner of

the screen below the copyright message.

Warning: Do not upgrade the BIOS unless your system has a BIOS-related issue.

Flashing the wrong BIOS can cause irreparable damage to the system. In no event

shall the manufacturer be liable for direct, indirect, special, incidental, or consequential

damage arising from a BIOS update. If you have to update the BIOS, do not shut down

or reset the system while the BIOS is being updated to avoid possible boot failure.

4-2 Main Setup

When you rst enter the AMI BIOS setup utility, you will enter the Main setup screen.

You can always return to the Main setup screen by selecting the Main tab on the

top of the screen. The Main BIOS setup menu screen is shown below.

Chapter 4: AMI BIOS

4-3

The AMI BIOS main menu displays the following information:

System Date

This item displays the system date in Day MM/DD/YYYY format (e.g. Wed

01/15/2014).

System Time

This item displays the system time in HH:MM:SS format (e.g. 15:32:52).

Supermicro X9DRG-O(T)F

Version

This item displays the SMC version of the BIOS ROM used in this system.

Build Date

This item displays the date that the BIOS ROM was built.

Memory Information

Total Memory

This displays the amount of memory that is available in the system.

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

4-3 Advanced Setup Congurations

Use the arrow keys to select Advanced setup menu and press <Enter> to access

the following submenu items.

Boot Feature

Quiet Boot

This feature allows the user to select the bootup screen display between POST

messages and the OEM logo. Select Disabled to display the POST messages.

Select Enabled to display the OEM logo instead of the normal POST messages.

The options are Enabled and Disabled.

AddOn ROM Display Mode

Use this item to set the display mode for the Option ROM. Select Keep Current to

use the current AddOn ROM Display setting. Select Force BIOS to use the Option

ROM display mode set by the system BIOS. The options are Force BIOS and

Keep Current.

Bootup Num-Lock

Use this feature to set the Power-on state for the Num Lock key. The options are

Off and On.

Wait For 'F1' If Error

Select Enabled to force the system to wait until the 'F1' key is pressed if an error

occurs. The options are Disabled and Enabled.

Chapter 4: AMI BIOS

4-5

Interrupt 19 Capture

Interrupt 19 is the software interrupt that handles the boot disk function. When this

item is set to Enabled, the ROM BIOS of the host adaptors will "capture" Interrupt 19

at bootup and allow the drives that are attached to these host adaptors to function

as bootable disks. If this item is set to Disabled, the ROM BIOS of the host adap-

tors will not capture Interrupt 19, and the drives attached to these adaptors will not

function as bootable devices. The options are Enabled and Disabled.

Re-try Boot

Use this item to select the type of the bootable device that the BIOS will continuously

try to boot the system from. The options are Disabled, Legacy Boot, and EFI Boot.

Power Conguration

Watch Dog Function

If enabled, the Watch Dog timer will allow the system to automatically reboot when

a non-recoverable error occurs that lasts for more than ve minutes. The options

are Enabled and Disabled.

Power Button Function

If this feature is set to Instant Off, the system will power off immediately as soon

as the user presses the power button. If this feature is set to 4 Seconds Override,

the system will power off when the user presses the power button for 4 seconds or

longer. The options are Instant Off and 4 Seconds Override.

Restore on AC Power Loss

Use this feature to set the power state after a power outage. Select Stay Off for the

system power to remain off after a power loss. Select Power On for the system

power to be turned on after a power loss. Select Last State to allow the system

to resume its last state before a power loss. The options are Power On, Stay Off,

and Last State.

CPU Conguration

This submenu displays the CPU information as detected by the BIOS. It also allows

the user to congure CPU settings.

Socket 1 CPU Information/Socket 2 CPU Information

This submenu displays the following information regarding the CPU installed in

Socket 1 or Socket 2.

•Type of CPU

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

•CPU Signature

•Microcode Patch

•CPU Stepping

•Max (Maximum) CPU Speed

•Min (Minimum) CPU Speed

•Processor Cores

•Intel HT (Hyper-Threading) Technology

•Intel VT-x Technology

•Intel SMX Technology

•L1 Data Cache

•L1 Code Cache

•L2 Cache

•L3 Cache

CPU Speed

This item displays the speed of the CPU installed in the Socket selected.

64-bit

This item indicates if 64-bit technology is supported by the CPU installed in the

socket specied.

Clock Spread Spectrum

Select Enable to enable Clock Spread Spectrum support, which will allow the BIOS

to monitor and attempt to reduce the level of Electromagnetic Interference caused

by the components when needed. The options are Disabled and Enabled.

RTID (Record Types IDs)

Use this item to congure the RTID setting which determines how the system

memory should be accessed. Select Optimal for all normal applications and bench-

marking operations. Select Alternate for I/O-intensive applications that require direct

access to the system memory. The options are Optimal and Alternate.

Chapter 4: AMI BIOS

4-7

Hyper-threading

Select Enabled to support Intel Hyper-threading Technology to enhance CPU per-

formance. The options are Enabled and Disabled.

Active Processor Cores

Set to Enabled to use a processor's second core and above. (Please refer to Intel's

website for more information.) The options are All, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11.

Limit CPUID Maximum

This feature allows the user to set the maximum CPU ID value. Enable this function

to boot the legacy operating systems that cannot support processors with extended

CPUID functions. The options are Enabled and Disabled (for the Windows OS).

Execute-Disable Bit (Available if supported by the OS & the CPU)

Select Enabled to enable the Execute Disable Bit which will allow the processor

to designate areas in the system memory where an application code can execute

and where it cannot, thus preventing a worm or a virus from ooding illegal codes

to overwhelm the processor or damage the system during an attack. The default is

Enabled. (Refer to Intel and Microsoft Web sites for more information.)

Intel® AES-NI

Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc-

tions (NI) technology to ensure data security. The options are Enabled and Disabled.

MLC Streamer Prefetcher (Available when supported by the CPU)

If set to Enabled, the prefetcher for the MLC (mid-level cache) streamer will prefetch

streams of data and instructions from the main memory to the L2 cache to improve

CPU performance. The options are Disabled and Enabled.

MLC Spatial Prefetcher (Available when supported by the CPU)

If this feature is set to Disabled, the CPU prefetches the cache line for 64 bytes.

If this feature is set to Enabled the CPU fetches both cache lines for 128 bytes as

comprised. The options are Disabled and Enabled.

DCU Streamer Prefetcher (Available when supported by the CPU)

Select Enabled for the Data Cache Unit (DCU) prefetcher to prefetch L1 data for

CPU use in an effort to speed up data accessing and processing in the DCU. The

options are Disabled and Enabled.

DCU IP Prefetcher

Select Enabled to activate the DCU (Data Cache Unit) IP prefetcher so that it will

prefetch IP addresses to improve network connectivity and system performance.

The options are Enabled and Disabled.

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Intel® Virtualization Technology (Available when supported by the CPU)

Select Enabled to support Intel Virtualization Technology, which will allow one

platform to run multiple operating systems and applications simultaneously in

multiple partitions, creating multiple "virtual" systems in one physical computer.

The options are Enabled and Disabled.

Note: If there is any change to this setting, you will need to reboot the

system for the change to take effect. Please refer to Intel’s website for

detailed information.)

PPIN Support (Available when supported by the CPU)

Select Enabled to enable Protected Processor Inventory Number (PPIN) support,

which will allow the Ivy Bridge server processors to return 64-bit ID numbers. The

options are Enabled and Disabled.

 CPU Power Management Conguration

This submenu allows the user to congure the following CPU Power Management

settings.

Power Technology

Select Energy Efciency to support power-saving mode. Select Custom to

customize system power settings. Select Disabled to disable power-saving fea-

tures. Select Max Performance to congure power mode to allow for maximum

system performance. The options are Disabled, Energy Efcient, Custom and

Max Performance. If the option is set to Custom, the following items will display:

EIST (Available when Power Technology is set to Custom)

Select Enabled to support EIST (Enhanced Intel SpeedStep Technology)

which will allow the system to automatically adjust processor voltage and

core frequency to reduce power consumption and heat dissipation. The op-

tions are Disabled and Enabled.

Turbo Mode (Available when Power Technology is set to Custom
and EIST is enabled)

This feature allows processor cores to run faster than marked frequency in

specic conditions. The options are Disabled and Enabled.

C1E Support (Available when Power Technology is set to Custom)

Select Enabled to enable Enhanced C1 Power State to boost system per-

formance. The options are Enabled and Disabled.

Chapter 4: AMI BIOS

4-9

CPU C3 Report (Available when Power Technology is set to Custom)

Select Enabled to allow the BIOS to report the CPU C3 State (ACPI C2) to

the operating system. During the CPU C3 State, the CPU clock generator

is turned off. The options are Enabled and Disabled.

CPU C6 Report (Available when Power Technology is set to Custom)

Select Enabled to allow the BIOS to report the CPU C6 State (ACPI C3) to

the operating system. During the CPU C6 State, the power to all cache is

turned off. The options are Enabled and Disabled.

Package C State limit (Available when Power Technology is set to

Custom)

This feature allows the user to set the limit on the C-State package register.

The options are C0, C2, C6, and No Limit.

Energy/Performance Bias

Use this feature to select an appropriate fan setting to achieve maximum system

performance (with maximum cooling) or maximum energy efciency (with maxi-

mum power saving). The fan speeds are controlled by the rmware management

via IPMI 2.0. The options are Performance, Balanced Performance, Balanced

Energy, and Energy Efcient.

Factory Long Duration Power Limit

This item displays the power limit (in watts) set by the manufacturer during which

long duration power is maintained.

Long Duration Power Limit

This item displays the power limit (in watts) set by the user during which long

duration power is maintained. The default setting is 0.

Factory Long Duration Maintained

This item displays the period of time (in seconds) set by the manufacturer during

which long duration power is maintained.

Long Duration Maintained

This item displays the period of time (in seconds) during which long duration

power is maintained. The default setting is 0.

4-10

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Recommended Short Duration Power Limit

This item displays the short duration power settings (in watts) recommended by

the manufacturer.

Short Duration Power Limit

This item displays the time period during which short duration power (in watts)

is maintained. The default setting is 0.

Chipset Conguration

North Bridge

This feature allows the user to congure the settings for the Intel North Bridge.

Integrated IO Conguration

Intel® VT-d

Select Enabled to enable Intel Virtualization Technology support for Direct I/O
VT-d by reporting the I/O device assignments to the VMM (Virtual Machine

Monitor) through the DMAR ACPI Tables. This feature offers fully-protected I/O

resource sharing across Intel platforms, providing greater reliability, security

and availability in networking and data-sharing. The options are Enabled and

Disabled.

Ageing Timer Rollover

Use this feature to determine how long the Ageing timer should be. The Ageing

timer is used to break the deadlock of PCI-E bus transactions to resume normal

system operations. The options are Disabled, 32 us, 128 us, and 512 us.

Intel® I/OAT

Select Enabled to enable Intel I/OAT (I/O Acceleration Technology), which signi-

cantly reduces CPU overhead by leveraging CPU architectural capabilities and

freeing up system resources for use of other tasks. The options are Disabled

and Enabled.

DCA Support

When set to Enabled, this feature uses Intel's DCA (Direct Cache Access)

Technology to improve data transfer efciency. The options are Enabled and

Disabled.

Chapter 4: AMI BIOS

4-11

MMCFG BASE

This feature determines the lowest base address that can be assigned to PCI

devices. The lower the address, the less system memory is available (for a 32-bit

OS). The higher the address, the less resources are allocated to PCI devices.

The options are 0x80000000, 0xA0000000, and 0xC0000000.

IIO 1 PCIe Port Bifurcation Control (Available when a PCI-E device is
installed)

This submenu congures the following Port-Bifurcation control settings which will

determine how the PCI-Express lanes will be distributed between PCI-E ports.

CPU1 Slot6 PCI-E 3.0 x8 Link Speed

Use this item to select the desired type of PCI-Exp Generation support for the

slot indicated above. The options are GEN1, GEN2, and GEN3.

CPU1 Slot8/9 PCI-E 3.0 x16 Link Speed

Use this item to select the desired type of PCI-Exp Generation support for the

slot indicated above. The options are GEN1, GEN2, and GEN3.

CPU1 Slot10/11 PCI-E 3.0 x16 Link Speed

Use this item to select the desired type of PCI-Exp Generation support for the

slot indicated above. The options are GEN1, GEN2, and GEN3.

IIO 2 PCIe Port Bifurcation Control (Available when a PCI-E device is
installed)

This submenu congures the following Port-Bifurcation control settings which will

determine how the PCI-Express lanes will be distributed between PCI-E ports..

CPU2 Slot5 PCI-E 3.0 x8 Link Speed

Use this item to select the desired type of PCI-Exp Generation support for the

slot indicated above. The options are GEN1, GEN2, and GEN3.

CPU2 Slot3/4 PCI-E 3.0 x16 Link Speed

Use this item to select the desired type of PCI-Exp Generation support for the

slot indicated above. The options are GEN1, GEN2, and GEN3.

CPU2 Slot1/2 PCI-E 3.0 x16 Link Speed

Use this item to select the desired type of PCI-Exp Generation support for the

slot indicated above. The options are GEN1, GEN2, and GEN3.

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

QPI Conguration

Current QPI Link Speed

This item displays the speed of the QPI Link.

Current QPI Link Frequency

This item displays the frequency of the QPI Link.

Isoc

Select Enabled to enable Isochronous support to meet QoS (Quality of Service)

requirements. This feature is especially important for Intel Virtualization technol-

ogy support. The options are Enabled and Disabled.

QPI (Quick Path Interconnect) Link Speed Mode

Use this feature to set data transfer rate for QPI Link connections. The options

are Fast and Slow.

QPI Link Frequency Select

Use this feature to set QPI Link frequency. The options are Auto, 6.4 GT/s, 7.2

GT/s, and 8.0 GT/s.

DIMM Conguration

This section displays the following DIMM information.

Memory Mode

This item displays the current memory mode.

Current Memory Speed

This item displays the current memory speed.

Mirroring

This item displays if memory mirroring is supported by the motherboard. Memory

mirroring creates a duplicate copy of the data stored in the memory to enhance

data security.

Sparing

This item displays if memory sparing is supported by the motherboard. Memory

sparing enhances system performance.

Chapter 4: AMI BIOS

4-13

DIMM Information

The status of a memory module is displayed as detected by the BIOS.

Memory Mode

When Independent is selected, all DIMMs are available to the operating system.

When Mirroring is selected, the motherboard maintains two identical copies of all

data in memory for data backup. When Lockstep is selected, the motherboard

uses two areas of memory to run the same set of operations in parallel. The

options are Independent, Mirroring, and Lockstep.

DRAM RAPL Mode

RAPL (Running Average Power Limit) is used to set the power consumption

limit for a processor4. The options are DRAM RAPL MODE0, DRAM RAPL

MODE1, and Disabled.

DDR Speed

Use this feature to force a DDR3 memory module to run at a frequency other

than what is specied by the manufacturer. The options are Auto, Force DDR3

800, Force DDR3 1066, Force DDR3 1333, Force DDR3 1600 and Force SPD.

Channel Interleaving

Use this feature to select channel-interleaving mode for system memory mod-

ules. The options are Auto, 1 Way, 2 Way, 3, Way, and 4 Way.

Rank Interleaving

Use this feature to select rank-interleaving mode for system memory modules.

The options are Auto, 1 Way, 2 Way, 4, Way, and 8 Way.

Patrol Scrub

Patrol Scrubbing is a process that allows the CPU to correct correctable memory

errors detected on a memory module and send the correction to the requestor

(the original source). When this item is set to Enabled, read-and-write will be

performed every 16K cycles per cache line if there is no delay caused by internal

processing. The options are Enabled and Disabled.

Demand Scrub

Demand Scrubbing is a process that allows the CPU to correct correctable

memory errors found on a memory module. When the CPU or I/O issues a

demand-read command, and the read data from memory turns out to be a

correctable error, the error is corrected and sent to the requestor (the original

source). Memory is updated as well. Select Enabled to use Demand Scrubbing

for ECC memory correction. The options are Enabled and Disabled.

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Data Scrambling

Select Enabled to enable data scrambling to ensure data security and integrity.

The options are Disabled and Enabled.

Device Tagging

Select Enabled to support device tagging which will allow the BIOS to tag a

memory device that generates a stuck-bit or a hard error. The options are Dis-

abled and Enabled.

Thermal Throttling

Throttling improves system reliability, availability and serviceability (RAS), and

reduces CPU power consumption via automatic voltage control when the proces-

sor is idle. The options are Disabled and CLTT (Closed Loop Thermal Throttling).

Double Refresh

Select Enabled to support memory double-refreshing under high temperatures to

ensure memory stability. The options are Disabled, Auto, and Enabled.

South Bridge

This feature allows the user to congure the settings for the Intel PCH chip.

PCH Information

This feature displays the following PCH information.

Name: This item displays the name of the PCH chip.

Stepping: This item displays the PCH stepping.

USB Devices: This item displays the USB devices detected by the BIOS.

All USB Devices

Select Enabled to enable all USB ports and devices. The options are Disabled

and Enabled.

EHCI Controller 1, EHCI Controller 2 (Available when All USB Devices are
set to Enabled)

Select Enabled to enable EHCI (Enhanced Host Controller Interface) Controller 1

or Controller 2. The options are Disabled and Enabled.

Legacy USB Support (Available when USB Functions is not Disabled)

Select Enabled to support legacy USB devices. Select Auto to disable legacy sup-

port when legacy USB devices are not present. Select Disabled to make all USB

Chapter 4: AMI BIOS

4-15

devices available for EFI (Extensive Firmware Interface) applications only. The

settings are Disabled, Enabled and Auto.

Port 60/64 Emulation

Select Enabled to enable I/O port 60h/64h emulation support for a legacy USB

keyboard to be supported by the operating system that does not recognize a legacy

USB device. The options are Disabled and Enabled.

EHCI Hand-Off

This item is for operating systems that do not support Enhanced Host Controller

Interface (EHCI) hand-off. When this feature is enabled, EHCI ownership change

will be claimed by the EHCI driver. The options are Disabled and Enabled.

SATA Conguration

When this submenu is selected, the AMI BIOS automatically detects the presence

of IDE or SATA devices and displays the following items.

SATA Port0~SATA Port5: The AMI BIOS displays the status of each SATA port

as detected by the BIOS.

SATA Mode

Use this feature to congure SATA mode for a selected SATA port. The options

are Disabled, IDE Mode, AHCI Mode, and RAID Mode. The following items will be

displayed pending on your selection:

IDE Mode

The following items are displayed when IDE Mode is selected:

Serial-ATA (SATA) Controller 0~1

Use this feature to activate or deactivate the SATA controller, and set the

compatibility mode. The options are Disabled, Enhanced, and Compatible.

The default for SATA Controller 0 is Compatible. The default of SATA Con-

troller 1 is Enhanced.

AHCI Mode

The following items are displayed when the AHCI Mode is selected.

Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the

power usage of the SATA link. The controller will put the link in a low power

mode during extended periods of I/O inactivity, and will return the link to

4-16

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

an active state when I/O activity resumes. The options are Enabled and

Disabled.

Port 0~5 Hot Plug

Select Enabled to enable hot-plugging support for a particular port, which will

allow the user to change a hardware component or device without shutting

down the system. The options are Enabled and Disabled.

Port 0~5 Staggered Spin Up

Select Enabled to enable Staggered Spin-up support to prevent excessive

power consumption caused by spinning-up of multiple devices simultane-

ously. The options are Enabled and Disabled.

RAID Mode

The following items are displayed when RAID Mode is selected:

SATA RAID Option ROM/UEFI Driver

Use this feature to enable the onboard SATA Option ROM or EFI driver. The

options are Enabled and Disabled.

Port 0~5 Hot Plug

Select Enabled to enable hot-plugging support for the particular port which

will allow the user to replace a device without shutting down the system.

The options are Disabled and Enabled.

SCU (Storage Control Unit) Conguration

Storage Controller Unit

Select Enabled to support SCU storage devices. The options are Disabled and

Enabled.

SCU RAID Option ROM/UEFI Driver

Select Enabled to support the onboard SCU Option ROM to boot up the system via

a storage device or from the UEFI driver. The options are Disabled and Enabled.

SCU Port 0-SCU Port 3: The AMI BIOS will automatically detect the onboard SCU

devices and display the status of each SCU device as detected.

Chapter 4: AMI BIOS

4-17

PCIe/PCI/PnP Conguration

Launch Storage OpROM Policy

Use this feature to select the Option ROM to boot the system when there are multiple

Option ROMs available in the system. The options are UEFI only and Legacy only.

PCI Latency Timer

Use this feature to set the latency timer of each PCI device installed on a PCI bus.

Select 64 to set the PCI latency to 64 PCI clock cycles. The options are 32, 64,

96, 128, 160, 192, 224 and 248.

PERR# Generation

Select Enabled to allow a PCI device to generate a PERR number for a PCI Bus

Signal Error Event. The options are Enabled and Disabled.

SERR# Generation

Select Enabled to allow a PCI device to generate an SERR number for a PCI Bus

Signal Error Event. The options are Enabled and Disabled.

Maximum Payload

Select Auto to allow the system BIOS to automatically set the maximum payload

value for a PCI-E device to enhance system performance. The options are Auto,

128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes,.and 4096 Bytes.

Maximum Read Request

Select Auto to allow the system BIOS to automatically set the maximum Read

Request size for a PCI-E device to enhance system performance. The options are

Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.

ASPM Support

This feature allows the user to set the Active State Power Management (ASPM)

level for a PCI-E device. Select Auto to allow the system BIOS to automatically

set the ASPM level for the system. Select Disabled to disable ASPM support. The

options are Disabled and Auto.

Warning: Enabling ASPM support may cause some PCI-E devices to fail!

Above 4G Decoding (Available if the system supports 64-bit PCI decoding)

Select Enabled to decode a PCI device that supports 64-bit in the space above 4G

Address. The options are Enabled and Disabled.

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

CPU2 Slot1 PCI-E 3.0 x16 OPROM, CPU2 Slot2 PCI-E 3.0 x16 OPROM, CPU2
Slot3 PCI-E 3.0 x16 OPROM, CPU2 Slot4 PCI-E 3.0 x16 OPROM, CPU2 Slot5
PCI-E 3.0 x8 OPROM, CPU1 Slot6 PCI-E 3.0 x8 OPROM, PCI/PCIX/PCIe
Slot7 OPROM, CPU1 Slot8 PCI-E 3.0 x16 OPROM, CPU1 Slot9 PCI-E 3.0
x16 OPROM, CPU1 Slot9 PCI-E 3.0 x16 OPROM, CPU1 Slot10 PCI-E 3.0 x16
OPROM, CPU1 Slot11 PCI-E 3.0 x16 OPROM,

Select Enabled to enable Option ROM support to boot the computer using a de-

vice installed on the slot specied above. The options are Enabled and Disabled.

Onboard LAN Option ROM Select

Select iSCSI to use the iSCSI Option ROM to boot the computer from a SCSI

drive. Select PXE (Preboot Execution Environment) to use an PXE Option ROM to

boot the computer from a SCSI PXE drive. The options are iSCSI, FCoE, and PXE.

Load Onboard LAN1 Option ROM, Load Onboard LAN2 Option ROM

Select Enabled to enable the onboard LAN1/LAN2 Option ROM. This is to boot

the computer using a network device installed in a LAN port specied. The default

setting for LAN1 Option ROM is Enabled, and the default setting for LAN2 Option

ROM is Disabled.

VGA Priority

This feature allows the user to select the graphics adapter to be used as the primary

boot device. The options are Onboard and Offboard.

Network Stack

Select Enabled enable PXE (Preboot Execution Environment) or UEFI (Unied

Extensible Firmware Interface) for network stack support. The options are Enabled

and Disabled.

IPv4 PXE Support (Available when the item abobe-Network Stack is set to
Enabled)

Set this item to Enabled to activate IPv4 PXE Support. The options are Enabled

and Disabled.

Super IO Conguration

Super IO Chip: This item displays the Super IO chip used in the motherboard.

WPCM450 Serial Port Attribute

If this item is set to COM/SOL, the port specied above will be used for normal

operation. Select BMC for the port specied above to be used for system debugging

only. The options are COM/SOL and BMC.

Chapter 4: AMI BIOS

4-19

Serial Port 1 Conguration

Serial Port

Select Enabled to enable a serial port specied by the user. The options are En-

abled and Disabled.

Device Settings

This item displays the settings of Serial Port 1.

Change Settings

This option species the base I/O port address and the Interrupt Request address

of Serial Port 1. Select Disabled to prevent the serial port from accessing any

system resources. When this option is set to Disabled, the serial port becomes

unavailable. The options are Auto, IO=3F8h; IRQ=4, IO=3F8h, IRQ=3; IO=2F8h,

IRQ=3; IO=3E8h, IRQ=5; IO=2E8h, IRQ=7; IO=3F8h, IRQ=3, 4, 5, 6, 7, 10, 11,

12; IO=2F8h, IRQ=3, 4, 5, 6, 7, 10, 11, 12; IO=3E8h, IRQ=3, 4, 5, 6, 7, 10, 11, 12;

IO=2E8h, IRQ=3, 4, 5, 6, 7, 10, 11, 12.

Device Mode

Use this feature to select the desired mode for a serial port specied. The options

are Normal and High Speed.

Serial Port 2 Conguration

SOL (Serial-Over-LAN) Serial Port

Select Enabled to enable a serial port specied by the user. The options are En-

abled and Disabled.

Device Settings

This item displays the settings of Serial Port 2.

SOL Change Settings

This option species the base I/O port address and the Interrupt Request address

of Serial Port 2. Select Disabled to prevent the serial port from accessing any

system resources. When this option is set to Disabled, the serial port becomes

unavailable. The options are Auto, IO=3F8h, IRQ=4; IO=3F8h, IRQ=3; IO=2F8h,

IRQ=3; IO=3E8h, IRQ=5; IO=2E8h, IRQ=7; IO=3F8h, IRQ=3, 4, 5, 6, 7, 10, 11,

12; IO=2F8h, IRQ=3, 4, 5, 6, 7, 10, 11, 12; IO=3E8h, IRQ=3, 4, 5, 6, 7, 10, 11, 12;

IO=2E8h, IRQ=3, 4, 5, 6, 7, 10, 11, 12.

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X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

SOL Device Mode

Use this feature to select the desired mode for a serial port specied. The options

are Normal and High Speed.

Serial Port Console Redirection

COM1/SOL

These two submenus allow the user to congure the following console redirection

settings for a COM Port specied by the user.

COM1/SOL Console Redirection

Select Enabled to use a COM Port selected by the user for console redirection.

The options are Enabled and Disabled. The default setting for COM1 is Disabled,

and for COM2 is Enabled.

Console Redirection Settings

This feature allows the user to specify how the host computer will exchange data

with the client computer, which is the remote computer used by the user.

Terminal Type

This feature allows the user to select the target terminal emulation type for con-

sole redirection. Select VT100 to use the ASCII Character set. Select VT100+ to

add color and function key support. Select ANSI to use the Extended ASCII Char-

acter Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters

into one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8.

Bits Per second

Use this feature to set the transmission speed for a serial port used in console

redirection. Make sure that the same speed is used in the host computer and the

client computer. A lower transmission speed may be required for long and busy

lines. The options are 9600, 19200, 38400, 57600 and 115200 (bits per second).

Data Bits

Use this feature to set the data transmission size for Console redirection. The

options are 7 Bits and 8 Bits.

Parity

A parity bit can be sent along with regular data bits to detect data transmission

errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits

is even. Select Odd if the parity bit is set to 0, and the number of 1's in data bits

is odd. Select None if you do not want to send a parity bit with your data bits

Chapter 4: AMI BIOS

4-21

in transmission. Select Mark to add a mark as a parity bit to be sent along with

the data bits. Select Space to add a Space as a parity bit to be sent with your

data bits. The options are None, Even, Odd, Mark and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard

serial data communication. Select 2 Stop Bits if slower devices are used. The

options are 1 and 2.

Flow Control

This feature allows the user to set the ow control for Console redirection to

prevent data loss caused by buffer overow. Send a "Stop" signal to stop send-

ing data when the receiving buffer is full. Send a "Start" signal to start sending

data when the receiving buffer is empty. The options are None and Hardware

RTS/CTS.

VT-UTF8 Combo Key Support

Select Enabled to enable VT-UTF8 Combination Key support for ANSI/VT100

terminals. The options are Enabled and Disabled.

Recorder Mode

Select Enabled to capture the data displayed on a terminal and send it as text

messages to a remote server. The options are Disabled and Enabled.

Resolution 100x31

Select Enabled for extended-terminal resolution support. The options are Dis-

abled and Enabled.

Legacy OS Redirection Resolution

Use this feature to select the number of rows and columns used in Console

redirection for legacy OS support. The options are 80x24 and 80x25.

Putty KeyPad

This feature selects Function Keys and KeyPad settings for Putty, which is a

terminal emulator designed for the Windows OS. The options are VT100, LINUX,

XTERMR6, SCO, ESCN, and VT400.

Redirection After BIOS Post

Use this feature to enable or disable legacy console redirection after BIOS POST.

When set to Bootloader, legacy console redirection is disabled before booting

the OS. When set to Always Enable, legacy console redirection remains enabled

when booting the OS. The options are Always Enable and Bootloader.

4-22

X9DRG-O(T)F-CPU/X9DRG-O-PCIE Platform User’s Manual

Serial Port for Out-of-Band Management/Windows Emergency Management
Services (EMS)

The submenu allows the user to congure console redirection settings to support

Out-of-Band Serial Port management.

Console Redirection

Select Enabled to use a COM Port selected by the user for console redirection. The

options are Enabled and Disabled.



Console Redirection Settings (for EMS)

This feature allows the user to specify how the host computer will exchange

data with the client computer, which is the remote computer used by the user.

Out-of-Band Management Port

The feature selects a serial port used by the Microsoft Windows Emergency

Management Services (EMS) to communicate with a remote server. The options

are COM1 and SOL.

Terminal Type

This feature allows the user to select the target terminal emulation type for con-

sole redirection. Select VT100 to use the ASCII character set. Select VT100+

to add color and function key support. Select ANSI to use the extended ASCII

character set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters

into one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8.

Bits Per Second

This item sets the transmission speed for a serial port used in console redirec-

tion. Make sure that the same speed is used in the host computer and the client

computer. A lower transmission speed may be required for long and busy lines.

The options are 9600, 19200, 57600, and 115200 (bits per second).

Flow Control

This feature allows the user to set the ow control for console redirection to

prevent data loss caused by buffer overow. Send a "Stop" signal to stop send-

ing data when the receiving buffer is full. Send a "Start" signal to start sending

data when the receiving buffer is empty. The options are None, Hardware RTS/

CTS, and Software Xon/Xoff.

Data Bits, Parity, Stop Bits

The setting for each of these items is displayed.