M93C86-x M93C76-x M93C66-x
PDIP8 (BN)
SO8 (MN)
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm
M93C56-x M93C46-x
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE™ serial access EEPROM
Datasheet - production data
Features
• Industry standard MICROWIRE™ bus
• Single supply voltage:
–2.5 V to 5.5 V for M93Cx6-W
–1.8 V to 5.5 V for M93Cx6-R
• Dual organization: by word (x16) or byte (x8)
• Programming instructions that work on: byte,
d or entire memory
wor
• Self-timed programming cycle with auto-erase:
5 ms
• READY/
• 2 MHz clock rate
• Sequential read operation
• Enhanced ESD/latch-up behavior
• More than 4 million write cycles
• More than 200-year data retention
• Packages
– SO8, TSSOP8, UFDFPN8 packages:
– PDIP8 package:
BUSY signal during programming
OPACK2®)
EC
ECOPACK1®
Table 1. Device summary
Reference
December 2015 DocID4997 Rev 17 1/35
This is information on a product in full production.
M93C46-x
M93C56-x
M93C66-x
M93C76-x
M93C86-x
Part
nu
mber
M93C46-W
M93C46-R 1.8 V to 5.5 V
M93C56-W
M93C56-R 1.8 V to 5.5 V
M93C66-W
M93C66-R 1.8 V to 5.5 V
M93C76-W
M93C76-R 1.8 V to 5.5 V
M93C86-W
M93C86-R 1.8 V to 5.5 V
Memory
size
1 Kbit
2 Kbit
4 Kbit
8 Kbit
16 Kbit
Supply
voltage
2.5 V to 5.5 V
2.5 V to 5.5 V
2.5 V to 5.5 V
2.5 V to 5.5 V
2.5 V to 5.5 V
www.st.com
Contents M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.3 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.4 Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.5 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.1 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Contents
11.3 UFDFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.4 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID4997 Rev 17 3/35
3
List of tables M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Memory size versus organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Operating conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Operating conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Memory cell da ta ret en tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. DC characteristics (M93Cx6-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. AC characteristics (M93Cx6-W, M93Cx6-R, device grade 6). . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. DC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. AC characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 18. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. M93Cx6 ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. READ, WRITE, WEN, WDS sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. WRAL sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. PDIP8 – 8 lead plastic dual in-line package, 300 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . 26
Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID4997 Rev 17 5/35
5
Description M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
!)
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6
##
-#X
6
33
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1
3
/2'
1 Description
The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable P
through the MICROWIRE™ bus protocol. The memory array can be configured either in
bytes (x8b) or in words (x16b).
ROgrammable Memory (EEPROM) devices accessed
The M93Cx6-W devices operate within a voltage
supply range from 2.5 V to 5.5 V and the
M93Cx6-R devices operate within a voltage supply range from 1.8 V to 5.5 V. All these
devices operate with a clock frequency of 2 MHz (or less), over an ambient temperature
ange of - 40 °C / + 85 °C.
r
Table 2. Memory size versus organization
Device Number of bits Number of 8-bit bytes Number of 16-bit words
M93C86 16384 2048 1024
M93C76 8192 1024 512
M93C66 4096 512 256
M93C56 2048 256 128
M93C46 1024 128 64
Figure 1. Logic diagram
Table 3. Signal names
Signal name Function Direction
S Chip Select Input
D Serial Data input Input
Q Serial Data output Output
C Serial Clock Input
ORG Organization Select Input
V
CC
V
6/35 DocID4997 Rev 17
SS
Supply voltage Ground -
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Description
6
33
1
/2'
$5#
36
##
$
!)"
-#X
Figure 2. 8-pin package connections (top view)
1. See Section 11: Package information for package dimensions, and how to identify pin-1.
2. DU = Don't Use. The DU (do not use) pin does not con
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to V
or VSS.
CC
tribute to the normal operation of the device. It is
DocID4997 Rev 17 7/35
34
Connecting to the serial bus M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
!)B
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-XXX
MEMORYDEVICE
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3
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#1$
3
-XXX
MEMORYDEVICE
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3
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/2'
/2'
/2'
22 2
6
##
6
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6
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6
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6
33
6
33
6
33
6
33
2
2 Connecting to the serial bus
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only on
line at a time, the other devices are high impedan ce.
e device drives the Serial Data output (Q)
The pull-down resistor R (represented in Figure 3) ensures that no device is s
elected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
imp
edance at the same time (for example, if the bus master is reset du ring the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the t
requirement is met. The typical value of R is 100 kΩ.
SLCH
Figure 3. Bus master and memory devices on the serial bus
8/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Operating features
3 Operating features
3.1 Supply voltage (VCC)
3.1.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [V
DC supply voltage, it is recommended to decouple the V
(usually of the order of 10 nF to 100 nF) close to the V
This voltage must remain stable and valid until the end of the transmission of the instr uction
and, for a Write instruction, until the completion of the internal write cycle (t
3.1.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float and should be driven to V
recommended to connect the S line to V
3.1.3 Power-up and device reset
(min), VCC(max)] range must be applied. In order to secure a sta ble
CC
via a suitable pull-down resistor.
SS
line with a suitable capacitor
CC
CC/VSS
package pins.
, it is therefore
SS
).
W
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V
instruction until V
lower than the minimum V
Section 10: DC and AC parameters).
When VCC passes the POR threshold, the device is reset and is in the following state:
• Standby Power mode
• deselected (assuming that there is a pull-down resistor on the S line)
3.1.4 Power-down
At power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in th e S ta ndby Power mode (that is,
there should be no internal Write cycle in progress).
), the device does not respond to any
has reached the power on reset threshold voltage (this threshold is
CC
operating voltage defined in Operating conditions, in
CC
CC
DocID4997 Rev 17 9/35
34
Memory organization M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x
06Y9
9FF
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4 Memory organization
The M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization
Select (ORG) is left unconnected (or connected to V
when Organization Select (ORG) is connected to Ground (V
selected. When the M93Cx6 is in Standby mode, Organization Select (ORG) should be set
either to V
between V
or VCC to reach the device minimum power consumption (as any voltage
SS
and VCC applied to ORG input may increase the device Standby current).
SS
Figure 4. M93Cx6 ORG input connection
) the x16 organization is selected;
CC
) the x8 organization is
SS
10/35 DocID4997 Rev 17
M93C86-x M93C76-x M93C66-x M93C56-x M93C46-x Instructions
5 Instructions
The instruction set of the M93Cx6 devices contains seven instructions, as summarized in
Table 4 to Table 6. Each instruction
READ, WRITE, WEN, WDS sequences:
• Each instruction is preceded by a ri sing edge on Chip Select
(C) being held low.
• A start bit, which is the first ‘1’ read on Seria
Serial Clock (C).
• Two op-code bits, read on Serial Data Input (D) du
(C). (Some instructions also use the first two bits of the address to define the op-code).
• The address bits of the byte or word that
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 4). For the M93C56 and M93C6 6, the ad d re ss is ma de up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 5). For the M93C76 and
M93C86, the address is made up of 10 bit s for the x16 o rganization or 11 bits for the x8
ganization (see Table 6).
or
consists of the following parts, as shown in Figure 5:
Input (S) with Serial Clock
l Data Input (D) during the rising edge of
ring the rising edge of Serial Clock
is to be accessed. For the M93C46, the
The M93Cx6 devices are fabricated in CMOS te
slow as 0 Hz (static input signals) or as fast as
chnology and are therefore able to run as
the maximum ratings specified in “AC
characteristics” tables, in Section 10: DC and AC parameters.
Instruction Description
READ
WRITE
WEN Write Enable 1 00 11X XXXX - 10 11 XXXX - 9
WDS Write Disable 1 00
ERASE
ERAL Erase All Memory 1 00
WRAL
1. X = Don't Care bit.
Read Data from
Memory
Write Data to
Memory
Erase Byte or
rd
Wo
Write All Memory
with same Data
T a ble 4. Instruction set for the M93C46
x8 origination (ORG = 0) x16 origination (ORG = 1)
Start
Op-
t
code
bi
1 10 A6-A0 Q7-Q0 - A5-A0 Q15-Q0 -
1 01 A6-A0 D7-D0 18 A5-A0 D15-D0 25
1 11 A6-A0 - 10 A5-A0 - 9
1 00
Address
(1)
00X
XXX
X
10X
XXX
X
01X
X
XXX
Data
D7-D0 18 01 XXXX D15-D0 25
Required
clock
cycles
- 10 00 XXXX - 9
- 10 10 XXXX - 9
Address
(1)
Data
Required
cycles
clock
DocID4997 Rev 17 1 1/35
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