Features
3
Type R
DS(on)
VNN7NV04
VNS7NV04
VND7NV04
60 mΩ 6A 40V
VND7NV04-1
■ Linear current limitation
■ Thermal shutdown
■ Short circuit protection
■ Integrated clamp
■ Low current drawn from input pin
■ Diagnostic feedback through input pin
■ ESD protection
■ Direct access to the gate of the Power
MOSFET (analog driving)
■ Compatible with standard Power MOSFET in
compliance with the 2002/95/EC European
Directive
I
lim
V
clamp
VNN7NV04, VNS7NV04
VND7NV04, VND7NV04-1
OMNIFET II
fully autoprotected Power MOSFET
2
3
2
1
SOT-223
3
1
TO252 (DPAK)
Description
The VNN7NV04, VNS7NV04, VND7NV04
VND7NV04-1, are monolithic devices designed in
STMicroelectronics VIPower M0-3 Technology,
intended for replacement of standard Power
MOSFETs from DC up to 50 kHz applications.
Built in thermal shutdown, linear current limitation
and overvoltage clamp protect the chip in harsh
environments.
SO-8
TO251 (IPAK)
2
1
Fault feedback can be detected by monitoring the
voltage at the input pin.
Table 1. Device summary
Package
Tube Tube (lead-free) Tape and reel Tape and reel (lead-free)
SOT-223 VNN7NV04 - VNN7NV0413TR -
SO-8 VNS7NV04 - VNS7NV0413TR -
TO-252 VND7NV04 VND7NV04-E VND7NV0413TR VND7NV04TR-E
TO-251 VND7NV04-1 VND7NV04-1-E - -
September 2010 Doc ID 7383 Rev 3 1/37
Order codes
www.st.com
1
Contents VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 SO-8 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 DPAK maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 SOT-223 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . 19
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 DPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5 SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.7 DPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.8 IPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. SOT-223 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. DPAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 7383 Rev 3 3/37
List of figures VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Static drain source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Static drain-source on resistance vs Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20. Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 21. Turn-off drain source voltage slope (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 27. Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 28. Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 29. Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 30. SO-8 maximum turn-off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 31. SO-8 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 32. DPAK maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 33. DPAK demagnetization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 34. SOT-223 maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 35. SOT-223 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 36. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 37. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 38. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 39. Thermal fitting model of an OMNIFET II in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 40. SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 41. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 42. SOT-223 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 43. Thermal fitting model of an OMNIFET II in SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 44. DPAK PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 45. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 46. DPAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 47. Thermal fitting model of an OMNIFET II in DPAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 48. TO-251 (IPAK) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 List of figures
Figure 49. TO-252 (DPAK) package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 50. SOT-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 51. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 52. SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 53. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 54. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 55. DPAK footprint and tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 56. DPAK tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 57. IPAK tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 7383 Rev 3 5/37
Block diagram and pin description VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
1 Block diagram and pin description
Figure 1. Block diagram
DRAIN
2
Overvoltage
Clamp
INPUT
1
Gate
Control
Over
Temperature
Linear
Current
Limiter
Figure 2. Configuration diagram (top view)
SO-8 Package
SOURCE
SOURCE
SOURCE
INPUT
1
4
1. For the pins configuration related to SOT-223, DPAK, IPAK see outlines at page 1.
(1)
DRAIN
8
DRAIN
DRAIN
5
DRAIN
3
SOURCE
FC01000
6/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Electrical specifications
2 Electrical specifications
Figure 3. Current and voltage conventions
I
D
V
DS
R
I
IN
IN
INPUT
V
IN
2.1 Absolute maximum ratings
DRAIN
SOURCE
Table 2. Absolute maximum ratings
Val ue
Symbol Parameter
Unit
SOT-223 SO-8 DPAK/IPAK
V
R
IN MIN
V
V
V
I
ESD1
ESD2
P
Drain-source voltage (VIN=0 V) Internally clamped V
DS
Input voltage Internally clamped V
IN
Input current +/-20 mA
IN
Minimum input series impedance 150 Ω
Drain current Internally limited A
I
D
Reverse DC output current -10.5 A
I
R
Electrostatic discharge (R=1.5 KΩ,
C=100 pF)
Electrostatic discharge on output pin
only (R=330 Ω, C=150 pF)
Total dissipation at Tc=25 °C 7 4.6 60 W
tot
4000 V
16500 V
Maximum switching energy
E
MAX
(L=0.7 mH; R
T
=150 ºC; IL=9 A)
jstart
=0 Ω; V
L
=13.5 V;
bat
40 40 mJ
Maximum switching energy
E
MAX
T
T
(L=0.6 mH; R
T
=150 ºC; IL=9 A)
jstart
Operating junction temperature Internally limited °C
T
j
Case operating temperature Internally limited °C
c
Storage temperature -55 to 150 °C
stg
=0 Ω; V
L
=13.5 V;
bat
37 mJ
Doc ID 7383 Rev 3 7/37
Electrical specifications VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
2.2 Thermal data
Table 3. Thermal data
Value
Symbol Parameter
SOT-223 SO-8 DPAK IPAK
R
thj-case
R
thj-lead
R
thj-amb
1. When mounted on a standard single-sided FR4 board with 0.5 mm2 of Cu (at least 35 µm thick) connected to all DRAIN
pins.
Thermal resistance junction-case max 18 2.1 2.1 °C/W
Thermal resistance junction-lead max 27 °C/W
Thermal resistance junction-ambient max 96
(1)
90
(1)
65
(1)
102 °C/W
2.3 Electrical characteristics
-40 °C < Tj < 150 °C, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test conditions Min Typ Max Unit
Off
V
CLAMP
V
CLTH
V
INTH
I
ISS
V
INCL
I
DSS
On
Drain-source clamp
voltage
Drain-source clamp
threshold voltage
V
=0 V; ID=3.5 A 40 45 55 V
IN
=0 V; ID=2 mA 36 V
V
IN
Input threshold voltage VDS=VIN; ID=1 mA 0.5 2.5 V
Supply current from input
pin
Input-source clamp
voltage
Zero input voltage drain
current (VIN=0 V)
=0 V; VIN=5 V 100 150 µA
V
DS
=1 mA
I
IN
=-1 mA
I
IN
=13 V; VIN=0 V; Tj=25 °C
V
DS
=25 V; VIN=0 V
V
DS
6
-1.0
6.8 8
-0.3
30
75
Unit
V
µA
=5 V; ID=3.5 A; Tj=25 °C
V
IN
=5 V; ID=3.5 A
V
IN
=13 V; ID=3.5 A 9 S
V
DD
R
DS(on)
Dynamic (T
(1)
g
fs
C
OSS
Static drain-source on
resistance
=25 °C, unless otherwise specified)
j
Forward
transconductance
Output capacitance VDS=13V; f=1MHz; VIN=0 V 220 pF
8/37 Doc ID 7383 Rev 3
60
120
mΩ
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Electrical specifications
Table 4. Electrical characteristics (continued)
Symbol Parameter Test conditions Min Typ Max Unit
Switching (Tj=25 °C, unless otherwise specified)
t
d(on)
t
t
d(off)
t
t
d(on)
t
t
d(off)
t
(dI/dt)
Q
Source drain diode (T
V
SD
t
Q
I
RRM
Protections (-40 °C < T
I
lim
t
dlim
Turn-on delay time
V
=15 V; ID=3.5 A
Rise time 470 1500 ns
r
Turn-off delay time 500 1500 ns
Fall time 350 1000 ns
f
DD
V
=5 V; R
gen
gen=RIN MIN
(see figure Figure 4.)
=150 Ω
Turn-on delay time
=15 V; ID=3.5 A
V
Rise time 4.6 14.0 µs
r
Turn-off delay time 5.4 16.0 µs
Fall time 3.6 11.0 µs
f
Turn-on current slope
on
Total input charge
i
=25 °C, unless otherwise specified)
j
(1)
Forward on voltage ISD=3.5 A; VIN=0 V 0.8 V
Reverse recovery time
rr
Reverse recovery charge 0.28 µC
rr
Reverse recovery current 2.5 A
< 150 °C, unless otherwise specified)
j
DD
V
gen
=5 V; R
=2.2 KΩ
gen
(see figure Figure 4.)
VDD=15 V; ID=3.5 A
=5 V; R
V
gen
V
=12 V; ID=3.5 A; VIN=5 V
DD
=2.13 mA (see figure Figure 7.)
I
gen
gen=RIN MIN
=150 Ω
ISD=3.5 A; dI/dt=20 A/µs
=30 V; L=200 µH
V
DD
(see test circuit, figure Figure 5.)
100 300 ns
0.75 2.3 µs
6.5 A/µs
18 nC
220 ns
Drain current limit VIN=5 V; VDS=13 V 6 9 12 A
Step response current
limit
VIN=5 V; VDS=13 V 4.0 µs
jsh
T
I
E
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
shutdown
Over temperature reset 135 °C
jrs
Fault sink current VIN=5 V; VDS=13 V; Tj=T
gf
Single pulse avalanche
as
energy
Over temperature
T
jsh
starting T
V
IN
=25 °C; VDD=24 V
j
=5 V R
gen=RIN MIN
=150 Ω; L=24 mH
(see figures Figure 6. & Figure 8.)
Doc ID 7383 Rev 3 9/37
150 175 200 °C
15 mA
200 mJ
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
3 Protection features
During normal operation, the input pin is electrically connected to the gate of the internal
Power MOSFET through a low impedance path.
The device then behaves like a standard Power MOSFET and can be used as a switch from
DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current
I
(typ. 100µA) flows into the input pin in order to supply the internal circuitry.
ISS
The device integrates:
● Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche
characteristics of the Power MOSFET stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly important when driving inductive
loads.
● Linear current limiter circuit: limits the drain current I
voltages. When the current limiter is active, the device operates in the linear region, so
power dissipation may exceed the capability of the heatsink. Both case and junction
temperatures increase, and if this phase lasts long enough, junction temperature may
reach the over temperature threshold T
● Over temperature and short circuit protection: these are based on sensing the chip
jsh
.
temperature and are not dependent on the input voltage. The location of the sensing
element on the chip in the power stage area ensures fast, accurate detection of the
junction temperature. Over temperature cutout occurs in the range 150 to 190 °C, a
typical value being 170 °C. The device is automatically restarted when the chip
temperature falls of about 15 °C below shutdown temperature.
● Status feedback: in the case of an over temperature fault condition (T
device tries to sink a diagnostic current I
through the input pin in order to indicate fault
gf
condition. If driven from a low impedance source, this current may be used in order to
warn the control circuit of a device shutdown. If the drive impedance is high enough so
that the input pin driver is not able to supply the current I
This will not however affect the device operation: no requirement is put on the current
capability of the input pin driver except to be able to supply the normal operation drive
current I
ISS
.
Additional features of this device are ESD protection according to the Human Body model
and the ability to be driven from a TTL logic circuit.
to I
D
whatever the input pin
lim
> T
j
, the input pin will fall to 0 V.
gf
jsh
), the
10/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features
Figure 4. Switching time test circuit for resistive load
I
D
90%
t
r
t
V
gen
d(on)
10%
Figure 5. Test circuit for diode recovery times
A
FAST
DIODE
B
R
gen
I
V
gen
150
I
OMNIFET
Ω
D
S
t
d(off)
A
B
OMNIFET
t
f
D
S
L=100uH
t
t
V
DD
8.5
Ω
Doc ID 7383 Rev 3 11/37
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Figure 6. Unclamped inductive load test
Figure 7. Input charge test circuit
circuits
V
IN
R
V
IN
P
GEN
W
Figure 8. Unclamped inductive waveforms
12/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features
3.1 Electrical characteristics curves
Figure 9. Derating curve Figure 10. Transconductance
Gfs (S)
20
18
16
14
12
10
8
6
4
2
0
Vds=13V
Tj=-40ºC
Tj=25ºC
Tj=150ºC
01234567 8
Id(A)
Figure 11. Static drain-source on resistance
vs input voltage (part 1/2)
Rds(on) (mOhm)
120
110
100
90
80
70
60
50
40
30
20
10
0
33.544.555.566.5 7
Id=3.5A
Tj=150ºC
Tj=25ºC
Tj= - 40ºC
Vin(V)
Figure 13. Source-drain diode forward
characteristics
Vsd (mV)
1000
950
900
850
800
750
700
650
600
550
500
Vin=0V
0 2 4 6 8 101214
Id(A)
Figure 12. Static drain-source on resistance
vs input voltage (part 2/2)
Rds(on) (m Ohm)
140
120
Tj=150ºC
100
80
Tj=25ºC
60
Tj=-40ºC
40
20
0
33.544.5 55.5 6 6.5
Id=6A
Id=1A
Id=6A
Id=1A
Id=6A
Id=1A
Vin(V)
Figure 14. Static drain source on resistance
Rds(on) (mohms)
150
125
Vin=5V
100
75
50
25
0
0123456
Id(A)
Tj=150ºC
Tj=25ºC
Tj=-40ºC
Doc ID 7383 Rev 3 13/37
)
dv/dt(V/us)
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Figure 15. Turn-on current slope (part 1/2) Figure 16. Turn-on current slope (part 2/2)
di/dt(A/us)
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
100
200
300
400
500
Rg(ohm)
600
700
Vin=3.5V
Vdd=15V
Id=3.5A
800
900
1000
1100
di/dt(A/us)
8
7
6
5
4
3
2
1
0
100
200
300
400
500
Rg(ohm)
600
Vin=5V
Vdd=15V
Id=3.5A
700
800
900
1000
Figure 17. Transfer characteristics Figure 18. Static drain-source on resistance
vs Id
Idon(A)
10
9
8
7
6
Vds=13.5V
Tj=25ºC
Tj=-40ºC
Tj=150ºC
Rds(on) (mOhm)
140
120
100
80
Vin=3.5V
Tj=150ºC
5
4
3
2
1
0
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vin(V
60
Tj=25ºC
40
Tj=-40ºC
20
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Id(A)
Figure 19. Input voltage vs input charge Figure 20. Turn-off drain source voltage slope
(part 1/2)
Vin(V)
8
7
6
Vds=12V
Id=3.5A
5
4
3
2
1
0
0 5 10 15 20 25
300
250
200
150
100
Vin=5V
Vdd=15V
Id=3.5A
50
0
100
200
300
400
500
600
700
800
900
Rg(ohm)
Vin=5V
Vin=3.5V
Vin=5V
Vin=3.5V
Vin=5V
1000
1100
1100
14/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features
Figure 21. Turn-off drain source voltage slope
Figure 22. Capacitance variations
(part 2/2)
dv/dt(v/us)
300
250
700
Vin=3.5V
Vdd=15V
Id=3.5A
800
900
1000
1100
200
150
100
50
0
200
400
100
300
500
600
Rg(ohm)
C(pF)
600
500
400
300
200
100
0 5 10 15 20 25 30 35
f=1MHz
Vin=0V
Vds(V)
Figure 23. Output characteristics Figure 24. Normalized on resistance vs
temperature
v
ID(A)
12
11
10
9
8
7
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Vin=5V
Vin=4.5V
Vin=4V
Vin=3V
Vin=2.5V
Vin=2V
VDS(V)
Rds(on)
2.25
2
1.75
1.5
1.25
0.75
0.5
Vin=5V
Id=3.5A
1
-50 -25 0 25 50 75 100 125 150 175
T(ºC)
Figure 25. Switching time resistive load (part
1/2)
t(us)
5.5
5
4.5
3.5
2.5
1.5
0.5
Vdd=15V
Id=3.5A
Vin=5V
4
3
2
1
0
250
0
500
750
1000
1250
td(off)
td(on)
1500
1750
Rg(ohm)
2000
tr
tf
2250
Figure 26. Switching time resistive load (part
2/2)
t(ns)
1600
tr
1400
1200
1000
800
2500
600
400
200
0
3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25
td(off)
td(on)
Vin(V)
Doc ID 7383 Rev 3 15/37
Vdd=15V
Id=3.5A
Rg=150ohm
tf
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Figure 27. Normalized input threshold voltage
vs temperature
Vin(th)
1.15
1.1
1.05
Vds=Vin
Id=1mA
1
0.95
0.9
0.85
0.8
0.75
0.7
-50 -25 0 25 50 75 100 125 150 175
T(ºC)
Figure 29. Step response current limit
Tdlim(us)
7
6.5
6
Vin=5V
Rg=150ohm
Figure 28. Normalized current limit vs junction
temperature
Ilim (A)
15
14
13
12
11
10
9
8
7
6
5
Vds=13V
Vin=5V
-50 -25 0 25 50 75 100 125 150 175
Tj (ºC)
5.5
5
4.5
4
3.5
5 101520253035
Vdd(V)
16/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features
3.2 SO-8 maximum demagnetization energy
Figure 30. SO-8 maximum turn-off current versus load inductance
LMAX (A)
I
100
10
A
B
C
1
0.1 1 10 100
L(mH)
Legend
A = Single Pulse at T
B = Repetitive pulse at T
C = Repetitive Pulse at T
Conditions:
V
=13.5 V
CC
Values are generated with R
demagnetization) of every pulse must not exceed the temperature specified above for
curves B and C.
Figure 31. SO-8 demagnetization
VIN, I
L
Jstart
=150 °C
=100 °C
Jstart
=125 °C
Jstart
=0 Ω. In case of repetitive pulses, T
L
Demagnetization
Demagnetization
(at beginning of each
jstart
Demagnetization
t
Doc ID 7383 Rev 3 17/37
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
3.3 DPAK maximum demagnetization energy
Figure 32. DPAK maximum turn-off current versus load inductance
LMAX (A)
I
100
10
1
0.01 0.1 1 10 100
L(mH)
Legend
A = Single Pulse at T
B = Repetitive pulse at T
C = Repetitive Pulse at T
Jstart
=150 °C
=100 °C
Jstart
=125 °C
Jstart
Conditions:
V
=13.5 V
CC
Values are generated with R
=0 Ω. In case of repetitive pulses, T
L
(at beginning of each
jstart
demagnetization) of every pulse must not exceed the temperature specified above for
curves B and C.
Figure 33. DPAK demagnetization
VIN, I
L
Demagnetization
Demagnetization
Demagnetization
t
18/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features
3.4 SOT-223 maximum demagnetization energy
Figure 34. SOT-223 maximum turn-off current versus load inductance
LMAX (A)
I
100
10
1
0.01 0.1 1 10
L(mH)
Legend
A = Single Pulse at T
B = Repetitive pulse at T
C = Repetitive Pulse at T
Conditions:
V
=13.5 V
CC
Values are generated with R
demagnetization) of every pulse must not exceed the temperature specified above for
curves B and C.
Figure 35. SOT-223 demagnetization
VIN, I
L
Jstart
=150 °C
=100 °C
Jstart
=125 °C
Jstart
=0 Ω. In case of repetitive pulses, T
L
Demagnetization
Demagnetization
(at beginning of each
jstart
Demagnetization
t
Doc ID 7383 Rev 3 19/37
Package and PCB thermal data VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
4 Package and PCB thermal data
4.1 SO-8 thermal data
Figure 36. SO-8 PC board
Note: Layout condition of R
thickness=2 mm, Cu thickness=35 µm, Copper areas: 0.14 cm
Figure 37. R
thj-amb
RT Hj _am b ( º C / W)
and Zth measurements (PCB FR4 area=58 mm x 58 mm, PCB
th
2
, 0.8 cm2, 2 cm2).
vs PCB copper area in open box free air condition
SO-8 at 2 pins connecte d to TAB
110
105
100
95
90
85
80
75
70
00.511.522.5
20/37 Doc ID 7383 Rev 3
PCB Cu heatsink area (cm^2)
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and PCB thermal data
Figure 38. SO-8 thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
100
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 39. Thermal fitting model of an OMNIFET II in SO-8
Tj
C1
R1 R2
Pd
C2
C3
R3
T_amb
C4
R4
C5
R5
C6
R6
Equation 1 Pulse calculation formula
Z
THδ
where
Table 5. SO-8 thermal parameter
R
δ t
TH
p
δ Z
T⁄=
THtp
1 δ–()+⋅=
Area/island (cm2) Footprint 2
R1 (°C/W) 0.2
R2 (°C/W) 0.9
R3 (°C/W) 3.5
R4 (°C/W) 21
R5 (°C/W) 16
R6 (°C/W) 58 28
C1 (W.s/°C) 3.00E-04
Doc ID 7383 Rev 3 21/37
Package and PCB thermal data VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Table 5. SO-8 thermal parameter (continued)
Area/island (cm2) Footprint 2
C2 (W.s/°C) 9.00E-04
C3 (W.s/°C) 7.50E-03
C4 (W.s/°C) 0.045
C5 (W.s/°C) 0.35
C6 (W.s/°C) 1.05 2
4.2 SOT-223 thermal data
Figure 40. SOT-223 PC board
Note: Layout condition of R
thickness=2 mm, Cu thickness=35 µm, Copper areas: 0.11 cm
Figure 41. R
th
vs PCB copper area in open box free air condition
thj-amb
RTH j-am b (°C/ W )
140
130
120
110
100
90
80
70
60
0 0.5 1 1.5 2 2.5
and Z
measurements (PCB FR4 area=58 mm x 58 mm, PCB
th
Cu area (cm^2)
2
, 1 cm2, 2 cm2).
22/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and PCB thermal data
Figure 42. SOT-223 thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
100
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 43. Thermal fitting model of an OMNIFET II in SOT-223
Tj
C1
R1 R2
Pd
C2
C3
R3
T_amb
C4
R4
C5
R5
C6
R6
Equation 2 Pulse calculation formula
Z
THδ
where
Table 6. SOT-223 thermal parameter
R
δ t
TH
p
δ Z
T⁄=
THtp
1 δ–()+⋅=
Area/island (cm2) Footprint 2
R1 (°C/W) 0.2
R2 (°C/W) 1.1
R3 (°C/W) 4.5
R4 (°C/W) 24
R5 (°C/W) 0.1
R6 (°C/W) 100 45
C1 (W.s/°C) 3.00E-04
Doc ID 7383 Rev 3 23/37
Package and PCB thermal data VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Table 6. SOT-223 thermal parameter (continued)
Area/island (cm2) Footprint 2
C2 (W.s/°C) 9.00E-04
C3 (W.s/°C) 3.00E-02
C4 (W.s/°C) 0.16
C5 (W.s/°C) 1000
C6 (W.s/°C) 0.5 2
4.3 DPAK thermal data
Figure 44. DPAK PC board
Note: Layout condition of R
thickness=2 mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8 cm2).
Figure 45. R
vs PCB copper area in open box free air condition
thj-amb
RTH j_amb (ºC/W)
90
80
70
60
50
40
30
0246810
and Zth measurements (PCB FR4 area=60 mm x 60 mm, PCB
th
PCB CU he atsink area (cm^2)
24/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and PCB thermal data
Figure 46. DPAK thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
100
10
1
0.1
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
Figure 47. Thermal fitting model of an OMNIFET II in DPAK
Tj
C1
R1 R2
Pd
C2
C3
R3
C4
R4
T_amb
C5
R5
C6
R6
Equation 3 Pulse calculation formula
Z
THδ
where
Table 7. DPAK thermal parameter
R
δ t
TH
p
δ Z
T⁄=
THtp
1 δ–()+⋅=
Area/island (cm2) Footprint 6
R1 (°C/W) 0.1
R2 (°C/W) 0.35
R3 (°C/W) 1.20
R4 (°C/W) 2
R5 (°C/W) 15
R6 (°C/W) 61 24
Doc ID 7383 Rev 3 25/37
Package and PCB thermal data VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Table 7. DPAK thermal parameter (continued)
Area/island (cm2) Footprint 6
C1 (W.s/°C) 0.0006
C2 (W.s/°C) 0.0021
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.3
C5 (W.s/°C) 0.45
C6 (W.s/°C) 0.8 5
26/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and packing information
5 Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK® is an ST trademark.
5.1 TO-251 (IPAK) mechanical data
Table 8. TO-251 (IPAK) mechanical data
Symbol
Min. Typ. Max.
A2.2 2.4
A1 0.9 1.1
A3 0.7 1.3
B 0.64 0.9
B2 5.2 5.4
millimeters
.
B3 0.85
B5 0.3
B6 0.95
C 0.45 0.6
C2 0.48 0.6
D6 6.2
E6.4 6.6
G4.4 4.6
H 15.9 16.3
L9 9.4
L1 0.8 1.2
L2 0.8 1
Doc ID 7383 Rev 3 27/37
Package and packing information VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Figure 48. TO-251 (IPAK) package dimensions
5.2 TO-252 (DPAK) mechanical data
Table 9. TO-252 (DPAK) mechanical data
Symbol
Min. Typ. Max.
A 2.20 2.40
A1 0.90 1.10
A2 0.03 0.23
B 0.64 0.90
B2 5.20 5.40
C 0.45 0.60
C2 0.48 0.60
D 6.00 6.20
D1 5.1
E 6.40 6.60
E1 4.7
e2.28
G 4.40 4.60
H 9.35 10.10
millimeters
28/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and packing information
Table 9. TO-252 (DPAK) mechanical data (continued)
millimeters
Symbol
Min. Typ. Max.
L2 0.8
L4 0.60 1.00
R0.2
V2 0° 8°
Package Weight Gr. 0.29
Figure 49. TO-252 (DPAK) package dimensions
5.3 SOT-223 mechanical data
Table 10. SOT-223 mechanical data
Symbol
A 1.8
B0.60.70.85
B1 2.9 3 3.15
c 0.24 0.26 0.35
D6.36.56.7
e2.3
P032P
millimeters
Min. Typ. Max.
Doc ID 7383 Rev 3 29/37
Package and packing information VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Table 10. SOT-223 mechanical data (continued)
millimeters
Symbol
Min. Typ. Max.
e1 4.6
E3.33.53.7
H6.7 7 7.3
V 10 (max)
A1 0.02 0.1
Figure 50. SOT-223 package dimensions
5.4 SO-8 mechanical data
Table 11. SO-8 mechanical data
Symbol
Min Typ Max
A 1.75
a1 0.1 0.25
a2 1.65
30/37 Doc ID 7383 Rev 3
a3 0.65 0.85
b 0.35 0.48
A 1.75
A1 0.10 0.25
0046067
millimeters
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and packing information
Table 11. SO-8 mechanical data (continued)
millimeters
Symbol
Min Typ Max
A2 1.25
b 0.28 0.48
c 0.17 0.23
(1)
4.80 4.90 5.00
D
E 5.80 6.00 6.20
(2)
E1
3.80 3.90 4.00
e 1.27
h 0.25 0.50
L 0.40 1.27
L1 1.04
k 0° 8°
ccc 0.10
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
Figure 51. SO-8 package dimensions
0016023 D
Doc ID 7383 Rev 3 31/37
Package and packing information VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
5.5 SOT-223 packing information
Figure 52. SOT-223 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
32/37 Doc ID 7383 Rev 3
Top
cover
tape
End
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Start
No componentsNo components Components
500mm min
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and packing information
5.6 SO-8 packing information
Figure 53. SO-8 tube shipment (no suffix)
B
C
Base Q.ty 100
Bulk Q.ty 2000
A
Tube length (± 0.5) 532
A 3.2
B 6
C (± 0.1) 0.6
Figure 54. SO-8 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Start
No componentsNo components Components
500mm min
All dimensions are in mm.
Doc ID 7383 Rev 3 33/37
Package and packing information VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
5.7 DPAK packing information
Figure 55. DPAK footprint and tube shipment (no suffix)
A
B
6.7
6.7 3.01.8 1.6
2.3
2.3
Figure 56. DPAK tape and reel shipment (suffix “TR”)
C
Base Q.ty 75
Bulk Q.ty 3000
Tube length (± 0.5) 532
A 6
B 21.3
C (± 0.1) 0.6
REEL DIMENSIONS
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
End
Start
Top
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
No componentsNo components Components
500mm min
34/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and packing information
5.8 IPAK packing information
Figure 57. IPAK tube shipment (no suffix)
A
C
Base Q.ty 75
Bulk Q.ty 3000
Tube length (± 0.5) 532
B
A 6
B 21.3
C (± 0.1) 0.6
All dimensions are in mm.
Doc ID 7383 Rev 3 35/37
Revision history VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
6 Revision history
Table 12. Document revision history
Date Revision Changes
01-Feb-2003 1 Initial Release
Added Table 1: Device summary on page 1 and Section 4:
28-Apr-2009 2
10-Sep-2010 3 Updated Table 4: Electrical characteristics
Package and PCB thermal data on page 20.
Updated Section 5: Package and packing information on
page 27.
36/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
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