ST VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 User Manual
Features
3
Type R
DS(on)
VNN7NV04
VNS7NV04
VND7NV04
60 mΩ 6A 40V
VND7NV04-1
■ Linear current limitation
■ Thermal shutdown
■ Short circuit protection
■ Integrated clamp
■ Low current drawn from input pin
■ Diagnostic feedback through input pin
■ ESD protection
■ Direct access to the gate of the Power
MOSFET (analog driving)
■ Compatible with standard Power MOSFET in
compliance with the 2002/95/EC European
Directive
I
lim
V
clamp
VNN7NV04, VNS7NV04
VND7NV04, VND7NV04-1
OMNIFET II
fully autoprotected Power MOSFET
2
3
2
1
SOT-223
3
1
TO252 (DPAK)
Description
The VNN7NV04, VNS7NV04, VND7NV04
VND7NV04-1, are monolithic devices designed in
STMicroelectronics VIPower M0-3 Technology,
intended for replacement of standard Power
MOSFETs from DC up to 50 kHz applications.
Built in thermal shutdown, linear current limitation
and overvoltage clamp protect the chip in harsh
environments.
SO-8
TO251 (IPAK)
2
1
Fault feedback can be detected by monitoring the
voltage at the input pin.
Table 1. Device summary
Package
Tube Tube (lead-free) Tape and reel Tape and reel (lead-free)
SOT-223 VNN7NV04 - VNN7NV0413TR -
SO-8 VNS7NV04 - VNS7NV0413TR -
TO-252 VND7NV04 VND7NV04-E VND7NV0413TR VND7NV04TR-E
TO-251 VND7NV04-1 VND7NV04-1-E - -
September 2010 Doc ID 7383 Rev 3 1/37
Order codes
www.st.com
1
Contents VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 SO-8 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 DPAK maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 SOT-223 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . 19
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 SOT-223 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 DPAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3 SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5 SOT-223 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.7 DPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.8 IPAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. SOT-223 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. DPAK thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. TO-251 (IPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. TO-252 (DPAK) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. SOT-223 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 7383 Rev 3 3/37
List of figures VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Switching time test circuit for resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Test circuit for diode recovery times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Unclamped inductive load test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Input charge test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Unclamped inductive waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Static drain-source on resistance vs input voltage (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Static drain-source on resistance vs input voltage (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Source-drain diode forward characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Static drain source on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. Turn-on current slope (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Turn-on current slope (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Transfer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Static drain-source on resistance vs Id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Input voltage vs input charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20. Turn-off drain source voltage slope (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 21. Turn-off drain source voltage slope (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Capacitance variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Normalized on resistance vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Switching time resistive load (part 1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Switching time resistive load (part 2/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 27. Normalized input threshold voltage vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 28. Normalized current limit vs junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 29. Step response current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 30. SO-8 maximum turn-off current versus load inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 31. SO-8 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 32. DPAK maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 33. DPAK demagnetization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 34. SOT-223 maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 35. SOT-223 demagnetization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 36. SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 37. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 38. SO-8 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 39. Thermal fitting model of an OMNIFET II in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 40. SOT-223 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 41. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 42. SOT-223 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 43. Thermal fitting model of an OMNIFET II in SOT-223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 44. DPAK PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 45. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 46. DPAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 47. Thermal fitting model of an OMNIFET II in DPAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 48. TO-251 (IPAK) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 List of figures
Figure 49. TO-252 (DPAK) package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 50. SOT-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 51. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 52. SOT-223 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 53. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 54. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 55. DPAK footprint and tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 56. DPAK tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 57. IPAK tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 7383 Rev 3 5/37
Block diagram and pin description VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
1 Block diagram and pin description
Figure 1. Block diagram
DRAIN
2
Overvoltage
Clamp
INPUT
1
Gate
Control
Over
Temperature
Linear
Current
Limiter
Figure 2. Configuration diagram (top view)
SO-8 Package
SOURCE
SOURCE
SOURCE
INPUT
1
4
1. For the pins configuration related to SOT-223, DPAK, IPAK see outlines at page 1.
(1)
DRAIN
8
DRAIN
DRAIN
5
DRAIN
3
SOURCE
FC01000
6/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Electrical specifications
2 Electrical specifications
Figure 3. Current and voltage conventions
I
D
V
DS
R
I
IN
IN
INPUT
V
IN
2.1 Absolute maximum ratings
DRAIN
SOURCE
Table 2. Absolute maximum ratings
Val ue
Symbol Parameter
Unit
SOT-223 SO-8 DPAK/IPAK
V
R
IN MIN
V
V
V
I
ESD1
ESD2
P
Drain-source voltage (VIN=0 V) Internally clamped V
DS
Input voltage Internally clamped V
IN
Input current +/-20 mA
IN
Minimum input series impedance 150 Ω
Drain current Internally limited A
I
D
Reverse DC output current -10.5 A
I
R
Electrostatic discharge (R=1.5 KΩ,
C=100 pF)
Electrostatic discharge on output pin
only (R=330 Ω, C=150 pF)
Total dissipation at Tc=25 °C 7 4.6 60 W
tot
4000 V
16500 V
Maximum switching energy
E
MAX
(L=0.7 mH; R
T
=150 ºC; IL=9 A)
jstart
=0 Ω; V
L
=13.5 V;
bat
40 40 mJ
Maximum switching energy
E
MAX
T
T
(L=0.6 mH; R
T
=150 ºC; IL=9 A)
jstart
Operating junction temperature Internally limited °C
T
j
Case operating temperature Internally limited °C
c
Storage temperature -55 to 150 °C
stg
=0 Ω; V
L
=13.5 V;
bat
37 mJ
Doc ID 7383 Rev 3 7/37
Electrical specifications VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
2.2 Thermal data
Table 3. Thermal data
Value
Symbol Parameter
SOT-223 SO-8 DPAK IPAK
R
thj-case
R
thj-lead
R
thj-amb
1. When mounted on a standard single-sided FR4 board with 0.5 mm2 of Cu (at least 35 µm thick) connected to all DRAIN
pins.
Thermal resistance junction-case max 18 2.1 2.1 °C/W
Thermal resistance junction-lead max 27 °C/W
Thermal resistance junction-ambient max 96
(1)
90
(1)
65
(1)
102 °C/W
2.3 Electrical characteristics
-40 °C < Tj < 150 °C, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test conditions Min Typ Max Unit
Off
V
CLAMP
V
CLTH
V
INTH
I
ISS
V
INCL
I
DSS
On
Drain-source clamp
voltage
Drain-source clamp
threshold voltage
V
=0 V; ID=3.5 A 40 45 55 V
IN
=0 V; ID=2 mA 36 V
V
IN
Input threshold voltage VDS=VIN; ID=1 mA 0.5 2.5 V
Supply current from input
pin
Input-source clamp
voltage
Zero input voltage drain
current (VIN=0 V)
=0 V; VIN=5 V 100 150 µA
V
DS
=1 mA
I
IN
=-1 mA
I
IN
=13 V; VIN=0 V; Tj=25 °C
V
DS
=25 V; VIN=0 V
V
DS
6
-1.0
6.8 8
-0.3
30
75
Unit
V
µA
=5 V; ID=3.5 A; Tj=25 °C
V
IN
=5 V; ID=3.5 A
V
IN
=13 V; ID=3.5 A 9 S
V
DD
R
DS(on)
Dynamic (T
(1)
g
fs
C
OSS
Static drain-source on
resistance
=25 °C, unless otherwise specified)
j
Forward
transconductance
Output capacitance VDS=13V; f=1MHz; VIN=0 V 220 pF
8/37 Doc ID 7383 Rev 3
60
120
mΩ
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Electrical specifications
Table 4. Electrical characteristics (continued)
Symbol Parameter Test conditions Min Typ Max Unit
Switching (Tj=25 °C, unless otherwise specified)
t
d(on)
t
t
d(off)
t
t
d(on)
t
t
d(off)
t
(dI/dt)
Q
Source drain diode (T
V
SD
t
Q
I
RRM
Protections (-40 °C < T
I
lim
t
dlim
Turn-on delay time
V
=15 V; ID=3.5 A
Rise time 470 1500 ns
r
Turn-off delay time 500 1500 ns
Fall time 350 1000 ns
f
DD
V
=5 V; R
gen
gen=RIN MIN
(see figure Figure 4.)
=150 Ω
Turn-on delay time
=15 V; ID=3.5 A
V
Rise time 4.6 14.0 µs
r
Turn-off delay time 5.4 16.0 µs
Fall time 3.6 11.0 µs
f
Turn-on current slope
on
Total input charge
i
=25 °C, unless otherwise specified)
j
(1)
Forward on voltage ISD=3.5 A; VIN=0 V 0.8 V
Reverse recovery time
rr
Reverse recovery charge 0.28 µC
rr
Reverse recovery current 2.5 A
< 150 °C, unless otherwise specified)
j
DD
V
gen
=5 V; R
=2.2 KΩ
gen
(see figure Figure 4.)
VDD=15 V; ID=3.5 A
=5 V; R
V
gen
V
=12 V; ID=3.5 A; VIN=5 V
DD
=2.13 mA (see figure Figure 7.)
I
gen
gen=RIN MIN
=150 Ω
ISD=3.5 A; dI/dt=20 A/µs
=30 V; L=200 µH
V
DD
(see test circuit, figure Figure 5.)
100 300 ns
0.75 2.3 µs
6.5 A/µs
18 nC
220 ns
Drain current limit VIN=5 V; VDS=13 V 6 9 12 A
Step response current
limit
VIN=5 V; VDS=13 V 4.0 µs
jsh
T
I
E
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
shutdown
Over temperature reset 135 °C
jrs
Fault sink current VIN=5 V; VDS=13 V; Tj=T
gf
Single pulse avalanche
as
energy
Over temperature
T
jsh
starting T
V
IN
=25 °C; VDD=24 V
j
=5 V R
gen=RIN MIN
=150 Ω; L=24 mH
(see figures Figure 6. & Figure 8.)
Doc ID 7383 Rev 3 9/37
150 175 200 °C
15 mA
200 mJ
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
3 Protection features
During normal operation, the input pin is electrically connected to the gate of the internal
Power MOSFET through a low impedance path.
The device then behaves like a standard Power MOSFET and can be used as a switch from
DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current
I
(typ. 100µA) flows into the input pin in order to supply the internal circuitry.
ISS
The device integrates:
● Overvoltage clamp protection: internally set at 45 V, along with the rugged avalanche
characteristics of the Power MOSFET stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly important when driving inductive
loads.
● Linear current limiter circuit: limits the drain current I
voltages. When the current limiter is active, the device operates in the linear region, so
power dissipation may exceed the capability of the heatsink. Both case and junction
temperatures increase, and if this phase lasts long enough, junction temperature may
reach the over temperature threshold T
● Over temperature and short circuit protection: these are based on sensing the chip
jsh
.
temperature and are not dependent on the input voltage. The location of the sensing
element on the chip in the power stage area ensures fast, accurate detection of the
junction temperature. Over temperature cutout occurs in the range 150 to 190 °C, a
typical value being 170 °C. The device is automatically restarted when the chip
temperature falls of about 15 °C below shutdown temperature.
● Status feedback: in the case of an over temperature fault condition (T
device tries to sink a diagnostic current I
through the input pin in order to indicate fault
gf
condition. If driven from a low impedance source, this current may be used in order to
warn the control circuit of a device shutdown. If the drive impedance is high enough so
that the input pin driver is not able to supply the current I
This will not however affect the device operation: no requirement is put on the current
capability of the input pin driver except to be able to supply the normal operation drive
current I
ISS
.
Additional features of this device are ESD protection according to the Human Body model
and the ability to be driven from a TTL logic circuit.
to I
D
whatever the input pin
lim
> T
j
, the input pin will fall to 0 V.
gf
jsh
), the
10/37 Doc ID 7383 Rev 3
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features
Figure 4. Switching time test circuit for resistive load
I
D
90%
t
r
t
V
gen
d(on)
10%
Figure 5. Test circuit for diode recovery times
A
FAST
DIODE
B
R
gen
I
V
gen
150
I
OMNIFET
Ω
D
S
t
d(off)
A
B
OMNIFET
t
f
D
S
L=100uH
t
t
V
DD
8.5
Ω
Doc ID 7383 Rev 3 11/37
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1
Figure 6. Unclamped inductive load test
Figure 7. Input charge test circuit
circuits
V
IN
R
V
IN
P
GEN
W
Figure 8. Unclamped inductive waveforms
12/37 Doc ID 7383 Rev 3
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