ST STM32TS60 User Manual

ARM®-based 32-bit MCU with resistive multitouch engine, 32 KB

7 × 7 mm

UFBGA144

FBGA

Unsawn wafer

AIA

Flash, USB, 5 timers, 2 ADCs, and 6 communication interfaces

Features

■ Core: ARM 32-bit Cortex

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

– Single-cycle multiplication and hardware

division

■ Memories

– 32 Kbytes of Flash memory – 10 Kbytes of SRAM

■ Clock, reset and supply management

– 2.4 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage

detector (PVD) – 4 to 16 MHz crystal oscillator – Internal 8-MHz factory-trimmed RC – Internal 40-kHz RC – PLL for CPU clock

■ Low power

– Sleep, Stop and Standby modes

■ 2 x 12-bit, 1 µs A/D converters (with up to 64

channels) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Temperature sensor

■ DMA

– 8-channel DMA controller – Peripherals supported: timers, ADC, SPIs,

Cs, USART, PMSE and PMAD.

■ Up to 138 fast I/O ports

■ PMatrix™ scanning engine (PMSE) and

PMatrix™ area detection (PMAD) – Up to 81 columns and 64 rows

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

-M3 CPU

STM32TS60

■ 5 timers

– 2 x 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

– 2 x watchdog timers (independent and

window)

– SysTick timer: a 24-bit downcounter

■ 6 communication interfaces

– 2 x I – 1 x USART (ISO 7816 interface, LIN, IrDA

– 2 x SPIs (18 Mbit/s and 9 Mbit/s) – USB 2.0 full-speed interface

■ CRC calculation unit, 96-bit unique ID

■ Packages are ECOPACK®

C interfaces (SMBus/PMBus)

capability, modem control)

Data brief

March 2011 Doc ID 16925 Rev 3 1/27

For further information contact your local STMicroelectronics sales office.

www.st.com

Contents STM32TS60

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 ARM Cortex-M3 core with embedded Flash and SRAM . . . . . . . . . . . . . 9

2.2.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 9

2.2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.9 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.10 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.11 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.12 PMatrix scanning engine (PMSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.13 PMatrix area detection (PMAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.14 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . 12

2.2.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.17 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.18 Universal synchronous/asynchronous receiver transmitter (USART) . . 13

2.2.19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.22 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Ballout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/27 Doc ID 16925 Rev 3

STM32TS60 Contents

5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Doc ID 16925 Rev 3 3/27

List of tables STM32TS60

List of tables

Table 1. STM32TS60 device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. STM32TS60 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. UFBGA144 - 7 x 7 mm ultra low profile fine pitch ball grid array package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Ordering information scheme for package devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Ordering information for die devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4/27 Doc ID 16925 Rev 3

STM32TS60 List of figures

List of figures

Figure 1. STM32TS60 device block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. STM32TS60 device UFBGA144 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 3. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 4. UFBGA144 - 7 x 7 mm ultra low profile fine pitch ball grid array package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Doc ID 16925 Rev 3 5/27

Introduction STM32TS60

1 Introduction

This data brief provides the ordering information and mechanical device characteristics of

the STM32TS60 microcontrollers.

The STM32TS60 is specifically designed for multitouch touch screen applications based on

Stantum's patented digital resistive multitouch technology. It features two dedicated touch

sensing peripherals (PMatrix™ scanning engine and PMatrix™ area detection) offering a

highly integrated solution and improved performances compared to existing market

solutions. The STM32TS60 supports a touch panel with a matrix of up to 81 columns and 64

rows.

For further information on any aspect of this device or to get access to the corresponding

datasheet, reference manual, die specification, and programming manual, please contact

your nearest ST Sales Office.

For information on the Cortex-M3 core please refer to the Cortex™-M3 Technical Reference

Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Note: PMatrix™ is a trademark of Stantum SAS.

2 Description

The STM32TS60 device incorporates the high-performance ARM, Cortex-M3, 32-bit RISC

core, operating at a 72-MHz frequency, with high-speed embedded memories (32 Kbytes

Flash memory and 10 Kbytes SRAM), and an extensive range of enhanced I/Os and

peripherals connected to two APB buses. It offers two 12-bit ADCs, two general purpose

16-bit timers, as well as standard and advanced communication interfaces: two I

SPIs, one USART, and a USB.

The device operates from a 2.4 to 3.6 V power supply. It is available in the –40 to +85 °C

temperature range. A comprehensive set of power-saving modes allow the design of

low-power applications.The STM32TS60 device is available in a UFBGA144 7 mm x 7 mm

package and die form (unsawn wafer).

Cs, two

6/27 Doc ID 16925 Rev 3

STM32TS60 Description

2.1 Device overview

Table 1. STM32TS60 device features and peripheral counts

Peripheral

Flash (Kbytes) 32

SRAM (Kbytes) 10

General-purpose timers 2

SPI 2

Communication

USART 1

USB 1

GPIOs 138

12-bit synchronized ADC (number of channels) 2 (64)

CPU frequency 72 MHz

Operating voltage 2.4 to 3.6 V

Operating temperatures

Ambient –40 to 85 °C (see Ta bl e 5 )

Junction –40 to 125 °C (see Ta b le 5 )

Packages

Device

UFBGA144

Unsawn wafer

Doc ID 16925 Rev 3 7/27

Description STM32TS60

SW/JTAG

ARM®

Cortex

-M3 CPU

MAX

= 72 MHz

NVIC

8-channel

DMA

BUS MATRIX

Dbus

System

Ibus

Flash

Interface

OBL

64-bit

Flash memory

32 Kbytes

SRAM

10 Kbytes

AHB f

MAX

=48MHz

SUPPLY

SUPERVISOR

POR/PDR

PVD

JTRST

JTDI JTCK/SWCLK JTMS/SWDAT

JTDO

AHB/APB2

BRIDGE

AHB/APB1

BRIDGE

PMSE

I/O

VDD

COL[1:81] as AF

ANALOG

ROW[1:64] as AF

12bit ADC

(x2)

MUX

SPI1

WAKEUP / IOs

APB2 f

MAX

=48MHz

NRESET

PMAD

SRAM 128x32bit

APB1 f

MAX

=24MHz

TIMER2

TIMER3

USART2

SPI2

I2C1

USB 2.0 FS

SRAM 512bytes

WWD

I2C2

SYSTIC

SRAM 128x32bit

DM,DP as AF

SDA,SCL as AF

RX,TX as AF

SDA,SCL as AF

MISO,MOSI,SCK

STANDBY I/F

IWDG

PLL

RC OSC 40kHz

OSC_IN OSC_OUT

XTAL OSC 8MHz

RC OSC 8MHz

RTC / AWU

POWER

3.3 V to 1.8 V

VOLTAGE RE G.

VDD VSS

NSS, as AF

4 channels as AF

GPIO A to I

MISO,MOSI,SCK NSS, as AF

PA0 as AF

138 GPIO

Figure 1. STM32TS60 device block diagram

8/27 Doc ID 16925 Rev 3

STM32TS60 Description

2.2 Peripheral overview

2.2.1 ARM Cortex-M3 core with embedded Flash and SRAM

The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex-M3 32-bit RISC processor features exceptional code efficiency, delivering the high performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32TS60 device, having an embedded ARM core, is therefore compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.2.2 Embedded Flash memory

32 Kbytes of embedded Flash is available for storing programs and data.

2.2.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

2.2.4 Embedded SRAM

The 10 Kbytes of embedded SRAM can be accessed (read/write) at CPU clock speed with 0 wait states.

2.2.5 Nested vectored interrupt controller (NVIC)

The STM32TS60 embeds a nested vectored interrupt controller which can handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3) and 16 priority levels. Features include:

● Closely coupled NVIC which gives low-latency interrupt processing

● Interrupt entry vector table address which is passed directly to the core

● Closely coupled NVIC core interface

● Early processing of interrupts is allowed

● Processing of “late arriving” higher priority interrupts

● Support for tail-chaining

● Processor state is automatically saved

● Interrupt entry is restored on interrupt exit with no instruction overhead

Doc ID 16925 Rev 3 9/27

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