Table 59.TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 98
Table 60.UFBGA100 - ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package
Figure 1 shows the general block diagram of the device family.
8/109 Doc ID 17659 Rev 6
STM32L151xx, STM32L152xxDescription
2 Description
The ultralow power STM32L15xxx incorporates the connectivity power of the universal
serial bus (USB) with the high-performance ARM Cortex
a 32
MHz frequency, a memory protection unit (MPU), high-speed embedded memories
(Flash memory up to 128
enhanced I/Os and peripherals connected to two APB buses. All devices offer a 12-bit ADC,
2 DACs and 2 ultralow power comparators, six general-purpose 16-bit timers and two basic
timers, which can be used as time bases. Moreover, the STM32L15xxx devices contain
standard and advanced communication interfaces: up to two I
and a USB. They also include a real-time clock and a set of backup registers that remain
powered in Standby mode. Finally, the integrated LCD controller has a built-in LCD voltage
generator that allows you to drive up to 8 multiplexed LCDs with contrast independent of the
supply voltage.
The ultralow power STM32L15xxx operates from a 1.8 to 3.6 V power supply (down to
1.65
V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option.
It is available in the -40 to +85
modes allows the design of low-power applications.
Kbytes and RAM up to 16 Kbytes), and an extensive range of
°C temperature range. A comprehensive set of power-saving
™
-M3 32-bit RISC core operating at
2
Cs and SPIs, three USARTs
Doc ID 17659 Rev 69/109
DescriptionSTM32L151xx, STM32L152xx
2.1 Device overview
Table 2.Ultralow power STM32L15xxx device features and peripheral counts
Ambient temperatures: –40 to +85 °C
Junction temperature: –40 to + 105 °C
4x16
1.8 V to 3.6 V (down to 1.65 V at power-down)
1.65 V to 3.6 V without BOR option
4x32
8x28
with BOR option
4x44
8x40
.
10/109 Doc ID 17659 Rev 6
STM32L151xx, STM32L152xxDescription
2.2 Ultralow power device continuum
The ultralow power STM32L151xx and STM32L152xx are fully pin-to-pin, software and
feature compatible. Besides the full compatibility within the family, the devices are part of
STMicroelectronics microcontrollers ultralow power strategy which also includes
STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a
continuum of performance, peripherals, system architecture and features.
They are all based on STMicroelectronics 0.13 µm ultralow leakage process.
Note:The ultralow power STM32L and general-purpose STM32Fxxxx families are pin-to-pin
compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx
devices. Please refer to the STM32F and STM8L documentation for more information on
these devices.
2.2.1 Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex™-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultralow power performance to range from 5 up to 33.3 DMIPs.
2.2.2 Shared peripherals
STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy
migration from one family to another:
●Analog peripherals: ADC, DAC, and comparators
●Digital peripherals: RTC and some communication interfaces
2.2.3 Common system strategy
To offer flexibility and optimize performance, the STM8L15xx and STM32L15xx families use
a common architecture:
●Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for
STM8L15xx devices)
●Architecture optimized to reach ultralow consumption both in low power modes and
Run mode
●Fast startup strategy from low power modes
●Flexible system clock
●Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector.
2.2.4 Features
ST ultralow power continuum also lies in feature compatibility:
●More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm
●Memory density ranging from 4 to 128 Kbytes
Doc ID 17659 Rev 611/109
Functional overviewSTM32L151xx, STM32L152xx
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3 Functional overview
Figure 1 shows the block diagrams.
Figure 1.Ultralow power STM32L15xxx block diagram
12/109 Doc ID 17659 Rev 6
1. AF = alternate function on I/O port pin.
STM32L151xx, STM32L152xxFunctional overview
3.1 Low power modes
The ultralow power STM32L15xxx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the internal low-drop regulator that supplies the
logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply:
●In range 1 (V
Table 13 for consumption).
●In range 2 (full V
consumption)
●In range 3 (full V
multispeed internal RC oscillator clock source). Refer to Table 13 for consumption.
Seven low power modes are provided to achieve the best compromise between low power
consumption, short startup time and available wakeup sources:
●Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Sleep mode power consumption: refer to Ta bl e 1 5.
●Low power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (65 kHz), execution from SRAM or Flash memory, and internal regulator
in low power mode to minimize the regulator's operating current. In the Low power run
mode, the clock frequency and the number of enabled peripherals are both limited.
Low power run mode consumption: refer to Table 16.
●Low power sleep mode
This mode is achieved by entering the Sleep mode with the internal voltage regulator in
Low power mode to minimize the regulator’s operating current. In the Low power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
Low power sleep mode consumption: refer to Table 17.
●Stop mode (with or without RTC)
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks in the V
RC and HSE crystal oscillators are disabled. The voltage regulator is in the low power
mode.
The device can be woken up from the Stop mode by any of the EXTI line, in 8 µs. The
EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm(s),
the USB wakeup, the RTC tamper event, the RTC timestamp event, the RTC Wakeup,
the Comparator 1 event or Comparator 2 event.
Stop mode consumption: refer to Tab le 18 .
range limited to 2.0-3.6 V), the CPU runs at up to 32 MHz (refer to
DD
range), the CPU runs at up to 16 MHz (refer to Table 13 for
DD
range), the CPU runs at up to 4 MHz (generated only with the
DD
domain are stopped, the PLL, MSI RC, HSI
CORE
Doc ID 17659 Rev 613/109
Functional overviewSTM32L151xx, STM32L152xx
●Standby mode (with or without RTC)
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire V
domain is powered off. The
CORE
PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. After entering
Standby mode, the RAM and register contents are lost except for registers in the
Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC CSR).
The device exits the Standby mode in 60 µs when an external reset (NRST pin), an
IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or
Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event.
Standby mode consumption: refer to Table 19.
Note:The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the
Stop or Standby mode.
3.2 ARM® Cortex™-M3 core with MPU
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L15xxx is compatible with all ARM tools and
software.
Nested vectored interrupt controller (NVIC)
The ultralow power STM32L15xxx embeds a nested vectored interrupt controller able to
handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
●Interrupt entry vector table address passed directly to the core
●Closely coupled NVIC core interface
●Allows early processing of interrupts
●Processing of late arriving, higher-priority interrupts
●Support for tail-chaining
●Processor state automatically saved
●Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
14/109 Doc ID 17659 Rev 6
STM32L151xx, STM32L152xxFunctional overview
3.3 Reset and supply management
3.3.1 Power supply schemes
●V
●V
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.
DD
Provided externally through V
, V
SSA
= 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
DDA
and PLL (minimum voltage to be applied to V
V
DDA
and V
must be connected to V
SSA
DD
pins.
is 1.8 V when the ADC is used).
DDA
and VSS, respectively.
DD
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
For devices operating between 1.8 and 3.6 V, the BOR is always active at power-on and
ensures proper operation starting from 1.8
option byte loading process starts, either to confirm or modify default thresholds, or to
disable BOR permanently (in which case, the V
BOR thresholds are available through option bytes, starting from 1.8
power consumption in Stop mode, it is possible to automatically switch off the internal
reference voltage (V
below a specified threshold, V
) in Stop mode. The device remains in reset mode when V
REFINT
POR/PDR
circuit.
Note:For devices operating between 1.65 V and 3.6 V, the BOR is permanently disabled.
Consequently, the start-up time at power-on can be decreased down to 1ms typically.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD/VDDA
levels between 1.85
interrupt can be generated when V
V
DD/VDDA
power supply and compares it to the V
V and 3.05 V, chosen by software, with a step around 200 mV. An
is higher than the V
DD/VDDA
threshold. The interrupt service routine can then generate
PVD
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
V. After the 1.8 V BOR threshold is reached, the
min value at power down is 1.65 V). Five
DD
V to 3 V. To reduce the
or V
, without the need for any external reset
BOR
threshold. This PVD offers 7 different
PVD
drops below the V
threshold and/or when
PVD
DD
is
3.3.3 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●MR is used in Run mode (nominal regulation)
●LPR is used in the Low-power run, Low-power sleep and Stop modes
●Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost are lost except for the standby circuitry (wakeup logic,
IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).
Doc ID 17659 Rev 615/109
Functional overviewSTM32L151xx, STM32L152xx
3.3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
●Boot from Flash memory
●Boot from System Memory
●Boot from embedded RAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1 or USART2. For further details please refer to AN2606.
3.4 Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low power modes and ensures clock
robustness. It features:
●Clock prescaler: to get the best tradeoff between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
●Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
●Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●Master clock source: three different clock sources can be used to drive the master
clock:
–1-24 MHz high-speed external crystal (HSE), that can supply a PLL
–16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz)
with a consumption proportional to speed, down to 750 nA typical. When a
32.768 kHz clock source is available in the system (LSE), the MSI frequency can
be trimmed by software down to a ±0.5% accuracy.
●Auxiliary clock source: two ultralow power clock sources that can be used to drive the
LCD controller and the real-time clock:
–32.768 kHz low-speed external crystal (LSE)
–37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
●RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
●USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
●Startup clock: after reset, the microcontroller restarts by default with an internal
2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
16/109 Doc ID 17659 Rev 6
STM32L151xx, STM32L152xxFunctional overview
●Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
●Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
Figure 2.Clock tree
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24 MHz or 32 MHz.
Doc ID 17659 Rev 617/109
Functional overviewSTM32L151xx, STM32L152xx
3.5 Low power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded
decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made
automatically. The RTC provides a programmable alarm and programmable periodic
interrupts with wakeup from Stop and Standby modes.
●The programmable wakeup time ranges from 120 µs to 36 hours
●Stop mode consumption with LSI and Auto-wakeup: 1.2 µA (at 1.8 V) and 1.4 µA (at
3.0 V)
●Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 µA (at 1.8V), 1.6 µA
(at 3.0 V)
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
There are twenty 32-bit backup registers provided to store 80 bytes of user application data.
They are cleared in case of tamper detection.
3.6 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high-current-capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected
to the 16 external interrupt lines.
18/109 Doc ID 17659 Rev 6
STM32L151xx, STM32L152xxFunctional overview
3.7 Memories
The STM32L15xxx devices have the following features:
●Up to 16 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0
wait states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
●The non-volatile memory is divided into three arrays:
–32, 64 or 128 Kbyte of embedded Flash program memory
–4 Kbyte of data EEPROM
–Options bytes
The options bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–Level 0: no readout protection
–Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire)
and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8 DMA (direct memory access)
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers
and ADC.
3.9 LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
●Internal step-up converter to guarantee functionality and contrast control irrespective of
V
. This converter can be deactivated, in which case the V
DD
the voltage to the LCD
●Supports static, 1/2, 1/3, 1/4 and 1/8 duty
●Supports static, 1/2, 1/3 and 1/4 bias
●Phase inversion to reduce power consumption and EMI
●Up to 8 pixels can be programmed to blink
●Unneeded segments and common pins can be used as general I/O pins
●LCD RAM can be updated at any time owing to a double-buffer
●The LCD controller can operate in Stop mode
pin is used to provide
LCD
Doc ID 17659 Rev 619/109
Functional overviewSTM32L151xx, STM32L152xx
3.10 ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L15xxx devices with up to 24
external channels, performing conversions in single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start trigger and injection trigger, to allow the application to synchronize A/D
conversions and timers.
The ADC includes a specific low power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.8 V < V
connected to the ADC_IN16 input channel.
< 3.6 V. The temperature sensor is internally
DDA
3.11 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
●two DAC converters: one for each output channel
●left or right data alignment in 12-bit mode
●synchronized update capability
●noise-wave generation
●triangular-wave generation
●dual DAC channels’ independent or simultaneous conversions
●DMA capability for each channel (including the underrun interrupt)
●external triggers for conversion
●input reference voltage V
Eight DAC trigger inputs are used in the STM32L15xxx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
REF+
20/109 Doc ID 17659 Rev 6
STM32L151xx, STM32L152xxFunctional overview
3.12 Ultralow power comparators and reference voltage
The STM32L15xxx embeds two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
●one comparator with fixed threshold
●one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
–DAC output
–External I/O
–Internal reference voltage (V
REFINT
) or V
submultiple (1/4, 1/2, 3/4)
REFINT
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low power / low current output
buffer (driving current capability of 1
µA typical).
3.13 Routing interface
This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the
comparator and reference voltage output.
3.14 Timers and watchdogs
The ultralow power STM32L15xxx devices include six general-purpose timers, two basic
timers and two watchdog timers.
Ta bl e 3 compares the features of the general-purpose and basic timers.
Table 3.Timer feature comparison
Timer
TIM2,
TIM3,
TIM4
TIM916-bitUp
TIM10,
TIM11
TIM6,
TIM7
Counter
resolution
16-bit
16-bitUp
16-bitUp
Counter
type
Up,
down,
up/down
Prescaler
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
Any integer
between 1
and 65536
factor
DMA request
generation
Ye s4N o
No2No
No1No
Ye s0N o
Capture/compare
channels
Complementary
outputs
Doc ID 17659 Rev 621/109
Functional overviewSTM32L151xx, STM32L152xx
3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)
There are six synchronizable general-purpose timers embedded in the STM32L15xxx
devices (see
TIM2, TIM3, TIM4
These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the
largest packages.
The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11
and TIM9 general-purpose timers via the Timer Link feature for synchronization or event
chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers
can be used to generate PWM outputs.
TIM2, TIM3, TIM4 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and
TIM11 feature one independent channel, whereas TIM9 has two independent channels for
input capture/output compare, PWM or one-pulse mode output. They can be synchronized
with the TIM2, TIM3, TIM4 full-featured general-purpose timers.
Ta bl e 3 for differences).
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.14.2 Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.14.3 SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.14.4 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
22/109 Doc ID 17659 Rev 6
STM32L151xx, STM32L152xxFunctional overview
3.14.5 Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.15 Communication interfaces
3.15.1 I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide
hardware management of the CTS and RTS signals. They support IrDA SIR ENDEC, are
ISO 7816 compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
3.15.3 Serial peripheral interface (SPI)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
3.15.4 Universal serial bus (USB)
The STM32L15xxx embeds a USB device peripheral compatible with the USB full speed
12
Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has
software-configurable endpoint setting and supports suspend/resume. The dedicated
48
MHz clock is generated from the internal main PLL (the clock source must use a HSE
crystal oscillator).
Doc ID 17659 Rev 623/109
Functional overviewSTM32L151xx, STM32L152xx
3.16 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.17 Development support
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L15xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 10.
4. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to V
5. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PC14/PC15 I/Os, respectively, when the LSE oscillator is off ( after reset, the LSE oscillator is off ). The LSE has priority
over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L15xxx reference manual (RM0038).
6. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on ( by setting the HSEON bit
in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off ). The HSE has priority over the GPIO
function.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65
V ≤ V
tested.
≤ 3.6 V voltage range). They are given only as design guidelines and are not
DD
= 25 °C and TA = TAmax (given by
A
Σ).
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditionsFigure 11. Pin input voltage
Stresses above the absolute maximum ratings listed in Tab le 6: Voltage characteristics,
Ta bl e 7: Current characteristics, and Ta bl e 8: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 6.Voltage characteristics
SymbolRatingsMinMaxUnit
VDD–V
(2)
V
IN
|ΔV
DDx
− VSS|Variations between all different ground pins50
|V
SSX
V
ESD(HBM)
1. All main power (VDD, V
supply, in the permitted range.
2. V
maximum must always be respected. Refer to Table 7 for maximum allowed injected current values.
IN
Table 7.Current characteristics
External main supply voltage
SS
(including V
DDA
and VDD)
(1)
Input voltage on five-volt tolerant pinV
Input voltage on any other pinV
|Variations between different V
power pins50
DD
Electrostatic discharge voltage
(human body model)
) and ground (VSS, V
DDA
) pins must always be connected to the external power
SSA
–0.34.0
− 0.3VDD+4.0
SS
− 0.34.0
SS
see Section 6.3.10
SymbolRatings Max.Unit
(1)
(1)
80
80
I
VDD
I
VSS
Total current into VDD/V
Total current out of V
SS
power lines (source)
DDA
ground lines (sink)
Output current sunk by any I/O and control pin25
I
IO
I
INJ(PIN)
ΣI
INJ(PIN)
1. All main power (VDD, V
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.16.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. I
must never be exceeded. Refer to Table 6 for maximum allowed input voltage values.
4. A positive injection is induced by V
must never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ΣI
positive and negative injected currents (instantaneous values).
Output current sourced by any I/O and control pin- 25
Injected current on five-volt tolerant I/O
(2)
Injected current on any other pin
(3)
(4)
Total injected current (sum of all I/O and control pins)
) and ground (VSS, V
DDA
> VDD while a negative injection is induced by V
IN
) pins must always be connected to the external power
J Junction temperature range-40 °C ≤ TA ≤ 105 °C–40 105°C
1. When the ADC is used, refer to Table 50: ADC characteristics.
2. It is recommended to power VDD and V
between V
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 64: Thermal
characteristics on page 104).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max
(see Table 64: Thermal characteristics on page 104).
DD
and V
can be tolerated during power-up and operation.
DDA
from the same source. A maximum difference of 300 mV
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code. The current consumption is measured as described in
consumption measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
●V
●All I/O pins are in input mode with a static value at V
●All peripherals are disabled except when explicitly mentioned
●The Flash memory access time is adjusted depending on f
●Prefetch and 64-bit access are enabled in configurations with 1 wait state
The parameters given in Tab l e 13, Ta bl e 9 and Ta bl e 11 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Ta bl e 9.
Table 13.Current consumption in Run mode, code with data processing running from Flash
Symbol Parameter
DD
range
= 3.6 V
Conditions
f
HCLK
or VSS (no load)
DD
Typ
Figure 13: Current
frequency and voltage
HCLK
(1)
Max
55 °C 85 °C 105 °C
Unit
1 MHz270400400400
4 MHz890102510251025
4 MHz11.31.31.3
8 MHz22.52.52.5
16 MHz3.9555
8 MHz2.16333
16 MHz4.85.55.55.5
32 MHz9.6111111
16 MHz4555
32 MHz9.4111111
I
DD (Run
from
Flash)
Supply
current in
Run mode,
code
executed
from Flash
f
HSE
= f
HCLK
up to 8 MHz,
included
= f
f
HSE
above 8 MHz
(PLL ON)
HCLK
(2)
/2
HSI clock source
(16 MHz)
Range 3,
V
=1.2 V
CORE
VOS[1:0] = 11
Range 2,
V
=1.5 V
CORE
VOS[1:0] = 10
Range 1,
V
=1.8 V
CORE
VOS[1:0] = 01
Range 2,
V
=1.5 V
CORE
VOS[1:0] = 10
Range 1,
V
=1.8 V
CORE
VOS[1:0] = 01
MSI clock, 65 kHz
MSI clock, 524 kHz524 kHz 0.150.185 0.190.2
MSI clock,
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
1. Based on characterization, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
3. Tested in production
Table 16.Current consumption in Low power run mode
SymbolParameterConditionsTyp
TA = -40 °C to 25 °C912
I
DD (LP
Run)
I
Max
DD
(LP
Run)
(2)
Supply
current in
Low power
run mode
Max allowed
current in
Low power
run mode
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
DD
OFF, V
from 1.65 V
to 3.6 V
All
peripherals
OFF, code
executed
from Flash,
from
V
DD
1.65 V to
3.6 V
from
V
DD
1.65 V to
3.6 V
MSI clock, 65 kHz
= 32 kHz
f
HCLK
MSI clock, 65 kHz
f
= 65 kHz
HCLK
MSI clock, 131 kHz
= 131 kHz
f
HCLK
MSI clock, 65 kHz
= 32 kHz
f
HCLK
MSI clock, 65 kHz
f
= 65 kHz
HCLK
MSI clock, 131 kHz
= 131 kHz
f
HCLK
= 85 °C17.524
T
A
TA = 105 °C3146
TA = -40 °C to 25 °C1417
T
= 85 °C2229
A
TA = 105 °C3551
T
= -40 °C to 25 °C3742
A
T
= 55 °C3742
A
TA = 85 °C3742
TA = 105 °C4865
TA = -40 °C to 25 °C2432
TA = 85 °C3342
TA = 105 °C4864
TA = -40 °C to 25 °C3140
TA = 85 °C4048
TA = 105 °C5470
= -40 °C to 25 °C4858
T
A
TA = 55 °C5463
= 85 °C5665
T
A
T
= 105 °C7090
A
Max
(1)
200
Unit
µA
1. Based on characterization, not tested in production, unless otherwise specified.
2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator.
Consumption of the I/Os is not included in this limitation.
Table 18.Typical and maximum current consumptions in Stop mode
SymbolParameterConditionsTyp
Max
(1)
Unit
I
DD (WU
from Stop)
RMS (root mean
square) supply
current during
wakeup time
when exiting
MSI = 4.2 MHz
MSI = 1.05 MHz1.45
TA = -40°C to 25°C
MSI = 65 kHz
(6)
V
= 3.0 V
DD
from Stop mode
1. Based on characterization, not tested in production, unless otherwise specified
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected
3. LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY)
with two 6.8pF loading capacitors.
5. Tested in production
6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the
remaining time of the wakeup period, the current is similar to the Run mode current.
Table 19.Typical and maximum current consumptions in Standby mode
SymbolParameterConditionsTyp
T
= -40 °C to 25 °C1.41.8
A
= 55 °C1.552.5
T
A
= 85 °C2.23
T
A
TA = 105 °C3.55
TA = -40 °C to 25 °C1.552.9
= 55 °C1.73.4
T
A
= 85 °C2.34.3
T
A
I
DD
(Standby
with RTC)
Supply current in Standby
mode with RTC enabled
RTC clocked by LSI (no
independent watchdog)
RTC clocked by LSE (no
independent watchdog)
(2)
TA = 105 °C4.16.3
I
DD
(Standby)
I
DD (WU
from
Standby)
Supply current in Standby
mode (RTC disabled)
RMS supply current during
wakeup time when exiting
from Standby mode
Independent watchdog and
LSI enabled
Independent watchdog and
LSI OFF
= -40 °C to 25 °C1.21.6
T
A
= -40 °C to 25 °C0.30.55
T
A
= 55 °C0.50.8
T
A
TA = 85 °C11.7
= 105 °C2.54
T
A
= 3.0 V
V
DD
= -40 °C to 25 °C
T
A
2
mA
1.45
(1)
Max
Unit
µA
(3)
0.95mA
1. Based on characterization, not tested in production, unless otherwise specified
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
●Sleep mode: the clock source is the clock that was set before entering Sleep mode
●Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
●Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in
Table 20.Typical and maximum timings in Low power modes
SymbolParameterConditionsTyp
Ta bl e 9.
Max
(1)
Unit
t
WUSLEEP
t
WUSLEEP_LP
Wakeup from Sleep modef
Wakeup from Low power
sleep mode
= 262 kHz
f
HCLK
Wakeup from Stop mode,
regulator in Run mode
= 32 MHz0.36
HCLK
f
= 262 kHz
HCLK
Flash enabled
= 262 kHz
f
HCLK
Flash switched OFF
= f
f
HCLK
f
HCLK
= 4.2 MHz8.2
MSI
= f
= 4.2 MHz
MSI
Voltage range 1 and 2
= f
f
HCLK
= 4.2 MHz
MSI
Voltage range 3
t
WUSTOP
Wakeup from Stop mode,
regulator in low power mode
Wakeup from Standby mode
t
WUSTDBY
FWU bit = 1
Wakeup from Standby mode
FWU bit = 0
1. Based on characterization, not tested in production, unless otherwise specified
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: f
(range 3), f
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. Data based on a differential I
conversion (HSI consumption not included).
Fast mode5
(5)
= 32 MHz (range 1), f
= 64kHz (Low power run/sleep), f
HCLK
HCLK
DD measurement between ADC in reset configuration and continuous ADC
4. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
5. Including supply current of internal reference voltage.
6.3.5 External clock source characteristics
High-speed external user clock generated from an external source
Table 22.High-speed external user clock characteristics
(1)
SymbolParameterConditionsMinTypMaxUnit
f
HSE_ext
V
HSEH
V
HSEL
t
w(HSE)
t
w(HSE)
t
r(HSE)
t
f(HSE)
C
in(HSE)
DuCy
I
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions
summarized in
Table 23.Low-speed external user clock characteristics
SymbolParameterConditionsMinTypMaxUnit
Ta bl e 9.
(1)
f
LSE_ext
V
LSEH
V
LSEL
t
w(LSE)
t
w(LSE)
t
r(LSE)
t
f(LSE)
C
IN(LSE)
DuCy
I
1. Guaranteed by design, not tested in production
User external clock source
frequency
OSC32_IN input pin high level
voltage
OSC32_IN input pin low level
voltage
132.7681000kHz
0.7V
DD
V
SS
OSC32_IN high or low timeTBD
OSC32_IN rise or fall timeTBD
OSC32_IN input capacitance0.6pF
Duty cycleTBDTBD%
(LSE)
OSC32_IN Input leakage current V
L
SS
≤ V
IN
≤ V
DD
Figure 14. Low-speed external clock source AC timing diagram
Figure 15. High-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
4. t
HSE driving current
HSE
HSE oscillator power
consumption
g
Oscillator transconductanceStartup3.5
m
Startup time VDD is stabilized1ms
(4)
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
SU(HSE)
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
(3)
)
S
RS = 30 Ω20pF
V
= 3.3 V, V
DD
with 30 pF load
C = 20 pF
= 16 MHz
f
OSC
C = 10 pF
= 16 MHz
f
OSC
IN
= V
SS
3mA
2.5 (startup)
0.7 (stabilized)
2.5 (startup)
0.46 (stabilized)
mA
mA
/V
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5
pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C
and CL2. PCB and MCU pin capacitance must be included (10 pF
L1
can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
L1
microcontrollers” available from the ST website www.st.com.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 25.LSE oscillator characteristics (f
SymbolParameterConditionsMinTypMaxUnit
f
LSE
R
C
I
LSE
I
DD (LSE)
g
t
SU(LSE)
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details;
4. t
SU(LSE)
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Low speed external oscillator
frequency
Feedback resistor1.2MΩ
F
Recommended load capacitance
(2)
versus equivalent serial
resistance of the crystal (R
(3)
)
S
LSE driving currentV
LSE oscillator current
consumption
Oscillator transconductance3µA/V
m
(4)
Startup time VDD is stabilized1s
is the startup time measured from the moment it is enabled (by software) to a stabilized
Note:For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15
pF range selected to match the requirements of the crystal or resonator (see Figure 17).
CL1 and C
capacitance which is the series combination of C
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C
C
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
stray
are usually the same size. The crystal manufacturer typically specifies a load
L2,
and CL2.
L1
stray
where
between 2 pF and 7 pF.
Caution:To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance C
≤ 7 pF. Never use a resonator with a load
L
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C
then C
= CL2 = 8 pF.
L1
= 6 pF and C
L
stray
= 2 pF,
Figure 17. Typical application with a 32.768 kHz crystal
The parameters given in Tab l e 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 9.
High-speed internal (HSI) RC oscillator
Table 26.HSI oscillator characteristics
SymbolParameterConditionsMinTypMaxUnit
f
HSI
TRIM
ACC
t
SU(HSI)
I
DD(HSI)
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Based on characterization, not tested in production.
3. Tested in production.
FrequencyVDD = 3.0 V16MHz
HSI user-trimmed
(1)(2)
resolution
Accuracy of the
(2)
factory-calibrated
HSI
HSI oscillator
HSI oscillator
(2)
startup time
HSI oscillator
(2)
power consumption
Trimming code is not a multiple of 16± 0.40.7%
Trimming code is a multiple of 16± 1.5%
V
= 3.0 V, TA = 25 °C-1
DDA
= 3.0 V, TA = 0 to 55 °C-1.51.5%
V
DDA
= 3.0 V, TA = -10 to 70 °C-22%
V
DDA
V
= 3.0 V, TA = -10 to 85 °C-2.52%
DDA
= 3.0 V, TA = -10 to 105 °C-42%
V
DDA
V
= 1.65 V to 3.6 V
DDA
TA = -40 to 105 °C
(3)
-43%
3.76µs
100140µA
(3)
1
Low-speed internal (LSI) RC oscillator
Table 27.LSI oscillator characteristics
%
SymbolParameterMinTypMaxUnit
(1)
f
LSI
D
LSI
t
su(LSI)
I
DD(LSI)
1. Tested in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Based on characterization, not tested in production.
(2)
MSI oscillator stabilization time
MSI oscillator frequency overshoot
6.3.7 PLL characteristics
The parameters given in Tab l e 29 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Tab l e 9.
Table 29.PLL characteristics
SymbolParameter
f
PLL_IN
PLL input clock
PLL input clock duty cycle4555%
(2)
MSI range 42.5
µs
MSI range 52
MSI range 6,
Voltage range 1
2
and 2
MSI range 3,
Voltage range 3
Any range to
range 5
3
4
MHz
Any range to
range 6
6
Val ue
Unit
MinTypMax
(1)
224MHz
f
PLL_OUT
PLL output clock232MHz
Worst case PLL lock time
t
LOCK
PLL input = 2 MHz
100130µs
PLL VCO = 96 MHz
JitterCycle-to-cycle jitter± 600ps
(PLL)Current consumption on V
I
DDA
(PLL)Current consumption on V
I
DD
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
Table 32.Flash memory endurance and data retention
Val ue
SymbolParameter Conditions
Min
(1)
Typ Max
Unit
Cycling (erase / write )
Program memory
(2)
N
CYC
Cycling (erase / write )
EEPROM data memory
Data retention (program memory) after
10 kcycles at T
A
Data retention (EEPROM data memory)
after 300 kcycles at T
(2)
t
RET
Data retention (program memory) after
10 kcycles at T
A
Data retention (EEPROM data memory)
after 300 kcycles at T
1. Based on characterization not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.
6.3.9 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
●Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
●FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
V
through a 100 pF capacitor, until a functional disturbance occurs. This test is
SS
compliant with the IEC 61000-4-4 standard.
= 85 °C
= 85 °C
A
= 105 °C
= 105 °C
A
T
= -40°C to
A
105 °C
= +85 °C
T
RET
T
= +105 °C
RET
10
300
30
30
10
10
DD
kcycles
years
and
A device reset allows normal operations to be resumed.
The test results are given in Tab l e 33. They are based on the EMS levels and classes
defined in application note AN1709.
Table 33.EMS characteristics
SymbolParameterConditions
= 3.3 V, LQFP100, TA = +25 °C,
V
V
V
FESD
EFTB
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
Fast transient voltage burst limits to be
applied through 100 pF on VDD and V
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●Corrupted program counter
●Unexpected reset
●Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC
61967-2 standard which specifies the test board and the pin loading.
6.3.10 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 35.ESD absolute maximum ratings
SymbolRatingsConditionsClass Maximum value
(1)
Unit
V
ESD(HBM)
V
ESD(CDM)
1. Based on characterization results, not tested in production.
Electrostatic discharge
voltage (human body model)
Electrostatic discharge
voltage (charge device model)
TA = +25 °C, conforming
to JESD22-A114
TA = +25 °C, conforming
to JESD22-C101
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
●A supply overvoltage is applied to each power supply pin
●A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 36.Electrical sensitivities
SymbolParameterConditionsClass
LUStatic latch-up classT
= +105 °C conforming to JESD78AII level A
A
6.3.11 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above V
in order to give an indication of the robustness of the microcontroller in cases when
abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during device characterization.
(for standard pins) should be avoided during normal product operation. However,
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
Table 37.I/O current injection susceptibility
Functional susceptibility
SymbolDescription
Injected current on true open-drain pins-5+0
I
INJ
Injected current on any other pin-5+5
Negative
injection
Positive
injection
Unit
mAInjected current on all 5 V tolerant (FT) pins-5+0
Unless otherwise specified, the parameters given in Ta bl e 38 are derived from tests
performed under conditions summarized in Ta bl e 9. All I/Os are CMOS and TTL compliant.
Table 38.I/O static characteristics
SymbolParameterConditionsMinTyp MaxUnit
V
IL
V
IH
Input low level voltage
Standard I/O input high level voltage
(2)
I/O input high level voltage5.5V
FT
TTL ports
2.7 V
≤ VDD≤ 3.6 V
VSS - 0.30.8
(1)
2
VDD+0.3
V
Input low level voltage
IL
Standard I/O Input high level voltage
V
IH
(5)
I/O input high level voltage
FT
CMOS ports
1.65 V
≤ VDD≤ 3.6 V
CMOS ports
≤ VDD≤ 3.6 V
1.65 V
CMOS ports
1.65 V ≤ V
DD
≤ 2.0 V
–0.30.3V
0.7
(3)(4)
V
DD
VDD+0.3
CMOS ports
≤ VDD≤ 3.6 V
2.0 V
V
Standard I/O Schmitt trigger voltage
hys
hysteresis
(6)
10% V
V
≤ V
IN
≤ V
DD
SS
DD
(7)
I/Os with LCD
≤ V
IN
≤ V
DD
V
SS
I/Os with analog switches
V
≤ V
I
Input leakage current
lkg
(8)(3)
SS
I/Os with analog switches
IN
≤ V
DD
and LCD
V
≤ V
IN
≤ V
DD
SS
I/Os with USB
≤ V
IN
≤ V
DD
V
SS
Standard I/Os
R
R
1. Guaranteed by design.
2. FT = 5V tolerant. To sustain a voltage higher than V
3. Tested in production
4. 0.7V
5. FT = Five-volt tolerant.
6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
7. With a minimum of 200 mV. Based on characterization, not tested in production.
8. The max. value may be exceeded if negative current is injected on adjacent pins.
Weak pull-up equivalent resistor
PU
Weak pull-down equivalent resistor
PD
C
I/O pin capacitance5pF
IO
for 5V-tolerant receiver
DD
(9)(3)
(9)(3)
DD +0.5 the internal pull-up/pull-down resistors must be disabled.
9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum(~10% order).
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20
mA (with the non-standard VOL/V
specifications given in Tab le 39.
OH
in the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in
●The sum of the currents sourced by all the I/Os on V
consumption of the MCU sourced on V
I
(see Ta b le 7).
VDD
●The sum of the currents sunk by all the I/Os on V
consumption of the MCU sunk on V
I
(see Ta b le 7).
VSS
SS
Section 6.2:
plus the maximum Run
cannot exceed the absolute maximum rating
DD,
DD,
plus the maximum Run
SS
cannot exceed the absolute maximum rating
Output voltage levels
Unless otherwise specified, the parameters given in Ta bl e 39 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 9. All I/Os are CMOS and TTL compliant.
Table 39.Output voltage characteristics
SymbolParameterConditionsMinMaxUnit
Output low level voltage for an I/O pin
(1)(2)
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of I
2. Tested in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of I
4. Based on characterization data, not tested in production.
The definition and values of input/output AC characteristics are given in Figure 18 and
Ta bl e 40, respectively.
Unless otherwise specified, the parameters given in Ta bl e 40 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 9.
Table 40.I/O AC characteristics
(1)
OSPEEDRx
[1:0] bit
(1)
value
00
01
10
11
SymbolParameterConditionsMinMax
f
max(IO)out
t
f(IO)out
t
r(IO)out
f
max(IO)out
t
f(IO)out
t
r(IO)out
F
max(IO)out
t
f(IO)out
t
r(IO)out
F
max(IO)out
t
f(IO)out
t
r(IO)out
Maximum frequency
(3)
Output rise and fall time
Maximum frequency
(3)
Output rise and fall time
Maximum frequency
(3)
Output rise and fall time
Maximum frequency
(3)
Output rise and fall time
CL = 50pF, V
= 50pF, V
C
L
C
= 50pF, V
L
= 50pF, V
C
L
CL = 50pF, V
= 50pF, V
C
L
CL = 50pF, V
= 50pF, V
C
L
CL = 50 pF, V
= 50pF, V
C
L
C
= 50pF, V
L
= 50pF, V
C
L
CL = 50 pF, V
= 50pF, V
C
L
C
= 30pF, V
L
C
= 50pF, V
L
= 2.7 V to 3.6 V400
DD
= 1.65 V to 2.7 VTBD
DD
= 2.7 V to 3.6 V625
DD
= 1.65 V to 2.7 VTBD
DD
= 2.7 V to 3.6 V2
DD
= 1.65 V to 2.7 V1
DD
= 2.7 V to 3.6 V125
DD
= 1.65 V to 2.7 VTBD
DD
= 2.7 V to 3.6 V10
DD
= 1.65 V to 2.7 V2
DD
= 2.7 V to 3.6 V25
DD
= 1.65 V to 2.7 VTBD
DD
= 2.7 V to 3.6 V50
DD
= 1.65 V to 2.7 V8
DD
= 2.7 V to 3.6 V5
DD
= 1.65 V to 2.7 VTBD
DD
(2)
Unit
MHz
MHz
MHz
Pulse width of external
-t
EXTIpw
signals detected by the
8
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L15xxx reference manual for a description
of GPIO Port configuration register.
2. Guaranteed by design. Not tested in production.
Unless otherwise specified, the parameters given in Ta bl e 41 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 9.
Table 41.NRST pin characteristics
SymbolParameterConditionsMinTyp Max Unit
V
IL(NRST)
V
IH(NRST)
V
OL(NRST)
(1)
NRST input low level voltageV
(1)
NRST input high level voltage1.4V
= 2 mA
I
OL
NRST output low level
(1)
voltage
2.7 V < VDD < 3.6 V
= 1.5 mA
I
OL
SS
0.8
DD
0.4
1.65 V < VDD < 2.7 V
NRST Schmitt trigger voltage
V
hys(NRST)
V
F(NRST)
V
NF(NRST)
1. Guaranteed by design, not tested in production.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
Table 41. Otherwise the reset will not be taken into account by the device.
max level specified in
IL(NRST)
6.3.14 TIM timer characteristics
The parameters given in the following table are guaranteed by design.
Refer to Section 6.3.11: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).
Table 42.TIMx
(1)
characteristics
SymbolParameterConditionsMinMaxUnit
t
res(TIM)
f
EXT
Res
TIM
Timer resolution time
Timer external clock
frequency on CH1 to CH4
f
TIMxCLK
0
f
TIMxCLK
= 32 MHz31.25ns
= 32 MHz016MHz
Timer resolution16bit
16-bit counter clock period
t
COUNTER
t
MAX_COUNT
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
when internal clock is
selected (timer’s prescaler
disabled)
Unless otherwise specified, the parameters given in Ta bl e 43 are derived from tests
performed under ambient temperature, f
summarized in
The line
Ta bl e 9.
2
I
C interface meets the requirements of the standard I2C communication protocol
with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When
configured as open-drain, the PMOS connected between the I/O pin and V
but is still present.
The I2C characteristics are described in Ta b le 43. Refer also to Section 6.3.11: I/O current
injection characteristics
(SDA and SCL)
Table 43.I2C characteristics
SymbolParameter
.
for more details on the input/output alternate function characteristics
frequency and VDD supply voltage conditions
PCLK1
DD
Standard mode I
2C(1)
Fast mode I2C
MinMaxMinMax
is disabled,
(1)(2)
Unit
t
w(SCLL)
t
w(SCLH)
t
su(SDA)
t
h(SDA)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
h(STA)
t
su(STA)
t
su(STO)
t
w(STO:STA)
C
Guaranteed by design, not tested in production.
1.
2. f
PCLK1
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
3.
period of SCL signal.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
4.
undefined region of the falling edge of SCL.
SCL clock low time4.71.3
SCL clock high time4.00.6
SDA setup time250100
SDA data hold time0
(3)
SDA and SCL rise time100020 + 0.1C
(4)
0
b
900
300
(3)
SDA and SCL fall time300300
Start condition hold time4.00.6
Repeated Start condition
setup time
4.70.6
Stop condition setup time4.00.6 μs
Stop to Start condition time
(bus free)
Capacitive load for each bus
b
line
must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, f
conditions summarized in
Ta bl e 9.
Refer to Section 6.3.11: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 45.SPI characteristics
SymbolParameterConditionsMinMax
(1)
frequency and VDD supply voltage
PCLKx
(2)
Unit
f
SCK
1/t
c(SCK)
t
r(SCK)
t
f(SCK)
DuCy(SCK)
t
su(NSS)
t
h(NSS)
t
w(SCKH)
t
w(SCKL)
t
su(MI)
t
su(SI)
t
h(MI)
t
h(SI)
t
a(SO)
t
dis(SO)
t
v(SO)
t
v(MO)
t
h(SO)
t
h(MO)
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the
data.
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the
data in Hi-Z.
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock duty
cycle
NSS setup time Slave mode4t
NSS hold timeSlave mode2t
SCK high and low time
Data input setup time
Data input hold time
(3)
Data output access timeSlave mode, f
(4)
Data output disable time Slave mode TBD TBD
(2)
Data output valid timeSlave mode (after enable edge) TBD
(2)
Data output valid timeMaster mode (after enable edge) TBD
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for I
accuracy.
3. Based on characterization, not tested in production.
Figure 27. Maximum dynamic current consumption on V
supply pin during ADC
REF+
conversion
Table 52.R
Ts
(cycles)
AIN
Ts
(µs)
max for f
2.4 V < V
= 16 MHz
ADC
Multiplexed channelsDirect channels
< 3.6 V 1.8 V < V
DDA
40.25Not allowedNot allowed0.7Not allowed
(1)
R
max (kohm)
AIN
< 2.4 V 2.4 V < V
DDA
< 3.3 V 1.8 V < V
DDA
DDA
< 2.4 V
90.56250.8Not allowed2.01.0
1612.00.84.03.0
241.53.01.86.04.5
4836.84.015.010.0
96615.010.030.020.0
1921232.025.050.040.0
3842450.050.050.050.0
1. Guaranteed by design, not tested in production.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 28 or Figure 29,
depending on whether V
ceramic (good quality). They should be placed as close as possible to the chip.
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and
last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = V
REF+
/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and
0xFFF when buffer is OFF, and from code giving 0.2 V and (V
– 0.2) V when buffer is ON.
DDA
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 30. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
R
C
LOAD
LOAD
ai17157
12-bit
digital to
analog
converter
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DACx_OUT
6.3.18 Temperature sensor characteristics
Table 54.TS characteristics
SymbolParameterMinTypMaxUnit
(1)
T
L
Avg_Slope
V
110
I
(TEMP)
DDA
(3)
t
START
S_temp
byte.
(4)(3)
T
1. Guaranteed by characterization, not tested in production.
2. Measured at VDD = 3 V ±10 mV. V110 ADC conversion result is stored in the TS_Factory_CONV_V110
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.