ST STM32G4A1xE User Manual

STM32G4A1xE

Arm® Cortex®-M4 32-bit MCU+FPU, 170 MHz / 213 DMIPS, up to 512 KB Flash, 112 KB SRAM, rich analog, math accelerator, AES

Features

•Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions

•Operating conditions:

–VDD, VDDA voltage range: 1.71 V to 3.6 V

•Mathematical hardware accelerators

–CORDIC for trigonometric functions acceleration

–FMAC: filter mathematical accelerator

•Memories

–512 Kbytes of Flash memory with ECC support, proprietary code readout protection (PCROP), securable memory area, 1 Kbyte OTP

–96 Kbytes of SRAM, with hardware parity check implemented on the first 32 Kbytes

–Routine booster: 16 Kbytes of SRAM on instruction and data bus, with hardware parity check (CCM SRAM)

–Quad-SPI memory interface

•Reset and supply management

–Power-on/power-down reset (POR/PDR/BOR)

–Programmable voltage detector (PVD)

–Low-power modes: sleep, stop, standby and shutdown

–VBAT supply for RTC and backup registers

•Clock management

–4 to 48 MHz crystal oscillator

–32 kHz oscillator with calibration

–Internal 16 MHz RC with PLL option (± 1%)

–Internal 32 kHz RC oscillator (± 5%)

•Up to 86 fast I/Os

–All mappable on external interrupt vectors

Datasheet - production data

FBGA

			UFBGA64
LQFP48 (7 x 7 mm) UFQFPN32 (5 x 5 mm)						WLCSP64
LQFP64 (10 x 10 mm) UFQFPN48 (7 x 7 mm)			(5 x 5 mm)			(Pitch 0.4)
LQFP80 (12 x 12 mm)
LQFP80 (14 x 14 mm)
LQFP100 (14 x 14 mm)

–Several I/Os with 5 V tolerant capability

•Interconnect matrix

•16-channel DMA controller

•3 x ADCs 0.25 µs (up to 36 channels). Resolution up to 16-bit with hardware oversampling, 0 to 3.6 V conversion range

•4 x 12-bit DAC channels

–2 x buffered external channels 1 MSPS

–2 x unbuffered internal channels 15 MSPS

•4 x ultra-fast rail-to-rail analog comparators

•4 x operational amplifiers that can be used in PGA mode, all terminals accessible

•Internal voltage reference buffer (VREFBUF) supporting three output voltages (2.048 V, 2.5 V, 2.9 V)

•15 timers:

–1 x 32-bit timer and 2 x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

–3 x 16-bit 8-channel advanced motor control timers, with up to 8 x PWM channels, dead time generation and emergency stop

–1 x 16-bit timer with 2 x IC/OCs, one OCN/PWM, dead time generation and emergency stop

–2 x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop

–2 x watchdog timers (independent, window)

–1 x SysTick timer: 24-bit downcounter

–2 x 16-bit basic timers

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This is information on a product in full production.

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			STM32G4A1xE
	– 1 x low-power timer		– 1 x SAI (serial audio interface)
	• Calendar RTC with alarm, periodic wakeup		– USB 2.0 full-speed interface with LPM and
	from stop/standby		BCD support
	• Communication interfaces		– IRTIM (infrared interface)
			– USB Type-C™ /USB power delivery
	– 2 x FDCAN controller supporting flexible
			controller (UCPD)
		data rate
			• True random number generator (RNG)
	– 3 x I2C Fast mode plus (1 Mbit/s) with
		20 mA current sink, SMBus/PMBus,	• CRC calculation unit, 96-bit unique ID
		wakeup from stop	• AES: 128/256-bit key encryption hardware
	– 5 x USART/UARTs (ISO 7816 interface,
			accelerator
		LIN, IrDA, modem control)
			• Development support: serial wire debug
	–	1 x LPUART
			(SWD), JTAG, Embedded Trace Macrocell™
	–	3 x SPIs, 4 to 16 programmable bit frames,
		2 x with multiplexed half duplex I2S
		interface

	Table 1. Device summary
Reference	Part number
STM32G4A1xE	STM32G4A1CE, STM32G4A1KE, STM32G4A1ME, STM32G4A1RE, STM32G4A1VE

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Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
2	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
3	Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	3.1	Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.2	Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . .	17
	3.3	Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.4	Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.5	Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	3.6	Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.7	Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	3.8	CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.9	Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.10	Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . .	21
	3.11	Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21

3.11.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.12 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.13 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.16 DMA request router (DMAMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.17.1	Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . .	28
3.17.2	Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . .	28
3.18 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29

3.18.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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3.18.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.4 Operational amplifier internal output (OPAMPxINT): . . . . . . . . . . . . . . . 30

3.19 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.20 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.22 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.24 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 32 3.25 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.25.1 Advanced motor control timer (TIM1, TIM8, TIM20) . . . . . . . . . . . . . . . 34

3.25.2General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.25.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.25.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.25.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.25.6 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.25.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.26 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 37 3.27 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.28 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.29 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.30Universal synchronous/asynchronous receiver transmitter (USART) . . . 40

3.31Low-power universal asynchronous receiver transmitter (LPUART) . . . . 41

3.32 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.33 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.33.1 SAI peripheral supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.34 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 43 3.35 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.36 USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 43 3.37 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.38 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.39 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.39.1	Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . .	45
3.39.2	Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45

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4	Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		46
	4.1	UFQFPN32 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	4.2	UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
	4.3	LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
	4.4	WLCSP64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	4.5	LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48
	4.6	UFBGA64 ballout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	49
	4.7	LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	50
	4.8	LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	51
	4.9	Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	52
	4.10	Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	64

5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			70
	5.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		70
		5.1.1	Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
		5.1.2	Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
		5.1.3	Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
		5.1.4	Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
		5.1.5	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	70
		5.1.6	Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71
		5.1.7	Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . .	72
	5.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		72
	5.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		74

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 75 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 75 5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.6Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 120 5.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.3.18 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 121 5.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 136 5.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 143 5.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 147 5.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

5.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.3.25 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

5.3.26 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 153 5.3.27 QUADSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.3.28 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

6	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		166
	6.1	UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	166
	6.2	UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	169
	6.3	LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	172
	6.4	WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	176
	6.5	LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	179
	6.6	UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	182
	6.7	LQFP80 12 x 12 mm package information . . . . . . . . . . . . . . . . . . . . . . .	185
	6.8	LQFP80 14 x 14 mm package information . . . . . . . . . . . . . . . . . . . . . . .	188
	6.9	LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	191
	6.10	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	194
		6.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 195
		6.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . .	196
7	Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		198
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		199

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STM32G4A1xE	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 2. STM32G4A1xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. STM32G4A1xE peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 4. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 8. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 9. USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 10. SAI implementation for the features implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 11. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 12. STM32G4A1xE pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 13. Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 18. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 20. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 21. Current consumption in Run and Low-power run modes, code with data

processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF) . . 79 Table 22. Current consumption in Run and Low-power run modes,

code with data processing running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 23. Typical current consumption in Run and Low-power run modes, with different codes

running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 83 Table 24. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 25. Typical current consumption in Run and Low-power run modes, with different codes

running from SRAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 26. Typical current consumption in Run and Low-power run modes, with different codes

running from CCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 27. Current consumption in Sleep and Low-power sleep mode Flash ON . . . . . . . . . . . . . . . . 87 Table 28. Current consumption in low-power sleep modes, Flash in power-down. . . . . . . . . . . . . . . 88 Table 29. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 30. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 31. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 32. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 33. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 34. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 35. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 36. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 37. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 38. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 39. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 40. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 42. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 44. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 45. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 49. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 52. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 53. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 54. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 55. I/O (except FT_c) AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 56. I/O FT_c AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 58. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 59. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 60. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 61. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 62. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 63. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 64. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 65. ADC accuracy (Multiple ADCs operation) - limited test conditions 1 . . . . . . . . . . . . . . . . 132 Table 66. ADC accuracy (Multiple ADCs operation) - limited test conditions 2 . . . . . . . . . . . . . . . . 133 Table 67. ADC accuracy (Multiple ADCs operation) - limited test conditions 3 . . . . . . . . . . . . . . . . 134 Table 68. DAC 1MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 69. DAC 1MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 70. DAC 15MSPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 71. DAC 15MSPS accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Table 72. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 73. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 74. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 75. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Table 76. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 77. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 78. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 79. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 80. WWDG min/max timeout value at 170 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 81. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 82. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 83. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 84. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 85. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 86. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 87. USART electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Table 88. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 89. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 90. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 91. UFQFPN32 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 92. UFQFPN48 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 93. LQFP48 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 94. WLCSP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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Table 95. WLCSP64 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 96. LQFP64 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 97. UFBGA64 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 98. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 183 Table 99. LQFP80 12 x 12 mm - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 100. LQFP80 14 x 14 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 101. LQPF100 - mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 102. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 103. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 104. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

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List of figures	STM32G4A1xE

List of figures

Figure 1. STM32G4A1xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 2. Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 3. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 4. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 5. STM32G4A1xE UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 6. STM32G4A1xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 7. STM32G4A1xE LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 8. STM32G4A1xE WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 9. STM32G4A1xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 10. STM32G4A1xE UFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 11. STM32G4A1xE LQFP80 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 12. STM32G4A1xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 13. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 14. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 15. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 16. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 17. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 22. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 23. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 24. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 25. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 26. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 27. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 28. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 29. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Figure 30. VREFOUT_TEMP in case VRS = 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 31. VREFOUT_TEMP in case VRS = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 32. VREFOUT_TEMP in case VRS = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 33. OPAMP noise density @ 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 35. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 36. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 37. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 38. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 39. Quad SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 40. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 41. UFQFPN32 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 42. UFQFPN32 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 43. UFQFPN32 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 44. UFQFPN48 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 45. UFQFPN48 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure 46. UFQFPN48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 47. LQFP48 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 48. LQFP48 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

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STM32G4A1xE		List of figures
Figure 49. LQFP48 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . 175
Figure 50.	WLCSP64 - outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 176
Figure 51.	WLCSP64 - recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 177
Figure 52. WLCSP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 178
Figure 53.	LQFP64 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 179
Figure 54.	LQFP64 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 180
Figure 55. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 181
Figure 56.	UFBGA64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 182
Figure 57. UFBGA64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 183
Figure 58. UFBGA64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 184
Figure 59. LQFP80 12 x 12 mm - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 185
Figure 60. LQFP80 12 x 12 mm - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 186
Figure 61. LQFP80 12 x 12 mm top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 187
Figure 62. LQFP80 14 x 14 mm - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 188
Figure 63. LQFP80 14 x 14 mmrecommended footprint . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 189
Figure 64. LQFP80 14 x 14 mm - top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . 190
Figure 65.	LQFP100 - outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 191
Figure 66.	LQFP100 - recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 192
Figure 67.	LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 193

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Introduction	STM32G4A1xE

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of the STM32G4A1xE microcontrollers.

This document should be read in conjunction with the reference manual RM0440 “STM32G4 Series advanced Arm® 32-bit MCUs”. The reference manual is available from the STMicroelectronics website www.st.com.

For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 technical reference manual, available from the www.arm.com website.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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STM32G4A1xE	Description

2 Description

The STM32G4A1xE devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz.

The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.

These devices embed high-speed memories (512 Kbytes of Flash memory, and 112 Kbytes of SRAM), a Quad SPI Flash memory interface, an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

The devices also embed several protection mechanisms for embedded Flash memory and SRAM: readout protection, write protection, securable memory area and proprietary code readout protection.

The devices embed peripherals allowing mathematical/arithmetic function acceleration (CORDIC for trigonometric functions and FMAC unit for filter functions).

They offer three fast 12-bit ADCs (5 Msps), four comparators, four operational amplifiers, four DAC channels (2 external and 2 internal), an internal voltage reference buffer, a lowpower RTC, one general-purpose 32-bit timers, three 16-bit PWM timers dedicated to motor control, seven general-purpose 16-bit timers, and one 16-bit low-power timer.

They also feature standard and advanced communication interfaces such as:

-Three I2Cs

-Three SPIs multiplexed with two half duplex I2Ss

-Three USARTs, two UARTs and one low-power UART.

-Two FDCANs

-One SAI

-USB device

-UCPD

The STM32G4A1xE devices embed an AES.

The devices operate in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.

Some independent power supplies are supported including an analog independent supply input for ADC, DAC, OPAMPs and comparators. A VBAT input allows backup of the RTC and the registers.

The STM32G4A1xE family offers 9 packages from 32-pin to 100-pin.

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Description											STM32G4A1xE
			Table 2. STM32G4A1xE features and peripheral counts
Peripheral				STM32G4A1KE		STM32G4A1CE		STM32G4A1RE		STM32G4A1ME	STM32G4A1VE
Flash memory				512 KB		512 KB		512 KB		512 KB	512 KB
SRAM1								80 KB
SRAM2								16 KB
CCM SRAM								16 KB
QUADSPI							1
		Advanced						3 (16-bit)
		motor control
		General						5 (16-bit)
		purpose						1 (32-bit)
		Basic						2 (16-bit)
		Low power						1 (16-bit)
		SysTick timer					1
Timers
		Watchdog
		timers					2
		(independent,
		window)
		PWM channels		23		32		38		38	44
		(all)
		PWM channels
		(except compl		23		26		28		28	29
		ementary)
		SPI(I2S)(1)					3 (2)
		I2C					3
		USART		2					3
Comm.	UART				0				2
interfac	LPUART						1
es
		FDCANs					2
		USB device						Yes
		UCPD						Yes
		SAI						Yes
RTC								Yes
Tamper pins				1			2			2	3
Random number								Yes
generator
AES								Yes
CORDIC								Yes
FMAC								Yes

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STM32G4A1xE							Description
Table 2. STM32G4A1xE features and peripheral counts (continued)
Peripheral	STM32G4A1KE		STM32G4A1CE	STM32G4A1RE	STM32G4A1ME	STM32G4A1VE
GPIOs	26		38 in LQFP48	52	66		86
			42 in
Wakeup pins	2		UFQFPN48	4	4		5
			3
				3
12-bit ADCs
			18 in LQFP48
Number of channels
	11		19 in	24	32		36
			UFQFPN48
12-bit DAC				2
Number of channels			4 (2 external + 2 internal)
Internal voltage				Yes
reference buffer
Analog comparator				4
Operational amplifiers				4
Max. CPU frequency				170 MHz
Operating voltage				1.71 V to 3.6 V
Operating temperature		Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
			LQFP48/	LQFP64/
Packages	UFQFPN32			UFBGA4	LQFP80		LQFP100
			UFQFPN48
				WLCSP64

1. The SPI2/3 interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.

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Description	STM32G4A1xE

Figure 1. STM32G4A1xE block diagram

JTRST, JTDI,
JTCK/SWCLK	JTAG & SW	MPU
JTDO/SWD, JTDO
	ETM	NVIC
TRACECK
		FPU
TRACED(3:0)	Arm®
		D-BUS
			<![if ! IE]> <![endif]>/5M8S
	Cortex-M4			<![if ! IE]> <![endif]>ACCEL/ CACHE
		S-BUS
	170 MHz				FLASH 512 KB
		I-BUS	<![if ! IE]> <![endif]>MATRIX-
	GP-DMA2	8 Chan		CCM SRAM 16 KB
			<![if ! IE]> <![endif]>BUS
	GP-DMA1	8 Chan		SRAM2 16 KB
			<![if ! IE]> <![endif]>AHB
				SRAM1 80 KB
	DMAMUX			AHB2
	@VDDA				RNG
					RNB1
Ain ADC	SAR ADC1	IF			analog
	SAR ADC2
					CORDIC

	SAR ADC3			IF			FMAC
						<![if ! IE]> <![endif]>AHB1
PA(15:0)	GPIO PORT A
PB(15:0)	USARTGPIO2MBpsPORT B						@VDD
							LSI
PC(15:0)	USARTGPIO2MBpsPORT C
							PLL
PD(15:0)
	USART 2MBps						HSI
PE(15:0)	GPIO PORT D
	USARTGPIO2MBpsPORT E						HSI48
PF(10:9,2:0)
	USARTGPIO2MBpsPORT F
PG(10:10)	GPIO PORT G
	USART 2MBps
							RESET&
FS, SCK, SD,	SAI1						CLOCKCTRL
MCLK as AF
							peripheralclocks
86 AFP	EXT IT. WKUP						and system
	USART 2MBps
4 PWM,4PWM,	TIMER20	16b PWM
ETR,BKIN as F							CRC
4 PWM,4PWM,		16b PWM
	TIMER1
ETR,BKIN as F
4 PWM,4PWM,	TIMER8	16b PWM				AHB/APB2 AHB/APB1
ETR,BKIN as F
CH as AF	USARTTIMER152MBps		16b
CH as AF	USARTTIMER162MBps		16b		<![if ! IE]> <![endif]>APB2	PWRCTRL
CH as AF16b	USARTTIMER172MBps		16b			WinWATCHDOG
						LP timer1

QUADSPI
		CLK, NCS, BK1_IO[3:0]

TinyAES

@VDDA

CH1

DAC1 OUT1/OUT2

CH2

CH1

DAC3

CH2

POWER MNGT

VDD = 1.71 to 3.6V

VDD12

VOLT. REG.

VSS

3.3V TO 1.2V

@VDD

SUPPLY

POR

SUPERVISION

POR / BOR

Reset

Int

PVD, PWM

VDD, VSS,

VDDA, VSSA,

RESET

XTAL OSC

OSC_IN

4-48MHz

OSC_OUT

IWDG

Standby Interface

VBAT = 1.55 to 3.6V

@VBAT

OSC32_IN

XTAL 32kHz

OSC_OUT

RTC AWU

RTC_OUT

BKPREG

RTC_TS

RTC_TAMPx

RTC Interface

TIMER2

4 CH, ETR as AF

TIMER3&4

4 CH, ETR as AF

LP_UART1

RX, TX as AF

SCL, SDA, SMBAL as AF

I2C1&2&3

RX, TX, SCK,CTS,

RTS as AF

MOSI, MISO

SCK, NSS as AF

	USART12MBpsSmcard		<![if ! IE]> <![endif]>60MHzAPB1APB2
		irDA
		SPI 1
	USART 2MBps
		SysCfg
			@VDDA
	Vref_Buf	COMP	OPAMP
		1,2,3,4	1,2,3,6

TIMER6		16b trigg	USART2&3
TIMER7		16b trigg	UART4&5
CRS			SPI2&3
				CAN1&2
	<![if ! IE]> <![endif]>PHY	USBPD	<![if ! IE]> <![endif]>FIFO	Device
				USB
	CC1
	CC2

Smcard						RX, TX, SCK,
	irDA					CTS, RTS as AF
						RX, TX, CTS,
	irDA					RTS as AF
I2S half						MOSI, MISO, SCK
	duplex					NSS, as AF
	<![if ! IE]> <![endif]>FIFO					RX,TX as AF
	<![if ! IE]> <![endif]>PHY
						D-
						D+

MSv63469V1

1. AF: alternate function on I/O pins.

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STM32G4A1xE	Functional overview

3 Functional overview

3.1Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of the MCU implementation, with a reduced pin count and with low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm® Cortex®-M4 with FPU 32-bit RISC processor features an exceptional codeefficiency, delivering the expected high-performance from an Arm core in a memory size usually associated with 8-bit and 16-bit devices.

The processor supports a set of DSP instructions which allows an efficient signal processing and a complex algorithm execution. Its single precision FPU speeds up the software development by using metalanguage development tools to avoid saturation.

With its embedded Arm core, the STM32G4A1xE family is compatible with all Arm tools and software.

Figure 1 shows the general block diagram of the STM32G4A1xE devices.

3.2Adaptive real-time memory accelerator (ART accelerator)

The ART accelerator is a memory accelerator that is optimized for the STM32 industrystandard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies.

3.3Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to the memory and to prevent one task to accidentally corrupt the memory or the resources used by any other active task. This memory area is organized into up to 8 protected areas, which can be divided in up into 8 subareas each. The protection area sizes range between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.4Embedded Flash memory

The STM32G4A1xE devices feature 512 kbytes of embedded Flash memory which is available for storing programs and data.

Flexible protections can be configured thanks to the option bytes:

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Functional overview	STM32G4A1xE

•Readout protection (RDP) to protect the whole memory. Three levels of protection are available:

–Level 0: no readout protection

–Level 1: memory readout protection; the Flash memory cannot be read from or written to if either the debug features are connected or the boot in RAM or bootloader are selected

–Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This selection is irreversible.

•Write protection (WRP): the protected area is protected against erasing and programming.

•Proprietary code readout protection (PCROP): a part of the Flash memory can be protected against read and write from third parties. The protected area is execute-only and it can only be reached by the STM32 CPU as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0.

•Securable memory area: a part of Flash memory can be configured by option bytes to be securable. After reset this securable memory area is not secured and it behaves like the remainder of main Flash memory (execute, read, write access). When secured, any access to this securable memory area generates corresponding read/write error.

Purpose of the Securable memory area is to protect sensitive code and data (secure keys storage) which can be executed only once at boot, and never again unless a new reset occurs.

The Flash memory embeds the error correction code (ECC) feature supporting:

•Single error detection and correction

•Double error detection

•The address of the ECC fail can be read in the ECC register

•1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The OTP area is available in Bank 1 only. The OTP data cannot be erased and can be written only once.

3.5Embedded SRAM

STM32G4A1xE devices feature 112 Kbytes of embedded SRAM. This SRAM is split into three blocks:

•80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the SRAM1 through the System Bus (or through the I-Code/D-Code buses when boot from SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP register). The first 32 Kbytes of SRAM1 support hardware parity check.

•16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the SRAM2 through the System bus. SRAM2 can be kept in stop and standby modes.

•16 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU through I-Code/D-Code bus for maximum performance.

It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1, DMA2) through SBUS contiguously to SRAM1 and SRAM2.The CCM SRAM supports hardware parity check and can be write-protected with 1-Kbyte granularity.

•The memory can be accessed in read/write at max CPU clock speed with 0 wait states.

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3.6Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, QUADSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 2. Multi-AHB bus matrix

Cortex®-M4

DMA1 DMA2

with FPU

<![if ! IE]> <![endif]>I-bus

<![if ! IE]> <![endif]>D-bus

<![if ! IE]> <![endif]>S-bus

ICode

DCode

<![if ! IE]> <![endif]>ACCEL
		FLASH
		512 KB
		SRAM1
		CCM
		SRAM
		SRAM2
		AHB1
		peripherals
		AHB2
		peripherals

QUADSPI

BusMatrix-S

MS52814V1

3.7Boot modes

At startup, a BOOT0 pin (or nBOOT0 option bit)and an nBOOT1 option bit are used to select one of three boot options:

•Boot from user Flash

•Boot from system memory

•Boot from embedded SRAM

The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.

The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).

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3.8CORDIC

The CORDIC provides hardware acceleration of certain mathematical functions, notably trigonometric, commonly used in motor control, metering, signal processing and many other applications.

It speeds up the calculation of these functions compared to a software implementation, allowing a lower operating frequency, or freeing up processor cycles in order to perform other tasks.

Cordic features

•24-bit CORDIC rotation engine

•Circular and Hyperbolic modes

•Rotation and Vectoring modes

•Functions: Sine, Cosine, Sinh, Cosh, Atan, Atan2, Atanh, Modulus, Square root, Natural logarithm

•Programmable precision up to 20-bit

•Fast convergence: 4 bits per clock cycle

•Supports 16-bit and 32-bit fixed point input and output formats

•Low latency AHB slave interface

•Results can be read as soon as ready without polling or interrupt

•DMA read and write channels

3.9Filter mathematical accelerator (FMAC)

The filter mathematical accelerator unit performs arithmetic operations on vectors. It comprises a multiplier/accumulator (MAC) unit, together with address generation logic, which allows it to index vector elements held in local memory.

The unit includes support for circular buffers on input and output, which allows digital filters to be implemented. Both finite and infinite impulse response filters can be realized.

The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing up the processor for other tasks. In many cases it can accelerate such calculations compared to a software implementation, resulting in a speed-up of time critical tasks.

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FMAC features

•16 x 16-bit multiplier

•24+2-bit accumulator with addition and subtraction

•16-bit input and output data

•256 x 16-bit local memory

•Up to three areas can be defined in memory for data buffers (two input, one output), defined by programmable base address pointers and associated size registers

•Input and output sample buffers can be circular

•Buffer “watermark” feature reduces overhead in interrupt mode

•Filter functions: FIR, IIR (direct form 1)

•AHB slave interface

•DMA read and write data channels

3.10Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator with polynomial value and size.

Among other applications, the CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the Flash memory integrity.

The CRC calculation unit helps to compute a signature of the software during runtime, which can be ulteriorly compared with a reference signature generated at link-time and which can be stored at a given memory location.

3.11Power supply management

3.11.1Power supply schemes

The STM32G4A1xE devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent supplies, can be provided for specific peripherals:

•VDD = 1.71 V to 3.6 V

VDD is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks. It is provided externally through the VDD pins.

•VDDA = 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum VDDA voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation).

VDDA is the external analog power supply for A/D converters, D/A converters, voltage reference buffer, operational amplifiers and comparators. The VDDA voltage level is independent from the VDD voltage and should preferably be connected to VDD when these peripherals are not used.

•VBAT = 1.55 V to 3.6 V

VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.

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•VREF-, VREF+

VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled.

When VDDA < 2 V VREF+ must be equal to VDDA.

When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA.

The internal voltage reference buffer supports three output voltages, which are configured with VRS bits in the VREFBUF_CSR register:

–VREF+ = 2.048 V

–VREF+ = 2.5 V

–VREF+ = 2.9 V

VREF- is double bonded with VSSA.

3.11.2Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes (except for Shutdown mode). The BOR ensures proper operation of the device after poweron and during power down. The device remains in reset mode when the monitored supply voltage VDD is below a specified threshold, without the need for an external reset circuit.

The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected through option bytes.The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

In addition, the device embeds a peripheral voltage monitor which compares the independent supply voltages VDDA, with a fixed threshold in order to ensure that the peripheral is in its functional supply range.

3.11.3Voltage regulator

Two embedded linear voltage regulators, main regulator (MR) and low-power regulator (LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby and Shutdown modes, both regulators are powered down and their outputs set in highimpedance state, such as to bring their current consumption close to zero.

The device supports dynamic voltage scaling to optimize its power consumption in Run mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted according to the system’s maximum operating frequency.

The main regulator (MR) operates in the following ranges:

•Range 1 boost mode with the CPU running at up to 170 MHz.

•Range 1 normal mode with CPU running at up to 150 MHz.

•Range 2 with a maximum CPU frequency of 26 MHz.

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3.11.4Low-power modes

By default, the microcontroller is in Run mode after system or power Reset. It is up to the user to select one of the low-power modes described below:

•Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

•Low-power run mode: This mode is achieved with VCORE supplied by the low-power regulator to minimize the regulator's operating current. The code can be executed from SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be clocked by HSI16.

•Stop mode: In Stop mode, the device achieves the lowest power consumption while retaining the SRAM and register contents. All clocks in the VCORE domain are stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.

•Standby mode: The Standby mode is used to achieve the lowest power consumption with brown-out reset, BOR. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are also powered down. The RTC can remain active (Standby mode with RTC, Standby mode without RTC). The BOR always remains active in Standby mode. For each I/O, the software can determine whether a pull-up, a pull-down or no resistor shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM and register contents are lost except for registers in the RTC domain and standby circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE (CSS on LSE).

•Shutdown mode: The Shutdown mode allows to achieve the lowest power consumption. The internal regulator is switched off to power down the VCORE domain. The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC). The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this mode. Therefore, switching to RTC domain is not supported. SRAM and register contents are lost except for registers in the RTC domain. The device exits Shutdown mode upon external reset event (NRST pin), IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event (alarm, periodic wakeup, timestamp, tamper).

3.11.5Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal.

3.11.6VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when there is no external battery and when an external supercapacitor is present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-tamper detection pins are available in VBAT mode.

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	The VBAT operation is automatically activated when VDD is not present. An internal VBAT
	battery charging circuit is embedded and can be activated when VDD is present.
Note:	When the microcontroller is supplied from VBAT, neither external interrupts nor RTC
	alarm/events exit the microcontroller from the VBAT operation.

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3.12Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes.

Table 3. STM32G4A1xE peripherals interconnect matrix

				<![if ! IE]> <![endif]>Run	<![if ! IE]> <![endif]>Sleep	<![if ! IE]> <![endif]>run	<![if ! IE]> <![endif]>Stop
	Interconnect source	Interconnect	Interconnect action			<![if ! IE]> <![endif]>power-
		destination
						<![if ! IE]> <![endif]>Low
		TIMx	Timers synchronization or chaining	Y	Y	Y	-
		ADCx	Conversion triggers	Y	Y	Y	-
	TIMx	DACx
		DMA	Memory to memory transfer trigger	Y	Y	Y	-
		COMPx	Comparator output blanking	Y	Y	Y	-
	TIM16/TIM17	IRTIM	Infrared interface output generation	Y	Y	Y	-
		TIM1, 8, 20	Timer input channel, trigger, break	Y	Y	Y	-
		TIM2, 3, 4	from analog signals comparison
	COMPx
		LPTIMER1	Low-power timer triggered by	Y	Y	Y	Y
			analog signals comparison
	ADCx	TIM1, 8, 20	Timer triggered by analog watchdog	Y	Y	Y	-
		TIM16	Timer input channel from RTC	Y	Y	Y	-
			events
	RTC
		LPTIMER1	Low-power timer triggered by RTC	Y	Y	Y	Y
			alarms or tampers
	All clocks sources (internal	TIM15, 16, 17	Clock source used as input channel	Y	Y	Y	-
	and external)		for RC measurement and trimming
	USB	TIM2	Timer triggered by USB SOF	Y	Y	-	-
	CSS
	CPU (hard fault)
	RAM (parity error)	TIM1, 8, 20	Timer break	Y	Y	Y	-
	Flash memory (ECC error)	TIM15, 16, 17
	COMPx
	PVD
		TIMx	External trigger	Y	Y	Y	-
	GPIO	LPTIMER1	External trigger	Y	Y	Y	-
		ADCx	Conversion external trigger	Y	Y	Y	-
		DACx

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3.13Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

•Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler

•Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register.

•Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

•System clock source: three different sources can deliver SYSCLK system clock:

–4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock to system PLL. The HSE can also be configured in bypass mode for an external clock.

–16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to system PLL.

–System PLL with maximum output frequency of 170 MHz. It can be fed with HSE or HSI16 clocks.

•RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can be used to drive the USB or the RNG peripherals.

•Auxiliary clock source: two ultra-low-power clock sources for the real-time clock (RTC):

–32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes. The LSE can also be configured in bypass mode for using an external clock.

–32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to clock an independent watchdog.

•Peripheral clock sources: several peripherals (I2S, USART, I2C, LPTimer, ADC, SAI, RNG) have their own clock independent of the system clock.

•Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected and generate an interrupt.

•Clock-out capability:

–MCO: microcontroller clock output: it outputs one of the internal clocks for external use by the application

–LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.

Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 170 MHz.

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3.14General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

3.15Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features implementation.

Direct memory access (DMA) is used in order to provide a high-speed data transfer between peripherals and memory as well as from memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps the CPU resources free for other operations.

The two DMA controllers have 16 channels in total, each one dedicated to manage memory access requests from one or more peripherals. Each controller has an arbiter for handling the priority between DMA requests.

The DMA supports:

•16 independently configurable channels (requests)

–Each channel is connected to a dedicated hardware DMA request, a software trigger is also supported on each channel. This configuration is done by software.

•Priorities between requests from channels of one DMA are both software programmable (4 levels: very high, high, medium, low) or hardware programmable in case of equality (request 1 has priority over request 2, etc.)

•Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.

•Support for circular buffer management

•3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed together in a single interrupt request for each channel

•Memory-to-memory transfer

•Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers

•Access to Flash, SRAM, APB and AHB peripherals as source and destination

•Programmable number of data to be transferred: up to 65536.

Table 4. DMA implementation

DMA features	DMA1	DMA2
Number of regular channels	8	8

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3.16DMA request router (DMAMux)

When a peripheral indicates a request for DMA transfer by setting its DMA request line, the DMA request is pending until it is served and the corresponding DMA request line is reset. The DMA request router allows to route the DMA control lines between the peripherals and the DMA controllers of the product.

An embedded multi-channel DMA request generator can be considered as one of such peripherals. The routing function is ensured by a multi-channel DMA request line multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or synchronously with events on synchronization inputs.

For simplicity, the functional description is limited to DMA request lines. The other DMA control lines are not shown in figures or described in the text. The DMA request generator produces DMA requests following events on DMA request trigger inputs.

3.17Interrupts and events

3.17.1Nested vectored interrupt controller (NVIC)

The STM32G4A1xE devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and to handle up to 71 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4.

The NVIC benefits are the following:

•Closely coupled NVIC gives low latency interrupt processing

•Interrupt entry vector table address passed directly to the core

•Allows early processing of interrupts

•Processing of late arriving higher priority interrupts

•Support for tail chaining

•Processor state automatically saved

•Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

3.17.2Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 40 edge detector lines used to generate interrupt/event requests and to wake-up the system from the Stop mode. Each external line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently.

A pending register maintains the status of the interrupt requests. The internal lines are connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can be connected to the 16 external interrupt lines.

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3.18Analog-to-digital converter (ADC)

The device embeds three successive approximation analog-to-digital converters with the following features:

•12-bit native resolution, with built-in calibration

•4 Msps maximum conversion rate with full resolution

–Down to 41.67 ns sampling time

–Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit resolution)

•One external reference pin is available on all packages, allowing the input voltage range to be independent from the power supply

•Single-ended and differential mode inputs

•Low-power design

–Capable of low-current operation at low conversion rate (consumption decreases linearly with speed)

–Dual clock domain architecture: ADC speed independent from CPU frequency

•Highly versatile digital interface

–Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions

–Each ADC support multiple trigger inputs for synchronization with on-chip timers and external signals

–Results stored into a data register or in RAM with DMA controller support

–Data pre-processing: left/right alignment and per channel offset compensation

–Built-in oversampling unit for enhanced SNR

–Channel-wise programmable sampling time

–Analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers

–Hardware assistant to prepare the context of the injected channels to allow fast context switching

–Flexible sample time control

–Hardware gain and offset compensation

3.18.1Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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	Table 5. Temperature sensor calibration values
	Calibration value name	Description	Memory address
		TS ADC raw data acquired at a
	TS_CAL1	temperature of 30 °C (± 5 °C),	0x1FFF 75A8 - 0x1FFF 75A9
		VDDA = VREF+ = 3.0 V (± 10 mV)
		TS ADC raw data acquired at a
	TS_CAL2	temperature of 110 °C (± 5 °C),	0x1FFF 75CA - 0x1FFF 75CB
		VDDA = VREF+ = 3.0 V (± 10 mV)

3.18.2Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN18 and ADC3_IN18 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 6. Internal voltage reference calibration values

Calibration value name	Description	Memory address
	Raw data acquired at a
VREFINT	temperature of 30 °C (± 5 °C),	0x1FFF 75AA - 0x1FFF 75AB
	VDDA = VREF+ = 3.0 V (± 10 mV)

3.18.3VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using

the internal ADC1_IN17 channel. As the VBAT voltage may be higher than the VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by

3. As a consequence, the converted digital value is one third of the VBAT voltage.

3.18.4Operational amplifier internal output (OPAMPxINT):

The OPAMPx (x = 1,2,3,6) output OPAMPxINT can be sampled using an ADCx (x = 1,2,3) internal input channel. In this case, the I/O on which the OPAMPx output is mapped can be used as GPIO.

3.19Digital to analog converter (DAC)

Four 12 bit DAC channels (2 external buffered and 2 internal unbuffered) can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.

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