• Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator) allowing 0-wait-state execution
from Flash memory, frequency up to 170 MHz
with 213 DMIPS, MPU, DSP instructions
• Operating conditions:
–V
• Mathematical hardware accelerators
– CORDIC for trigonometric functions
– FMAC: filter mathematical accelerator
• Memories
– 512 Kbytes of Flash memory with ECC
– 96 Kbytes of SRAM, with hardware parity
– Routine booster: 16 Kbytes of SRAM on
– Quad-SPI memory interface
• Reset and supply management
– Power-on/power-down reset
The ART accelerator is a memory accelerator that is optimized for the STM32 industry-
standard Arm
the Arm
processor to wait for the Flash memory at higher frequencies.
®
®
Cortex®-M4 processors. It balances the inherent performance advantage of
Cortex®-M4 over Flash memory technologies, which normally requires the
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 8 protected areas, which can be
divided in up into 8 subareas each. The protection area sizes range between 32 bytes and
the whole 4 gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.4 Embedded Flash memory
The STM32G4A1xE devices feature 512 kbytes of embedded Flash memory which is
available for storing programs and data.
Flexible protections can be configured thanks to the option bytes:
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Functional overviewSTM32G4A1xE
• Readout protection (RDP) to protect the whole memory. Three levels of protection are
available:
– Level 0: no readout protection
– Level 1: memory readout protection; the Flash memory cannot be read from or written
to if either the debug features are connected or the boot in RAM or bootloader are
selected
– Level 2: chip readout protection; the debug features (Cortex-M4 JTAG and serial
wire), the boot in RAM and the bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•Write protection (WRP): the protected area is protected against erasing and
programming.
•Proprietary code readout protection (PCROP): a part of the Flash memory can be
protected against read and write from third parties. The protected area is execute-only
and it can only be reached by the STM32 CPU as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited. An
additional option bit (PCROP_RDP) allows to select if the PCROP area is erased or not
when the RDP protection is changed from Level 1 to Level 0.
•Securable memory area: a part of Flash memory can be configured by option bytes to
be securable. After reset this securable memory area is not secured and it behaves like
the remainder of main Flash memory (execute, read, write access). When secured, any
access to this securable memory area generates corresponding read/write error.
Purpose of the Securable memory area is to protect sensitive code and data (secure
keys storage) which can be executed only once at boot, and never again unless a new
reset occurs.
The Flash memory embeds the error correction code (ECC) feature supporting:
•Single error detection and correction
•Double error detection
•The address of the ECC fail can be read in the ECC register
•1 Kbyte (128 double word) OTP (one-time programmable) bytes for user data. The
OTP area is available in Bank 1 only. The OTP data cannot be erased and can be
written only once.
3.5 Embedded SRAM
STM32G4A1xE devices feature 112 Kbytes of embedded SRAM. This SRAM is split into
three blocks:
•80 Kbytes mapped at address 0x2000 0000 (SRAM1). The CM4 can access the
SRAM1 through the System Bus (or through the I-Code/D-Code buses when boot from
SRAM1 is selected or when physical remap is selected by SYSCFG_MEMRMP
register). The first 32 Kbytes of SRAM1 support hardware parity check.
•16 Kbytes mapped at address 0x2001 4000 (SRAM2). The CM4 can access the
SRAM2 through the System bus. SRAM2 can be kept in stop and standby modes.
•16 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is accessed by the CPU
through I-Code/D-Code bus for maximum performance.
It is also aliased at 0x2001 8000 address to be accessed by all masters (CPU, DMA1,
DMA2) through SBUS contiguously to SRAM1 and SRAM2.The CCM SRAM supports
hardware parity check and can be write-protected with 1-Kbyte granularity.
•The memory can be accessed in read/write at max CPU clock speed with 0 wait states.
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STM32G4A1xEFunctional overview
MS52814V1
Cortex
®
-M4
with FPU
DMA1DMA2
AHB2
peripherals
AHB1
peripherals
CCM
SRAM
SRAM1
FLASH
512 KB
ACCEL
S-bus
D-bus
ICode
DCode
I-bus
BusMatrix-S
SRAM2
QUADSPI
3.6 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, QUADSPI, AHB and APB peripherals). It also ensures a seamless
and efficient operation even when several high-speed peripherals work simultaneously.
Figure 2. Multi-AHB bus matrix
3.7 Boot modes
At startup, a BOOT0 pin (or nBOOT0 option bit)and an nBOOT1 option bit are used to select
one of three boot options:
•Boot from user Flash
•Boot from system memory
•Boot from embedded SRAM
The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit
depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed.
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade).
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Functional overviewSTM32G4A1xE
3.8 CORDIC
The CORDIC provides hardware acceleration of certain mathematical functions, notably
trigonometric, commonly used in motor control, metering, signal processing and many other
applications.
It speeds up the calculation of these functions compared to a software implementation,
allowing a lower operating frequency, or freeing up processor cycles in order to perform
other tasks.
•Supports 16-bit and 32-bit fixed point input and output formats
•Low latency AHB slave interface
•Results can be read as soon as ready without polling or interrupt
•DMA read and write channels
3.9 Filter mathematical accelerator (FMAC)
The filter mathematical accelerator unit performs arithmetic operations on vectors. It
comprises a multiplier/accumulator (MAC) unit, together with address generation logic,
which allows it to index vector elements held in local memory.
The unit includes support for circular buffers on input and output, which allows digital filters
to be implemented. Both finite and infinite impulse response filters can be realized.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
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STM32G4A1xEFunctional overview
FMAC features
•16 x 16-bit multiplier
•24+2-bit accumulator with addition and subtraction
•16-bit input and output data
•256 x 16-bit local memory
•Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
•Input and output sample buffers can be circular
•Buffer “watermark” feature reduces overhead in interrupt mode
•Filter functions: FIR, IIR (direct form 1)
•AHB slave interface
•DMA read and write data channels
3.10 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator with polynomial value and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the Flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, which
can be ulteriorly compared with a reference signature generated at link-time and which can
be stored at a given memory location.
3.11 Power supply management
3.11.1 Power supply schemes
The STM32G4A1xE devices require a 1.71 V to 3.6 V V
Several independent supplies, can be provided for specific peripherals:
•V
•V
•V
= 1.71 V to 3.6 V
DD
V
is the external power supply for the I/Os, the internal regulator and the system
DD
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
= 1.62 V to 3.6 V (see Section 5: Electrical characteristics for the minimum V
DDA
voltage required for ADC, DAC, COMP, OPAMP, VREFBUF operation).
V
is the external analog power supply for A/D converters, D/A converters, voltage
DDA
reference buffer, operational amplifiers and comparators. The V
independent from the V
voltage and should preferably be connected to VDD when
DD
these peripherals are not used.
= 1.55 V to 3.6 V
BAT
V
is the power supply for RTC, external clock 32 kHz oscillator and backup registers
BAT
(through power switch) when V
is not present.
DD
operating voltage supply.
DD
voltage level is
DDA
DDA
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Functional overviewSTM32G4A1xE
•VREF-, VREF+
V
is the input reference voltage for ADCs and DACs. It is also the output of the
REF+
internal voltage reference buffer when enabled.
When V
When V
DDA
DDA
< 2 V V
2 V V
must be equal to V
REF+
must be between 2 V and V
REF+
DDA
.
.
DDA
The internal voltage reference buffer supports three output voltages, which are
configured with VRS bits in the VREFBUF_CSR register:
–V
–V
–V
V
REF-
= 2.048 V
REF+
= 2.5 V
REF+
= 2.9 V
REF+
is double bonded with V
SSA
.
3.11.2 Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after poweron and during power down. The device remains in reset mode when the monitored supply
voltage V
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the V
interrupt can be generated when V
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
is below a specified threshold, without the need for an external reset circuit.
DD
power supply and compares it to the VPVD threshold. An
DD
drops below the VPVD threshold and/or when VDD is
DD
In addition, the device embeds a peripheral voltage monitor which compares the
independent supply voltages V
peripheral is in its functional supply range.
3.11.3 Voltage regulator
Two embedded linear voltage regulators, main regulator (MR) and low-power regulator
(LPR), supply most of digital circuitry in the device. The MR is used in Run and Sleep
modes. The LPR is used in Low-power run, Low-power sleep and Stop modes. In Standby
and Shutdown modes, both regulators are powered down and their outputs set in highimpedance state, such as to bring their current consumption close to zero.
The device supports dynamic voltage scaling to optimize its power consumption in Run
mode. the voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator (MR) operates in the following ranges:
•Range 1 boost mode with the CPU running at up to 170 MHz.
•Range 1 normal mode with CPU running at up to 150 MHz.
•Range 2 with a maximum CPU frequency of 26 MHz.
, with a fixed threshold in order to ensure that the
DDA
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STM32G4A1xEFunctional overview
3.11.4 Low-power modes
By default, the microcontroller is in Run mode after system or power Reset. It is up to the
user to select one of the low-power modes described below:
•Sleep mode: In Sleep mode, only the CPU is stopped. All peripherals continue to
operate and can wake up the CPU when an interrupt/event occurs.
•Low-power run mode: This mode is achieved with VCORE supplied by the low-power
regulator to minimize the regulator's operating current. The code can be executed from
SRAM or from Flash, and the CPU frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16.
•Stop mode: In Stop mode, the device achieves the lowest power consumption while
retaining the SRAM and register contents. All clocks in the VCORE domain are
stopped. The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are
disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC). Some peripherals with wakeup capability can enable
the HSI16 RC during Stop mode, so as to get clock for processing the wakeup event.
•Standby mode: The Standby mode is used to achieve the lowest power consumption
with brown-out reset, BOR. The internal regulator is switched off to power down the
VCORE domain. The PLL, as well as the HSI16 RC oscillator and the HSE crystal
oscillator are also powered down. The RTC can remain active (Standby mode with
RTC, Standby mode without RTC). The BOR always remains active in Standby mode.
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode. Upon entering Standby mode, SRAM
and register contents are lost except for registers in the RTC domain and standby
circuitry. The device exits Standby mode upon external reset event (NRST pin), IWDG
reset event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC
event (alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on
LSE (CSS on LSE).
•Shutdown mode: The Shutdown mode allows to achieve the lowest power
consumption. The internal regulator is switched off to power down the VCORE domain.
The PLL, as well as the HSI16 and LSI RC-oscillators and HSE crystal oscillator are
also powered down. The RTC can remain active (Shutdown mode with RTC, Shutdown
mode without RTC). The BOR is not available in Shutdown mode. No power voltage
monitoring is possible in this mode. Therefore, switching to RTC domain is not
supported. SRAM and register contents are lost except for registers in the RTC
domain. The device exits Shutdown mode upon external reset event (NRST pin),
IWDG reset event, wakeup event (WKUP pin, configurable rising or falling edge) or
RTC event (alarm, periodic wakeup, timestamp, tamper).
3.11.5 Reset mode
In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.11.6 V
operation
BAT
The V
pin allows to power the device V
BAT
supercapacitor, or from V
supercapacitor is present. The V
registers. Three anti-tamper detection pins are available in V
domain from an external battery, an external
when there is no external battery and when an external
DD
BAT
DS13268 Rev 223/200
BAT
pin supplies the RTC with LSE and the backup
mode.
BAT
45
Functional overviewSTM32G4A1xE
The V
operation is automatically activated when VDD is not present. An internal V
BAT
battery charging circuit is embedded and can be activated when V
Note:When the microcontroller is supplied from V
alarm/events exit the microcontroller from the V
is present.
DD
, neither external interrupts nor RTC
BAT
operation.
BAT
BAT
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STM32G4A1xEFunctional overview
3.12 Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
Timer input channel, trigger, break
from analog signals comparison
Low-power timer triggered by
analog signals comparison
Timer input channel from RTC
events
Low-power timer triggered by RTC
alarms or tampers
Clock source used as input channel
for RC measurement and trimming
Timer breakYYY-
Interconnect action
Run
Sleep
Low-power run
YYY -
YYYY
YYY -
YYYY
YYY -
Stop
GPIO
LPTIMER1External triggerYYY-
ADCx
DACx
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Conversion external triggerYYY-
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Functional overviewSTM32G4A1xE
3.13 Clocks and startup
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
•Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•System clock source: three different sources can deliver SYSCLK system clock:
–4 - 48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
It can supply clock to system PLL. The HSE can also be configured in bypass
mode for an external clock.
–16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can
supply clock to system PLL.
–System PLL with maximum output frequency of 170 MHz. It can be fed with HSE
or HSI16 clocks.
•RC48 with clock recovery system (HSI48): internal HSIRC48 MHz clock source can
be used to drive the USB or the RNG peripherals.
•Auxiliary clock source: two ultra-low-power clock sources for the real-time clock
(RTC):
–32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
–32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
RNG) have their own clock independent of the system clock.
•Clock security system (CSS): in the event of HSE clock failure, the system clock is
automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE
clock failure can also be detected and generate an interrupt.
•Clock-out capability:
–MCO: microcontroller clock output: it outputs one of the internal clocks for external
use by the application
–LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes.
Several prescalers allow to configure the AHB frequency, the High-speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 170 MHz.
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STM32G4A1xEFunctional overview
3.14 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.15 Direct memory access controller (DMA)
The device embeds 2 DMAs. Refer to Table 4: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide a high-speed data transfer
between peripherals and memory as well as from memory to memory. Data can be quickly
moved by DMA without any CPU actions. This keeps the CPU resources free for other
operations.
The two DMA controllers have 16 channels in total, each one dedicated to manage memory
access requests from one or more peripherals. Each controller has an arbiter for handling
the priority between DMA requests.
–Each channel is connected to a dedicated hardware DMA request, a software
trigger is also supported on each channel. This configuration is done by software.
•Priorities between requests from channels of one DMA are both software
programmable (4 levels: very high, high, medium, low) or hardware programmable in
case of equality (request 1 has priority over request 2, etc.)
•Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•Support for circular buffer management
•3 event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically ORed together in a single interrupt request for each channel
•Memory-to-memory transfer
•Peripheral-to-memory, memory-to-peripheral, and peripheral-to-peripheral transfers
•Access to Flash, SRAM, APB and AHB peripherals as source and destination
•Programmable number of data to be transferred: up to 65536.
DMA featuresDMA1DMA2
Number of regular channels88
Table 4. DMA implementation
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Functional overviewSTM32G4A1xE
3.16 DMA request router (DMAMux)
When a peripheral indicates a request for DMA transfer by setting its DMA request line, the
DMA request is pending until it is served and the corresponding DMA request line is reset.
The DMA request router allows to route the DMA control lines between the peripherals and
the DMA controllers of the product.
An embedded multi-channel DMA request generator can be considered as one of such
peripherals. The routing function is ensured by a multi-channel DMA request line
multiplexer. Each channel selects a unique set of DMA control lines, unconditionally or
synchronously with events on synchronization inputs.
For simplicity, the functional description is limited to DMA request lines. The other DMA
control lines are not shown in figures or described in the text. The DMA request generator
produces DMA requests following events on DMA request trigger inputs.
The STM32G4A1xE devices embed a nested vectored interrupt controller which is able to
manage 16 priority levels, and to handle up to 71 maskable interrupt channels plus the 16
interrupt lines of the Cortex
•Interrupt entry vector table address passed directly to the core
•Allows early processing of interrupts
•Processing of late arriving higher priority interrupts
•Support for tail chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.17.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 40 edge detector lines used to generate
interrupt/event requests and to wake-up the system from the Stop mode. Each external line
can be independently configured to select the trigger event (rising edge, falling edge, both)
and can be masked independently.
A pending register maintains the status of the interrupt requests. The internal lines are
connected to peripherals with wakeup from Stop mode capability. The EXTI can detect an
external line with a pulse width shorter than the internal clock period. Up to 86 GPIOs can
be connected to the 16 external interrupt lines.
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STM32G4A1xEFunctional overview
3.18 Analog-to-digital converter (ADC)
The device embeds three successive approximation analog-to-digital converters with the
following features:
•12-bit native resolution, with built-in calibration
•4 Msps maximum conversion rate with full resolution
–Down to 41.67 ns sampling time
–Increased conversion rate for lower resolution (up to 6.66 Msps for 6-bit
resolution)
•One external reference pin is available on all packages, allowing the input voltage
range to be independent from the power supply
•Single-ended and differential mode inputs
•Low-power design
–Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
–Dual clock domain architecture: ADC speed independent from CPU frequency
•Highly versatile digital interface
–Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
–Each ADC support multiple trigger inputs for synchronization with on-chip timers
and external signals
–Results stored into a data register or in RAM with DMA controller support
–Data pre-processing: left/right alignment and per channel offset compensation
–Built-in oversampling unit for enhanced SNR
–Channel-wise programmable sampling time
–Analog watchdog for automatic voltage monitoring, generating interrupts and
trigger for selected timers
–Hardware assistant to prepare the context of the injected channels to allow fast
context switching
–Flexible sample time control
–Hardware gain and offset compensation
3.18.1 Temperature sensor
The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
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Functional overviewSTM32G4A1xE
Calibration value nameDescriptionMemory address
TS_CAL1
TS_CAL2
Table 5. Temperature sensor calibration values
TS ADC raw data acquired at a
temperature of 30 °C (± 5 °C),
V
DDA
TS ADC raw data acquired at a
temperature of 110 °C (± 5 °C),
V
DDA
3.18.2 Internal voltage reference (V
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and the comparators. The VREFINT is internally connected to the ADC1_IN18 and
ADC3_IN18 input channel. The precise voltage of VREFINT is individually measured for
each part by ST during production test and stored in the system memory area. It is
accessible in read-only mode.
Calibration value nameDescriptionMemory address
Table 6. Internal voltage reference calibration values
Raw data acquired at a
VREFINT
temperature of 30 °C (± 5 °C),
V
DDA
= V
REF+
= V
REF+
REFINT
= V
REF+
0x1FFF 75A8 - 0x1FFF 75A9
= 3.0 V (± 10 mV)
0x1FFF 75CA - 0x1FFF 75CB
= 3.0 V (± 10 mV)
)
0x1FFF 75AA - 0x1FFF 75AB
= 3.0 V (± 10 mV)
3.18.3 V
battery voltage monitoring
BAT
This embedded hardware enables the application to measure the V
the internal ADC1_IN17 channel. As the V
voltage may be higher than the V
BAT
thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by
3. As a consequence, the converted digital value is one third of the V
The OPAMPx (x = 1,2,3,6) output OPAMPxINT can be sampled using an ADCx (x = 1,2,3)
internal input channel. In this case, the I/O on which the OPAMPx output is mapped can be
used as GPIO.
3.19 Digital to analog converter (DAC)
Four 12 bit DAC channels (2 external buffered and 2 internal unbuffered) can be used to
convert digital signals into analog voltage signal outputs. The chosen design structure is
composed of integrated resistor strings and an amplifier in inverting configuration.
battery voltage using
BAT
DDA
voltage.
BAT
, and
30/200DS13268 Rev 2
STM32G4A1xEFunctional overview
MSv40197V1
VREFBUF
Low frequency
cut-off capacitor
DAC, ADC
Bandgap+
V
DDA
-
100 nF
VREF+
This digital interface supports the following features:
•Up to two DAC output channels
•8-bit or 12-bit output mode
•Buffer offset calibration (factory and user trimming)
•Left or right data alignment in 12-bit mode
•Synchronized update capability
•Noise-wave generation
•Triangular-wave generation
•Saw tooth wave generation
•Dual DAC channel independent or simultaneous conversions
•DMA capability for each channel
•External triggers for conversion
•Sample and hold low-power mode, with internal or external capacitor
•Up to 1 Msps for external output and 15 Msps for internal output
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.20 Voltage reference buffer (V
The STM32G4A1xE devices embed a voltage reference buffer which can be used as
voltage reference for ADC, DACs and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports three voltages:
•2.048 V
•2.5 V
•2.9 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with V
internal voltage reference buffer is not available.
Figure 3. Voltage reference buffer
REFBUF
DDA
)
on some packages. In these packages the
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Functional overviewSTM32G4A1xE
3.21 Comparators (COMP)
The STM32G4A1xE devices embed four rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis.
The reference voltage can be one of the following:
•External I/O
•DAC output channels
•Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers.
3.22 Operational amplifier (OPAMP)
The STM32G4A1xE devices embed four operational amplifiers (OPAMP1, OPAMP2,
OPAMP3, OPAMP6) with external or internal follower routing and PGA capability.
The operational amplifier features:
•13 MHz bandwidth
•Rail-to-rail input/output
•PGA with a non-inverting gain ranging of 2, 4, 8, 16, 32 or 64 or inverting gain ranging
of -1, -3, -7, -15, -31 or -63
3.23 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.24 Advanced encryption standard hardware accelerator (AES)
The STM32G4A1xE devices embed an AES hardware accelerator that can be used both to
encipher and to decipher data using an AES algorithm.
32/200DS13268 Rev 2
STM32G4A1xEFunctional overview
The AES peripheral supports:
•Encryption/decryption using AES Rijndael block cipher algorithm
•NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
•128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x
•Register access supporting 32-bit data width only
•One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected, GCM mode or
CMAC mode
•Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data
•Suspend a message if another message with a higher priority needs to be processed.
3.25 Timers and watchdogs
The STM32G4A1xE devices include three advanced motor control timers, up to six generalpurpose timers, two basic timers, one low-power timer, two watchdog timers and a SysTick
timer. The table below compares the features of the advanced motor control, general
purpose and basic timers.
Timer typeTimer
Advanced
motor
control
General-
purpose
General-
purpose
General-
purpose
TIM1, TIM8,
TIM20
TIM232-bit
TIM3, TIM416-bit
TIM1516-bitUp
Table 7. Timer feature comparison
Counter
resolution
16-bit
Counter
type
Up,
down,
Up/down
Up,
down,
Up/down
Up,
down,
Up/down
Prescaler
factor
Any integer
between 1 and
65536
Any integer
between 1 and
65536
Any integer
between 1 and
65536
Any integer
between 1 and
65536
DMA
request
generation
Yes44
Yes4No
Yes4No
Yes21
Capture/
compare
channels
Complementary
outputs
DS13268 Rev 233/200
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Functional overviewSTM32G4A1xE
Table 7. Timer feature comparison (continued)
Timer typeTimer
General-
purpose
BasicTIM6, TIM716-bitUp
TIM16, TIM1716-bitUp
Counter
resolution
Counter
type
Prescaler
factor
Any integer
between 1 and
65536
Any integer
between 1 and
65536
DMA
request
generation
Yes11
Yes0No
3.25.1 Advanced motor control timer (TIM1, TIM8, TIM20)
The advanced motor control timers can each be seen as a four-phase
PWM multiplexed on 8 channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as complete general-purpose
timers.
The 4 independent channels can be used for:
•Input capture
•Output compare
•PWM generation (edge or center-aligned modes) with full modulation capability
(0-100%)
•One-pulse mode output
Capture/
compare
channels
Complementary
outputs
In debug mode, the advanced motor control timer counter can be frozen and the PWM
outputs disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in
Section 3.25.2) using the same architecture, so the advanced motor control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
There are up to six synchronizable general-purpose timers embedded in the
STM32G4A1xE devices (see Tab l e 7 for differences). Each general-purpose timer can be
used to generate PWM outputs, or act as a simple time base.
•TIM2, TIM3, and TIM4
They are full-featured general-purpose timers:
–TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
–TIM3 and TIM4 have 16-bit auto-reload up/downcounter and 16-bit prescaler.
These timers feature 4 independent channels for input capture/output compare, PWM
or one-pulse mode output. They can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•TIM15, 16 and 17
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–TIM15 has 2 channels and 1 complementary channel
–TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.25.3 Basic timers (TIM6 and TIM7)
The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
DS13268 Rev 235/200
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Functional overviewSTM32G4A1xE
3.25.4 Low-power timer (LPTIM1)
The devices embed a low-power timer. This timer has an independent clock and are running
in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the system
from Stop mode.
LPTIM1 is active in Stop mode.
This low-power timer supports the following features:
•16-bit up counter with 16-bit autoreload register
•16-bit compare register
•Configurable output: pulse, PWM
•Continuous/ one shot mode
•Selectable software/hardware input trigger
•Selectable clock source
–Internal clock sources: LSE, LSI, HSI16 or APB clock
–External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
•Programmable digital glitch filter
•Encoder mode
3.25.5 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.25.6 System window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.25.7 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
•A 24-bit down counter
•Autoreload capability
•Maskable system interrupt generation when the counter reaches 0.
•Programmable clock source
36/200DS13268 Rev 2
STM32G4A1xEFunctional overview
3.26 Real-time clock (RTC) and backup registers
The RTC supports the following features:
•Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•Two programmable alarms.
•On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
V
mode.
BAT
•17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC is supplied through a switch that takes power either from the V
present or from the VBAT pin.
The RTC clock sources can be:
•A 32.768 kHz external crystal (LSE)
•An external resonator or oscillator (LSE)
•The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
•The high-speed external clock (HSE) divided by 32.
The RTC is functional in V
mode and in all low-power modes when it is clocked by the
BAT
LSE. When clocked by the LSI, the RTC is not functional in V
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp) can generate an interrupt and wakeup
the device from the low-power modes.
3.27 Tamper and backup registers (TAMP)
•32 32-bit backup registers, retained in all low-power modes and also in V
They can be used to store sensitive data as their content is protected by an tamper
detection circuit. They are not reset by a system or power reset, or when the device
wakes up from Standby or Shutdown mode.
•Up to three tamper pins for external tamper detection events. The external tamper pins
can be configured for edge detection, edge and level, level detection with filtering.
•Five internal tampers events.
•Any tamper detection can generate a RTC timestamp event.
•Any tamper detection erases the backup registers.
•Any tamper detection can generate an interrupt and wake-up the device from all low-
power modes.
supply when
DD
mode, but is functional in
BAT
mode.
BAT
DS13268 Rev 237/200
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Functional overviewSTM32G4A1xE
3.28 Infrared transmitter
The STM32G4A1xE devices provide an infrared transmitter solution. The solution is based
on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be
sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
Figure 4. Infrared transmitter
TIM17_CH1
TIM16_CH1
IRTIM
IR_OUT
MS30474V2
38/200DS13268 Rev 2
STM32G4A1xEFunctional overview
3.29 Inter-integrated circuit interface (I2C)
The device embeds three I2Cs. Refer to Table 8: I2C implementation for the features
implementation.
2
The I
C bus interface handles communications between the microcontroller and the serial
2
I
C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
2
•I
C-bus specification and user manual rev. 5 compatibility:
–Slave and master modes, multimaster capability
–Standard-mode (Sm), with a bitrate up to 100 kbit/s
–Fast-mode (Fm), with a bitrate up to 400 kbit/s
–Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–Programmable setup and hold times
–Optional clock stretching
•System management bus (SMBus) specification rev 2.0 compatibility:
–Hardware PEC (packet error checking) generation and verification with ACK
control
–Address resolution protocol (ARP) support
–SMBus alert
•Power system management protocol (PMBus
•Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•Wakeup from Stop mode on address match
•Programmable analog and digital noise filters
•1-byte buffer with DMA capability
Table 8. I2C implementation
I2C features
(1)
TM
) specification rev 1.1 compatibility
I2C1I2C2I2C3
Standard-mode (up to 100 kbit/s)XXX
Fast-mode (up to 400 kbit/s)XXX
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)XXX
The STM32G4A1xE devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver
transmitters (UART4, UART5).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN master/slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 driver enable.
The USART1, USART2 and USART3 also provide a Smartcard mode (ISO 7816 compliant)
and an SPI-like communication capability.
The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3,4) to wake up the MCU from Stop mode. The wakeup from Stop mode can be done
on:
•Start bit detection
•Any received data frame
•A specific programmed data frame
•Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
All USART interfaces can be served by the DMA controller.
The STM32G4A1xE devices embed one Low-Power UART. The LPUART supports
asynchronous serial communication with minimum power consumption. It supports halfduplex single-wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default. It has a clock domain independent
from the CPU clock, and can wakeup the system from Stop mode. The wake up from Stop
mode can be done on:
•Start bit detection
•Any received data frame
•A specific programmed data frame
•Some specific TXFIFO/RXFIFO status interrupts when FIFO mode is enabled
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
The LPUART interface can be served by the DMA controller.
3.32 Serial peripheral interface (SPI)
Three SPI interfaces allow communication up to 75 Mbits/s in master and up to 41 Mbits/s in
slave, half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and hardware CRC calculation.
Two standard I
standards can operate as master or slave at half-duplex communication modes. They can
be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and
synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can
be set by 8-bit programmable linear prescaler. When operating in master mode it can output
a clock for an external audio component at 256 times the sampling frequency.
All SPI interfaces can be served by the DMA controller.
2
S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio
DS13268 Rev 241/200
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Functional overviewSTM32G4A1xE
3.33 Serial audio interfaces (SAI)
The device embeds 1 SAI. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
3.33.1 SAI peripheral supports
•Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
•8-word integrated FIFOs for each audio sub-block.
•Synchronous or asynchronous mode between the audio sub-blocks.
•Master or slave configuration independent for both audio sub-blocks.
•Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
•Error flags with associated interrupts if enabled respectively.
–Overrun and underrun detection.
–Anticipated frame synchronization signal detection in slave mode.
–Late frame synchronization signal detection in slave mode.
–Codec not ready for the AC’97 mode in reception.
•Interruption sources when enabled:
–Errors.
–FIFO requests.
•DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
Table 10. SAI implementation for the features implementation
SAI featuresSupport
(1)
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97X
Mute modeX
Stereo/Mono audio frame capabilityX
16 slotsX
42/200DS13268 Rev 2
STM32G4A1xEFunctional overview
Table 10. SAI implementation for the features implementation (continued)
SAI featuresSupport
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bitX
FIFO sizeX (8 word)
SPDIFX
1. X: supported.
(1)
3.34 Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules and message
RAM memory.
The two CAN modules (FDCAN1, and FDCAN2) are compliant with ISO 11898-1 (CAN
protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
The STM32G4A1xE devices embed a full-speed USB device peripheral compliant with the
USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 Kbyte and suspend/resume
support. It requires a precise 48 MHz clock which can be generated from the internal main
PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator
in automatic trimming mode. The synchronization for this oscillator can be taken from the
USB data stream itself (SOF signalization) which allows crystal less operation.
3.36 USB Type-C™ / USB Power Delivery controller (UCPD)
The device embeds one controller (UCPD) compliant with USB Type-C Rev. 1.2 and USB
Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB Power Delivery
requirements, featuring:
•USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
•“Dead battery” support
•USB Power Delivery message transmission and reception
•FRS (fast role swap) support
DS13268 Rev 243/200
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Functional overviewSTM32G4A1xE
The digital controller handles notably:
•USB Type-C level detection with de-bounce, generating interrupts
•FRS detection, generating an interrupt
•Byte-level interface for USB Power Delivery payload, generating interrupts (DMA
compatible)
•USB Power Delivery timing dividers (including a clock pre-scaler)
•CRC generation/checking
•4b5b encode/decode
•Ordered sets (with a programmable ordered set mask at receive)
•Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB Power Delivery messages and FRS signaling.
3.37 Clock recovery system (CRS)
The devices embed a special block which allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, which could be either
derived from USB SOF signalization, from LSE oscillator, from an external signal on
CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.38 Quad SPI memory interface (QUADSPI)
The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
•Indirect mode: all the operations are performed using the QUADSPI registers
•Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
•Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory.
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
quad SPI flash memories are accessed simultaneously.
44/200DS13268 Rev 2
STM32G4A1xEFunctional overview
The Quad SPI interface supports:
•Indirect mode: all the operations are performed using the QUADSPI registers
•Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
•Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory
•Three functional modes: indirect, status-polling, and memory-mapped
•SDR and DDR support
•Fully programmable opcode for both indirect and memory mapped mode
•Fully programmable frame format for both indirect and memory mapped mode
–Each of the 5 following phases can be configured independently (enable, length,
single/dual/quad communication)
–Instruction phase
–Address phase
–Alternate bytes phase
–Dummy cycles phase
–Data phase
•Integrated FIFO for reception and transmission
•8, 16, and 32-bit data accesses are allowed
•DMA channel for indirect mode operations
•Programmable masking for external flash flag management
•Timeout management
•Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
3.39 Development support
3.39.1 Serial wire JTAG debug port (SWJ-DP)
The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.39.2 Embedded trace macrocell™
The Arm embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32G4A1xE devices through a small number of ETM pins to an external hardware trace
port analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded trace macrocell operates with third party debugger software tools.
DS13268 Rev 245/200
45
Pinouts and pin descriptionSTM32G4A1xE
MSv47174V1
UFQFPN32
1
2
3
4
5
6
7
8
VDD
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
24
23
22
21
20
19
18
17
32 31
PB0
VSSA
VDD
PA10
PA14
VDDA
VSS
PA11
PA8
PA9
PA12
PA13
VSS
PB8-BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
30 29 28 27 26 25
9 10 111213141516
Exposed pad
4 Pinouts and pin description
4.1 UFQFPN32 pinout description
Figure 5. STM32G4A1xE UFQFPN32 pinout
1. The above figure shows the package top view.
46/200DS13268 Rev 2
STM32G4A1xEPinouts and pin description
MSv47172V1
UFQFPN48
1
2
3
4
5
6
7
8
9
10
11
12
VBAT
PC13
PC14-OSC32_IN
PC15-OSC32_OUT
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PA0
PA1
PA2
PA3
PA4
36
35
34
33
32
31
30
29
28
27
26
25
393740
38
45
43
41
484746
44
42
222421
23
16
18
20
131415
17
19
PA5
PA6
PB0
VREF+
PB11
PA7
PC4
VDDA
PB1
PB2
PB10
VDD
PA13
VDD
PA12
PA11
PA10
PA9
PA8
PC6
PB15
PB14
PB13
PB12
VDD
PB9
PB6
PB3
PA14
PB8-BOOT0
PB7
PC11
PB5
PB4
PC10
PA15
Exposed pad
VSS
MSv42659V2
LQFP48
1
2
3
4
5
6
7
8
9
10
11
12
VBAT
PC13
PC14 - OSC32_IN
PC15 - OSC32_OUT
PF0 - OSC_IN
PF1 - OSC_OUT
PG10 - NRST
PA0
PA1
PA2
PA3
PA4
36
35
34
33
32
31
30
29
28
27
26
25
393740
38
45
43
41
484746
44
42
222421
23
16
18
20
131415
17
19
PA5
PA6
PB1
VREF+
VDD
PA7
PB0
VDDA
PB2
VSSA
PB10
VSS
VDD
VSS
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
PB11
VDD
VSS
PB7
PB4
PA13
PB9
PB8-BOOT0
PB3
PB6
PB5
PA15
PA14
4.2 UFQFPN48 pinout description
Figure 6. STM32G4A1xE UFQFPN48 pinout
1. The above figure shows the package top view.
2. VSS pads are connected to the exposed pad.
4.3 LQFP48 pinout description
Figure 7. STM32G4A1xE LQFP48 pinout
1. The above figure shows the package top view.
DS13268 Rev 247/200
69
Pinouts and pin descriptionSTM32G4A1xE
MSv63424V1
VDDPC11PC12PD2PB5PB7PB9VDD
PA12VSSPC10PA15PB6
PB8-
BOOT0
VSSVBAT
PA11PA10PA13PA14PB4
PC14-
OSC32
_IN
PA9PA8PC9
PC7PC8PC6
PB15PB14
PB13VSS
VDD
PB10
PB11
PB12
PB0
VREF+
VSSA
PA7
PA4
PA2
VDDA
PB2
PC5
PA5
PB3
PA6
VSS
PA1
PF1-
OSC_OUT
PG10
-NRST
PB1
PC4
PA3
PC3
PC2
PC13PC1
VDD
PA0
PC0
PF0-
OSC_IN
PC15-
OSC32
_OUT
12345678
A
B
C
D
E
F
G
H
MSv42658V2
LQFP64
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
VBAT
PC14-OSC32_IN
PC15-OSC32_OUT
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PC0
PC1
PC2
PC3
PA0
PA1
PA2
VSS
VDD
PC13
48
46
45
44
43
42
41
40
39
38
37
36
35
34
33
47
55
5352515049
56
54
61
59
57
646362
60
58
26
2829303132
25
27
20
22
24
171819
21
23
PA3
PA4
PA7
PB0
VREF+
PA5
PA6
PB1
PB10
PC4
PC5
VSS
PB2
VSSA
VDDA
VDD
VDD
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PB11
VSS
VDD
VSS
PB7
PB4
PC11
PB9
PB8-BOOT0
PB3
PA15
PB6
PB5
PA14
PD2
PC12
PC10
PA13
4.4 WLCSP64 ballout description
Figure 8. STM32G4A1xE WLCSP64 ballout
1. The above figure shows the package top view.
4.5 LQFP64 pinout description
Figure 9. STM32G4A1xE LQFP64 pinout
48/200DS13268 Rev 2
1. The above figure shows the package top view.
STM32G4A1xEPinouts and pin description
MSv47177V3
VDDPB9PB7PB6PB3PC12PA15VDD
PC13 VSSPB8-BOOT0PB5PD2PC11VSSPA12
PC14-
OSC32_IN
VBATPC1PB4PC10PA11
PC15-
OSC32_OUT
PG10-NRSTPC2
PF0-OSC_INPC0PA1
PF1-OSC_OUTPA0
PC3
VDD
PA3
PA7
PA6
PA2
VDDA
VREF+
PB1
PB0
PC4
PB2
VSSA
PC5
PA5
PA4
PB11
VSS
PB15
PC7
PA9
PB10
PB13
PC8
PA8
PA10
PA14PA13
VDD
PB12
PB14
PC6
PC9
VSS
12345678
A
B
C
D
E
F
G
H
4.6 UFBGA64 ballout description
Figure 10. STM32G4A1xE UFBGA64 ballout
1. The above figure shows the package top view.
DS13268 Rev 249/200
69
Pinouts and pin descriptionSTM32G4A1xE
MSv60826V1
LQFP80
54
52
51
50
49
48
47
46
45
44
43
42
41
53
67
65
64
68
66
73
71
69
767574
72
70
PA7
PB0
VSSA
PE8
PC4
PC5
VREF+
PE10
PB1
PB2
PE11
VDDA
PE7
PE9
PE12
PC8
PC6
VDD
VSS
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PB11
VDD
PC7
PB7
PB6
PB3
PD0
PA15
PB5
PB4
PC12
PD2
PD1
PC11
PC10
PA14
37
PC1
PC2
PC3
PA0
PA1
PA2
VSS
9
10
11
12
13
14
15
16
17
29
3132333435
28
30
23
25
27
21
22
24
26
36PE13
PE14
55
56
57
PA9
PC9
PA8
PB8-BOOT0
PB9
VSS
VDD
77
PC13 2
VBAT
1
78
79
80
PC14-OSC32_IN3
PC15-OSC32_OUT
4
PF0-OSC_IN
5
PF1-OSC_OUT
6
PG10-NRST
7
PC0
8
20
18
19
VDD
PA4
PA5
PA6
PA3
38PE15
39PB10
40VSS
60PA12
59
PA11
58
PA10
63PA13
62VDD
61VSS
4.7 LQFP80 pinout description
Figure 11. STM32G4A1xE LQFP80 pinout
50/200DS13268 Rev 2
1. The above figure shows the package top view.
STM32G4A1xEPinouts and pin description
MSv42661V3
LQFP100
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
11
4
6
8
1
2
3
5
7
PF9
PF0-OSC_IN
PF1-OSC_OUT
PG10-NRST
PC0
PC1
PC2
PC3
PF2
PA0
PA1
PA2
VSS
VDD
PA3
PC15-OSC32_OUT
PF10
PE5
VBAT
PC14-OSC32_IN
PE2
PE3
PE4
PE6
PC13
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
67
65
72
70
68
75
74
73
71
69
91
89888786858483828180797877
76
92
90
97
95
93
100
99
98
96
94
35
37383940414243444546474849
50
34
36
29
31
33
262728
30
32
PA4
PA5
PC4
PB1
VDDA
PA6
PA7
PB2
PE8
PE11
PC5
PB0
PE9
PE12
PE15
VSSA
VREF+
PE13
PB10
VDD
PE7
PE10
PE14
VSS
PB11
PC7
VDD
VSS
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PC8
PC6
PA11
PA9
PC9
VDD
VSS
PA12
PA10
PA8
VDD
VSS
PB9
PB6
PD7
PE1
PE0
PB5
PD5
PD2
PB8-BOOT0
PB7
PD4
PD1
PC11
PB4
PB3
PD0
PC10
PA14
PD6
PD3
PC12
PA15
PA13
4.8 LQFP100 pinout description
Figure 12. STM32G4A1xE LQFP100 pinout
1. The above figure shows the package top view.
DS13268 Rev 251/200
69
Pinouts and pin descriptionSTM32G4A1xE
4.9 Pin definition
Table 11. Legend/abbreviations used in the pinout table
NameAbbreviationDefinition
Pin name
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
SSupply pin
Pin type
IInput only pin
I/OInput / output pin
FT5 V tolerant I/O
TT3.6 V tolerant I/O
BDedicated BOOT0 pin
NRSTBidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os
I/O structure
_aI/O, with Analog switch function supplied by V
_cI/O, USB Type-C PD capable
_dI/O, USB Type-C PD Dead Battery function
_fI/O, Fm+ capable
_u
(1)
I/O, with USB function
DDA
NotesUnless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Pin functions
Additional
functions
1. The related I/O structures in are FT_u.
Functions directly selected/enabled through peripheral registers
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
3. After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the reference manual RM0440 "STM32G4 Series advanced Arm
MCUs".
4. After reset, a pull-down resistor (Rd = 5.1k
UCPD1_CC2). The pull-down on PB6 (UCPD1_CC1) is activated by high level on PA9 (UCPD1_DBCC1). The pull-down
on PB4 (UCPD1_CC2) is activated by high level on PA10 (UCPD1_DBCC2). This pull-down control (dead battery support
on UCPD peripheral) can be disabled by setting bit UCPD1_DBDIS=1 in the PWR_CR3 register. PB4, PB6 have
UCPD_CC functionality which implements an internal pull-down resistor (5.1k
UCPD_DBCC pin (PA10, PA9). A high level on the UCPD_DBCC pin activates the pull-down on the UCPD_CC pin. The
pull-down effect on the CC lines can be removed by using the bit UCPD1_DBDIS =1 (USB Type-C and power delivery dead
battery disable) in the PWR_CR3 register.
5. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
6. It is recommended to set PB8 in another mode than analog mode after startup to limit consumption if the pin is left
unconnected.
from UCPD peripheral) can be activated on PB6, PB4 (UCPD1_CC1,
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3).
5.1.2 Typical values
= 25 °C and TA = TAmax (given by
A
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = V
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 13.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 14.
Figure 13. Pin loading conditionsFigure 14. Pin input voltage
(mean ±2).
= 3 V. They
DDA
70/200DS13268 Rev 2
STM32G4A1xEElectrical characteristics
MS60206V1
V
DD
Level shifter
IO
logic
Kernel logic
(CPU, Digital
& Memories)
Backup circuitry
(LSE, RTC,
Backup registers)
IN
OUT
Regulator
GPIOs
1.55 – 3.6 V
n x 100 nF
+1 x 4.7 μF
n x VSS
n x VDD
VBAT
V
CORE
Power switch
V
DDIO
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF-
V
DDA
10 nF
+1 μF
VDDA
VSSA
V
REF
100 nF
+1 μF
VREF+
VREF+
Reset block
Temp. sensor
PLL, HSI16, HSI48
Standby circuitry
(Wakeup logic,
IWDG)
5.1.6 Power supply scheme
Figure 15. Power supply scheme
Caution:Each power supply pair (V
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DD/VSS
, V
DDA/VSSA
etc.) must be decoupled with filtering ceramic
DS13268 Rev 271/200
165
Electrical characteristicsSTM32G4A1xE
MS60200V1
I
DD_VBAT
V
BAT
I
DD
V
DD
I
DDA
V
DDA
5.1.7 Current consumption measurement
Figure 16. Current consumption measurement
The I
including the current supplying V
parameters given in Table 21 to Table 33 represent the total MCU consumption
DD_ALL
DD
, V
DDA
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
SymbolRatingsMinMaxUnit
V
- V
DD
External main supply voltage (including VDD,
SS
V
DDA
, V
Input voltage on FT_xxx pins except FT_c pins
(2)
V
IN
Input voltage on FT_c pinsV
Input voltage on TT_xx pinsV
Input voltage on any other pinsV
|V
DDx
|V
SSx-VSS
V
REF+-VDDA
1. All main power (VDD, V
power supply, in the permitted range.
Variations between different V
|
the same domain
|
Variations between all the different ground pins
Allowed voltage difference for V
Table 14. Voltage characteristics
BAT
DDA
and V
, V
BAT
)
REF+
) and ground (VSS, V
and V
BAT
power pins of
DDX
> V
REF+
SSA
.
(1)
-0.34.0
min (V
-
V
0.3
SS
-
0.35.5
SS
-
0.34.0
SS
-
0.34.0
SS
-50
(5)
DDA
) pins must always be connected to the external
-50
-0.4V
+
DD
4.0
, V
(3)(4)
DDA
)
V
mV
72/200DS13268 Rev 2
STM32G4A1xEElectrical characteristics
2. VIN maximum must always be respected. Refer to Table 15: Current characteristics for the maximum
allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin
definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 15. Current characteristics
SymbolRatingsMaxUnit
(1)
(1)
(1)
(1)
150
150
100
100
IV
IV
IV
DD(PIN)
IV
SS(PIN)
Total current into sum of all V
DD
Total current out of sum of all V
SS
Maximum current into each V
Maximum current out of each V
power lines (source)
DD
ground lines (sink)
SS
power pin (source)
DD
ground pin (sink)
SS
Output current sunk by any I/O and control pin except FT_f20
I
IO(PIN)
Output current sunk by any FT_f pin20
Output current sourced by any I/O and control pin20
I
Total output current sunk by sum of all I/Os and control pins
IO(PIN)
I
INJ(PIN)
|I
INJ(PIN)
1. All main power (VDD, V
power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive injection (when V
lower than the specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 14:
Voltage characteristics for the minimum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum |I
the negative injected currents (instantaneous values).
Total output current sourced by sum of all I/Os and control pins
(3)
Injected current on FT_xxx, TT_xx, NRST pins-5/0
|Total injected current (sum of all I/Os and control pins)
, V
DDA
) and ground (VSS, V
BAT
> VDD) is not possible on these I/Os and does not occur for input voltages
IN
) pins must always be connected to the external
SSA
(2)
(2)
(5)
|
is the absolute sum of
INJ(PIN)
100
100
(4)
±25
mA
Table 16. Thermal characteristics
SymbolRatings ValueUnit
T
STG
T
J
Storage temperature range–65 to +150°C
Maximum junction temperature150°C
DS13268 Rev 273/200
165
Electrical characteristicsSTM32G4A1xE
5.3 Operating conditions
5.3.1 General operating conditions
Table 17. General operating conditions
SymbolParameter ConditionsMinMaxUnit
f
HCLK
PCLK1
f
PCLK2
V
Internal AHB clock frequency-0 170
Internal APB1 clock frequency-0 170
Internal APB2 clock frequency-0 170
Standard operating voltage-1.71
DD
(1)
MHzf
3.6V
ADC or COMP used1.62
3.6
DAC 1 MSPS or DAC 15 MSPS1.71
V
Analog supply voltage
DDA
OPAMP used2.03.6
V
VREFBUF used2.4
DD
3.6
+0.3
V
ADC, DAC, OPAMP, COMP,
VREFBUF not used
Backup operating voltage-1.553.6V
BAT
0
TT_xx-0.3V
FT_c I/O-0.35
V
I/O input voltage
IN
All I/O except TT_xx and FT_c-0.3
MIN(MIN(V
)+3.6 V,
V
DDA
(2)(3)
5.5 V)
DD
V
,
See Section 6.10: Thermal characteristics for application
appropriate thermal resistance and package.
P
Power dissipation
D
Power dissipation is then calculated according ambient
temperature (T
) and maximum junction temperature (TJ) and
A
mW
selected thermal resistance.
Ambient temperature for the
suffix 6 version
T
A
Ambient temperature for the
suffix 3 version
Maximum power dissipation -4085
Low-power dissipation
(4)
-40105
Maximum power dissipation -40125
Low-power dissipation
(4)
-40130
°C
T
Junction temperature range
J
1. When RESET is released functionality is guaranteed down to V
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between MIN(V
3. For operation with voltage higher than Min (V
disabled.
4. In low-power dissipation state, T
Thermal characteristics).
can be extended to this range as long as TJ does not exceed T
A
Suffix 3 version-40130
Min.
BOR0
, V
)+3.6 V and 5.5V.
DDA
(see Section 6.10:
Jmax
DD
DD
, V
) +0.3 V, the internal Pull-up and Pull-Down resistors must be
DDA
74/200DS13268 Rev 2
Suffix 6 version-40105
°C
STM32G4A1xEElectrical characteristics
5.3.2 Operating conditions at power-up / power-down
The parameters given in Table 18 are derived from tests performed under the ambient
temperature condition summarized in Table 17.
SymbolParameterConditionsMinMaxUnit
Table 18. Operating conditions at power-up / power-down
t
VDD
t
VDDA
VDD rise time rate
-
fall time rate10
V
DD
V
rise time rate
DDA
fall time rate10
V
DDA
-
0
0
5.3.3 Embedded reset and power control block characteristics
The parameters given in Table 19 are derived from tests performed under the ambient
temperature conditions summarized in Table 17: General operating conditions.
t
RSTTEMPO
Table 19. Embedded reset and power control block characteristics
SymbolParameterConditions
Reset temporization after
V
BOR0
(2)
BOR0 is detected
(2)
Brown-out reset threshold 0
rising-250400s
V
DD
Rising edge1.621.661.7
Falling edge1.61.641.69
Rising edge2.062.12.14
V
BOR1
Brown-out reset threshold 1
Falling edge1.9622.04
(1)
MinTypMaxUnit
µs/V
µs/V
V
V
V
BOR2
V
BOR3
V
BOR4
V
V
V
V
PVD0
PVD1
PVD2
PVD3
Brown-out reset threshold 2
Brown-out reset threshold 3
Brown-out reset threshold 4
Programmable voltage
detector threshold 0
PVD threshold 1
PVD threshold 2
PVD threshold 3
DS13268 Rev 275/200
Rising edge2.262.312.35
V
Falling edge2.162.202.24
Rising edge2.562.612.66
V
Falling edge2.472.522.57
Rising edge2.852.902.95
V
Falling edge2.762.812.86
Rising edge2.12.152.19
V
Falling edge22.052.1
Rising edge2.262.312.36
V
Falling edge2.152.202.25
Rising edge2.412.462.51
V
Falling edge2.312.362.41
Rising edge2.562.612.66
V
Falling edge2.472.522.57
165
Electrical characteristicsSTM32G4A1xE
Table 19. Embedded reset and power control block characteristics (continued)
SymbolParameterConditions
(1)
MinTypMaxUnit
V
PVD4
V
PVD5
V
PVD6
V
hyst_BORH0
V
hyst_BOR_PVD
I
DD
PVM1
PVM2
I
DD
(2)
(2)
(BOR_PVD)
V
V
V
hyst_PVM1
V
hyst_PVM2
(PVM1/PVM2)
PVD threshold 4
V
Falling edge2.592.642.69
Rising edge2.852.912.96
Rising edge2.692.742.79
PVD threshold 5
V
Falling edge2.752.812.86
Rising edge2.922.983.04
PVD threshold 6
V
Falling edge2.842.902.96
Hysteresis in
Hysteresis voltage of BORH0
Hysteresis voltage of BORH
(except BORH0) and PVD
(3)
BOR
(except BOR0) and
PVD consumption from V
V
peripheral voltage
DDA
DD
monitoring (COMP/ADC)
V
peripheral voltage
DDA
monitoring (OPAMP/DAC)
continuous
mode
Hysteresis in
other mode
--100-mV
--1.11.6µA
Rising edge1.611.651.69
Falling edge1.61.641.68
Rising edge1.781.821.86
Falling edge1.771.811.85
-20-
mV
-30-
V
V
PVM1 hysteresis--10-mV
PVM2 hysteresis--10-mV
PVM1 and PVM2
consumption from V
DD
--2-µA
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
76/200DS13268 Rev 2
STM32G4A1xEElectrical characteristics
5.3.4 Embedded voltage reference
The parameters given in Table 20 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 17: General operating
conditions.
SymbolParameterConditionsMinTypMaxUnit
Table 20. Embedded internal voltage reference
V
REFINT
Internal reference
voltage
–40 °C < T
< +130 °C 1.182 1.2121.232V
A
ADC sampling time
t
S_vrefint
(1)
internal reference
-4
(2)
when reading the
voltage
Start time of reference
t
start_vrefint
voltage buffer when
--812
ADC is enable
I
DD(VREFINTBUF
V
consumption from VDD
)
when converted by
REFINT
buffer
--12.520
ADC
Internal reference
V
REFINT
voltage spread over
VDD = 3 V-57.5
the temperature range
T
Coeff
A
Coeff
V
DDCoeff
V
REFINT_DIV1
V
REFINT_DIV2
V
REFINT_DIV3
1. The shortest sampling time is determined in the application by multiple iterations.
2. Guaranteed by design.
Average temperature
coefficient
Long term stability1000 hours, T = 25°C-3001000
Average voltage
coefficient
1/4 reference voltage
1/2 reference voltage495051
3/4 reference voltage747576
–40°C < T
3.0 V < V
< +130°C-3050
A
< 3.6 V-2501200
DD
242526
-
--µs
(2)
(2)
(2)
(2)
(2)
(2)
µs
µA
mV
ppm/°C
ppm
ppm/V
%
V
REFINT
DS13268 Rev 277/200
165
Electrical characteristicsSTM32G4A1xE
MSv40169V2
1.185
1.19
1.195
1.2
1.205
1.21
1.215
1.22
1.225
1.23
1.235
-40-20020406080100120
V
°C
MeanMinMax
Figure 17. V
5.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code
versus temperature
REFINT
The current consumption is measured as described in Figure 16: Current consumption
measurement.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•All I/O pins are in analog input mode
•All peripherals are disabled except when explicitly mentioned
•The Flash memory access time is adjusted with the minimum wait states number,
depending on the f
to CPU clock (HCLK) frequency” available in the reference manual RM0440
"STM32G4 Series advanced Arm
•When the peripherals are enabled f
•The voltage scaling Range 1 is adjusted to f
–Voltage Range 1 Boost mode for 150 MHz < f
–Voltage Range 1 Normal mode for 26 MHz < f
The parameters given in Table 26 to Table 33 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 17: General
operating conditions.
frequency (refer to the table “number of wait states according
HCLK
®
-based 32-bit MCUs").
= f
PCLK
HCLK
frequency as follows:
HCLK
170 MHz
HCLK
150 MHz
HCLK
78/200DS13268 Rev 2
Table 21. Current consumption in Run and Low-power run modes, code with data
STM32G4A1xEElectrical characteristics
processing running from Flash in single Bank, ART enable (Cache ON Prefetch OFF)
DS13268 Rev 279/200
SymbolParameter
IDD (Run)
Supply current
in Run mode
Condition
-
= f
f
HCLK
HSE
up to
48 MHz included,
bypass mode PLL
ON above 48 MHz
all peripherals
disable
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. The supply current in Standby with SRAM2 mode is:
+ RTC) +
4. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.
Supply current during wakeup
from Standby mode
IDD_ALL(SRAM2).
Wakeup clock is
HSI16 = 16 MHz
3.02.3- - - - --- - -mA
(4)
IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IIDD_ALL(Standby
Table 32. Current consumption in Shutdown mode
ConditionsTYPMAX
(1)
SymbolParameter
VDD25°C55°C85°C105°C125°C25°C55°C85°C105°C125°C
1.8 V26.016010503350980051.03202200630018000
2.4 V28.0195120039001150066.03702400700020000
3 V42.0230145045501350089.04502800800022000
IDD
(Shutdown)
Supply current
in Shutdown
mode (backup
registers
-
-
retained) RTC
disabled
3.6 V69.033518505500155001706303400950026000
Unit
nA
SymbolParameter
Table 32. Current consumption in Shutdown mode (continued)
ConditionsTYPMAX
-
VDD25°C55°C85°C105°C125°C25°C55°C85°C105°C125°C
STM32G4A1xEElectrical characteristics
(1)
Unit
IDD
(Shutdown with
RTC)
Supply current
in Shutdown
mode (backup
registers
retained) RTC
enabled
RTC
clocked by
LSE
bypassed
at 32768
Hz
RTC
clocked by
LSE
quartz
1.8 V2303701250355010000-----
2.4 V3304951550420011500-----
3 V4406401850495013500-----
3.6 V5958552350605016500-----
1.8 V37051013503550------
2.4 V47064016504200------
(2)
in
3 V61581020005000------
low drive
DS13268 Rev 293/200
IDD(wakeup
from
Shutdown)
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 35: Low-power mode wakeup timings.
Supply current
during wakeup
from Shutdown
mode
mode
Wakeup
clock is
HSI16 =
16 MHz
3.6 V805105025006100------
3 V1.60- - - - -----mA
(3)
nA
94/200DS13268 Rev 2
SymbolParameter
Table 33. Current consumption in VBAT mode
ConditionsTYPMAX
-
VBAT25°C55°C85°C105°C125°C25°C55°C85°C105°C125°C
1.8 V4.0031.02206801950-----
Electrical characteristicsSTM32G4A1xE
(1)
Unit
RTC
disabled
2.4 V5.0041.02557802250-----
3 V7.0045.03009102600-----
3.6 V13.066.037011003000-----
IDD(VBAT)
Backup domain
supply current
RTC
enabled and
clocked by
LSE
1.8 V215245435895------
2.4 V3003405551100------
3 V4054456951300-----bypassed at
32768 Hz
RTC
enabled and
3.6 V5305758651600------
1.8 V3553955807852050-----
2.4 V4605007208902350-----
clocked by
LSE
(2)
quartz
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
3 V58563589010002650-----
3.6 V735800110012003100-----
nA
STM32G4A1xEElectrical characteristics
I
SW
V
DDIOxfSW
C××=
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 53: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC, OPAMP, COMP input pins
which should be configured as analog inputs.
Caution:Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This is done either by using pull-up/down resistors or by configuring the pins in
output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 35: Low-power mode wakeup timings), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
where
I
is the current sunk by a switching I/O to charge/discharge the capacitive load
SW
V
is the I/O supply voltage
DD
f
is the I/O switching frequency
SW
C is the total capacitance seen by the I/O pin: C = C
INT
+ C
EXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS13268 Rev 295/200
165
Electrical characteristicsSTM32G4A1xE
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 34. The MCU is placed
under the following conditions:
•All I/O pins are in Analog mode
•The given value is calculated by measuring the difference of the current consumptions:
–when the peripheral is clocked on
–when the peripheral is clocked off
•Ambient operating temperature and supply voltage conditions summarized in Table 14:
Voltage characteristics
•The power consumption of the digital part of the on-chip peripherals is given in
Table 34. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 34. Peripheral current consumption
BUSPeripheral
Bus Matrix0.560.490.381.58
AHB
QUADSPI independent clock domain0.380.370.250.46
DMA13.162.942.392.81
DMA23.483.222.642.95
DMAMUX6.736.265.175.96
AHB1
CORDIC1.171.100.891.10
FMAC3.823.552.993.45
FLASH4.884.533.734.38
SRAM10.390.350.330.35
Range 1
Boost Mode
Range 1Range 2
Low-power
run and sleep
Unit
µA/MHzQUADSPI clock domain3.943.673.033.44
µA/MHz
96/200DS13268 Rev 2
STM32G4A1xEElectrical characteristics
Table 34. Peripheral current consumption (continued)
BUSPeripheral
CRC0.900.840.681.02
GPIOA0.600.560.430.46
GPIOB0.590.550.440.58
GPIOC0.650.610.520.52
GPIOD0.520.480.410.62
GPIOE0.590.550.440.71
GPIOF0.610.560.480.68
GPIOG0.680.630.510.66
CCMSRAM0.050.040.030.03
AHB2
SRAM20.120.110.120.28
ADC12 clock domain6.305.854.865.65
ADC12 independent clock domain0.610.550.420.54
ADC3 clock domain3.673.402.843.13
ADC3 independent clock domain0.810.730.560.91
DAC15.244.864.054.70
DAC35.174.804.014.67
AES3.733.452.633.10
Range 1
Boost Mode
Range 1Range 2
Low-power
run and sleep
Unit
µA/MHz
APB1
RNG clock domain2.932.72NANA
RNG independent clock domain3.383.70NANA
TIM210.289.577.889.19
TIM38.307.726.367.40
TIM48.247.676.317.26
TIM62.422.251.862.14
TIM72.522.351.922.14
CRS0.910.840.700.82
RTC3.753.492.913.68
µA/MHz
WWDG1.141.060.881.22
SPI25.194.833.994.60
SPI35.174.833.994.57
I2S2 clock domain3.553.302.753.12
I2S2 independent clock domain1.641.531.241.48
I2S3 clock domain3.553.312.753.29
I2S3 independent clock domain1.631.521.231.28
DS13268 Rev 297/200
165
Electrical characteristicsSTM32G4A1xE
Table 34. Peripheral current consumption (continued)
BUSPeripheral
USART2 clock domain3.933.663.053.44
USART2 independent clock domain7.567.055.816.84
USART3 clock domain3.553.302.773.07
USART3 independent clock domain7.767.235.956.98
UART4 clock domain3.233.012.522.93
UART4 independent clock domain6.285.854.815.41
UART5 clock domain3.923.653.063.41
UART5 independent clock domain6.355.924.865.77
I2C1 clock domain1.911.791.501.53
I2C1 independent clock domain4.344.043.324.06
I2C2 clock domain1.891.761.471.58
I2C2 independent clock domain4.073.803.113.60
APB1
USB clock domain0.340.31NANA
USB independent clock domain3.273.60NANA
FDCAN1 clock domain21.8220.3616.9018.16
FDCAN1 independent clock domain3.042.772.243.78
PWR0.880.810.690.72
Range 1
Boost Mode
Range 1Range 2
Low-power
run and sleep
Unit
µA/MHz
I2C3 clock domain1.791.671.411.54
I2C3 independent clock domain5.004.653.794.45
LPTIM1 clock domain1.741.621.371.61
LPTIM1 independent clock domain4.904.563.724.22
LPUART1 clock domain2.562.382.012.18
LPUART1 independent clock domain5.074.713.864.62
UCPD1 clock domain3.263.042.512.92
UCPD1 independent clock domain2.362.57NANA
98/200DS13268 Rev 2
STM32G4A1xEElectrical characteristics
Table 34. Peripheral current consumption (continued)
BUSPeripheral
SYSCFG/VREFBUF/COMPx/OPAMPx1.641.541.311.51
TIM111.2610.498.689.97
SPI12.922.732.232.61
TIM811.0810.328.539.73
USART1 clock domain2.942.742.302.34
USART1 independent clock domain6.916.465.336.36
APB2
TIM155.825.444.495.18
TIM164.123.853.163.61
TIM173.993.733.083.62
TIM2010.8710.128.379.61
SAI1 clock domain2.552.391.992.37
SAI1 independent clock domain2.602.421.952.10
ALL peripherals278260215248
Range 1
Boost Mode
Range 1Range 2
Low-power
run and sleep
Unit
µA/MHz
DS13268 Rev 299/200
165
Electrical characteristicsSTM32G4A1xE
5.3.6 Wakeup time from low-power modes and voltage scaling
transition times
The wakeup times given in Table 35 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
Table 35. Low-power mode wakeup timings
SymbolParameterConditionsTypMaxUnit
(1)
t
WUSLEEP
t
WULPSLEEP
t
WUSTOP0
t
WUSTOP1
t
WUSTBY
t
WUSTBY
SRAM2
t
WUSHDN
Wakeup time from Sleep
mode to Run mode
Wakeup time from Lowpower sleep mode to Lowpower run mode
Wake up time from Stop 0
mode to Run mode in Flash
Wake up time from Stop 0
mode to Run mode in SRAM1
Wake up time from Stop 1
mode to Run in Flash
Wake up time from Stop 1
mode to Run mode in SRAM1
Wake up time from Stop 1
mode to Low-power run
mode in Flash
Wake up time from Stop 1
mode to Low-power run
mode in SRAM1
Wakeup time from Standby
mode to Run mode
Wakeup time from Standby
with SRAM2 to Run mode
Wakeup time from
Shutdown mode to Run mode
-
-
Range 1Wakeup clock HSI16 = 16 MHz
Range 2Wakeup clock HSI16 = 16 MHz
Range 1Wakeup clock HSI16 = 16 MHz
Range 2Wakeup clock HSI16 = 16 MHz
Range 1Wakeup clock HSI16 = 16 MHz
Range 2Wakeup clock HSI16 = 16 MHz
Range 1Wakeup clock HSI16 = 16 MHz
Range 2Wakeup clock HSI16 = 16 MHz
Regulator in
low-power
mode (LPR=1
in PWR_CR1)
Wakeup clock
HSI16 = 16 MHz,
with HPRE = 8
Range 1Wakeup clock HSI16 = 16 MHz
Range 1Wakeup clock HSI16 = 16 MHz
Range 1Wakeup clock HSI16 = 16 MHz
1112
1011
6.87
18.118.4
2.93.1
2.93.1
10.410.8
21.622
6.66.9
6.46.7
31.437
15.519.2
24.429.6
24.429.6
261305
Nb of
CPU
cycles
µs
Wakeup time from Low-
t
WULPRUN
1. Guaranteed by characterization results.
2. Time until REGLPF flag is cleared in PWR_SR2.
power run mode to Run
(2)
mode
Wakeup clock HSI16 = 16 MHz
HPRE = 8
100/200DS13268 Rev 2
57
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