ST STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC User Manual

STM32F105xx

LQFP100 14 × 14 mm

LQFP64 10 × 10 mm

FBGA

LFBGA100 10 × 10 mm

STM32F107xx

Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB
OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access

– Single-cycle multiplication and hardware

division

■ Memories

– 64 to 256 Kbytes of Flash memory
– 64 Kbytes of general-purpose SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage

detector (PVD)
– 3-to-25 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes
–V

■ 2 × 12-bit, 1 µs A/D converters (16 channels)

supply for RTC and backup registers

BAT

– Conversion range: 0 to 3.6 V
– Sample and hold capability
– Temperature sensor
– up to 2 MSPS in interleaved mode

■ 2 × 12-bit D/A converters

■ DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

2

I

Ss, SPIs, I2Cs and USARTs

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™

■ Up to 80 fast I/O ports

– 51/80 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

■ CRC calculation unit, 96-bit unique ID

■ Up to 10 timers with pinout remap capability

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input

– 1 × 16-bit motor control PWM timer with

dead-time generation and emergency stop

– 2 × watchdog timers (Independent and

Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC

■ Up to 14 communication interfaces with pinout

remap capability
– Up to 2 × I

2

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with a

multiplexed I

2

S interface that offers audio

class accuracy via advanced PLL schemes
– 2 × CAN interfaces (2.0B Active) with

512 bytes of dedicated SRAM
– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY that supports

HNP/SRP/ID with 1.25 Kbytes of dedicated

SRAM
– 10/100 Ethernet MAC with dedicated DMA

and SRAM (4 Kbytes): IEEE1588 hardware

support, MII/RMII available on all packages

Table 1. Device summary

Reference Part number

STM32F105R8, STM32F105V8

STM32F105xx

STM32F107xx

STM32F105RB, STM32F105VB
STM32F105RC, STM32F105VC

STM32F107RB, STM32F107VB
STM32F107RC, STM32F107VC

August 2011 Doc ID 15274 Rev 6 1/103

www.st.com

1

Contents STM32F105xx, STM32F107xx

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 13

2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13

2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13

2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16

2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs) 18

2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.19 Inter-integrated sound (I

2

S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.20 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 19

2.3.21 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS) . . . . . . . . . . . 20

2.3.23 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.24 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.25 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.26 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.27 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.28 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/103 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Contents

2.3.29 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 36

5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.8 PLL, PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 54

5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

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Contents STM32F105xx, STM32F107xx

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 87

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

A.1 USB OTG FS interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

A.2 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

A.3 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

A.4 USB OTG FS interface + Ethernet/I

2

S interface solutions . . . . . . . . . . . . 96

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4/103 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F105xx and STM32F107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10

Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family . . . . . . . . . . . . . . 11

Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 13. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 14. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 39

Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 39

Table 17. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18. Typical current consumption in Sleep mode, code running from Flash or

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 22. HSE 3-25 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 23. LSE oscillator characteristics (f

Table 24. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 27. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 28. PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 31. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 32. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 33. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 34. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 35. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 36. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 37. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 38. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 39. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 40. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 41. I
Table 42. SCL frequency (f

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PCLK1

Table 43. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 44. I

2

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LSE

Doc ID 15274 Rev 6 5/103

List of tables STM32F105xx, STM32F107xx

Table 45. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 46. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 47. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 48. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 49. Dynamic characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 50. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 51. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 52. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 53. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

ADC

Table 54. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 55. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 56. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 57. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 58. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 59. LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 84

Table 60. LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 85

Table 61. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 62. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 63. PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 64. Applicative current consumption in Run mode, code with data

processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 65. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6/103 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx List of figures

List of figures

Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12

Figure 2. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view. . . . . . . . 23

Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 24

Figure 4. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 25

Figure 5. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10. Typical current consumption on V

different V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

BAT

Figure 11. Typical current consumption in Stop mode with regulator in Run mode

versus temperature at different V
Figure 12. Typical current consumption in Stop mode with regulator in Low-power

mode versus temperature at different V
Figure 13. Typical current consumption in Standby mode versus temperature at

different V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DD

Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 15. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 18. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 19. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 20. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 21. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 24. I

2

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 25. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 26. SPI timing diagram - slave mode and CPHA = 1
Figure 27. SPI timing diagram - master mode
Figure 28. I
Figure 29. I

2

S slave timing diagram (Philips protocol)

2

S master timing diagram (Philips protocol)

Figure 30. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 70

Figure 31. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 32. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 33. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 34. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 35. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 36. Power supply and reference decoupling (V
Figure 37. Power supply and reference decoupling (V

Figure 38. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 39. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

Figure 40. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 83

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 41. LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 42. Recommended footprint

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 43. LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

with RTC on vs. temperature at

BAT

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DD

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DD

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

(1)

(1)

REF+

REF+

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

not connected to V
connected to V

DDA

). . . . . . . . . . . . . . 77

DDA

). . . . . . . . . . . . . . . . . 77

Doc ID 15274 Rev 6 7/103

List of figures STM32F105xx, STM32F107xx

Figure 44. Recommended footprint
Figure 45. LQFP100 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

D

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 46. USB OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 47. Host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 48. OTG connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 49. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 50. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 51. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 52. RMII with a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 53. Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 54. Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 55. USB OTG FS + Ethernet solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 56. USB OTG FS + I

2

S (Audio) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8/103 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Introduction

1 Introduction

This datasheet provides the description of the STM32F105xx and STM32F107xx
connectivity line microcontrollers. For more details on the whole STMicroelectronics
STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family.

The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the
STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

2 Description

The STM32F105xx and STM32F107xx connectivity line family incorporates the high­performance ARM
speed embedded memories (Flash memory up to 256 Kbytes and SRAM 64 Kbytes), and
an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer two 12-bit ADCs, four general-purpose 16-bit timers plus a PWM timer, as well
as standard and advanced communication interfaces: up to two I
five USARTs, an USB OTG FS and two CANs. Ethernet is available on the STM32F107xx
only.

The STM32F105xx and STM32F107xx connectivity line family operates in the –40 to
+105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving mode allows the design of low-power applications.

The STM32F105xx and STM32F107xx connectivity line family offers devices in three
different package types: from 64 pins to 100 pins. Depending on the device chosen, different
sets of peripherals are included, the description below gives an overview of the complete
range of peripherals proposed in this family.

These features make the STM32F105xx and STM32F107xx connectivity line
microcontroller family suitable for a wide range of applications such as motor drives and
application control, medical and handheld equipment, industrial applications, PLCs,
inverters, printers, and scanners, alarm systems, video intercom, HVAC and home audio
equipment.

®

Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-

2

Cs, three SPIs, two I2Ss,

Doc ID 15274 Rev 6 9/104

Description STM32F105xx, STM32F107xx

2.1 Device overview

Figure 1 shows the general block diagram of the device family.

Table 2. STM32F105xx and STM32F107xx features and peripheral counts

Flash memory in Kbytes 64 128 256 128 256 64 128 256 128 256

SRAM in Kbytes 64

Package LQFP64

Ethernet No Yes No Yes

Peripherals

(1)

STM32F105Rx STM32F107Rx STM32F105Vx STM32F107Vx

General-purpose 4

LQFP

100

LQFP100,

BGA100

LQFP100

Timers

Advanced-control 1

Basic 2

Communication
interfaces

2S)(2)

SPI(I

2

C2121

I

USART 5

3(2) 3(2) 3(2) 3(2)

USB OTG FS Yes

CAN 2

GPIOs 51 80

12-bit ADC
Number of channels

12-bit DAC
Number of channels

2

16

2
2

CPU frequency 72 MHz

Operating voltage 2.0 to 3.6 V

Operating temperatures

1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required by

the application.

2. The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I

Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Junction temperature: –40 to + 125 °C

2

S audio mode.

10/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Description

2.2 Full compatibility throughout the family

The STM32F105xx and STM32F107xx constitute the connectivity line family whose
members are fully pin-to-pin, software and feature compatible.

The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density
(STM32F103x4/6), medium-density (STM32F103x8/B) and high-density
(STM32F103xC/D/E) performance line devices, allowing the user to try different memory
densities and peripherals providing a greater degree of freedom during the development
cycle.

Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family

STM32
device

Low-density

STM32F103xx devices

Medium-density

STM32F103xx devices

High-density

STM32F103xx devices

STM32F105xx STM32F107xx

(1)

Flash

size (KB)

RAM

size (KB)

16 32 32 64 128 256 384 512 64 128 256 128 256

6101020204864646464646464

144 pins

100 pins

64 pins

48 pins

2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I

2

CAN,
1 × PWM timer
2 × ADCs

C, USB,

2 × USARTs
2 × 16-bit
timers
1 × SPI,

2

1 × I

C,
USB, CAN,
1 × PWM
timer
2 × ADCs

3 × USARTs
3 × 16-bit
timers
2 × SPIs,

2

2 × I

Cs, USB,
CAN,
1 × PWM timer
2 × ADCs

5 × USARTs
4 × 16-bit timers,
2 × basic timers, 3 × SPIs,

2

2 × I

Ss, 2 × I2Cs, USB,
CAN, 2 × PWM timers
3 × ADCs, 2 × DACs,
1 × SDIO, FSMC (100­and 144-pin packages

(2)

5 × USARTs,
4 × 16-bit timers,
2 × basic timers,
3 × SPIs,

2

2 × I

Ss,
2 × I2Cs,
USB OTG FS,
2 × CANs,

)

1 × PWM timer,
2 × ADCs,
2 × DACs

5 × USARTs,
4 × 16-bit timers,
2 × basic timers,
3 × SPIs,

2

2 × I

S,
1 × I2C,
USB OTG FS,
2 × CANs,
1 × PWM timer,
2 × ADCs,
2 × DACs,
Ethernet

36 pins

1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required
by the application.

2. Ports F and G are not available in devices delivered in 100-pin packages.

Doc ID 15274 Rev 6 11/104

Description STM32F105xx, STM32F107xx

2.3 Overview

Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram

TRACECLK

TRACED[ 0:3]

as AF

NJTRST

JTDI

JTCK /SWCLK

JTMS/SWDIO

JTDO
as AF

MII_TXD[3:0]/RMII_TXD[1:0]

MII_TX_CLK/RMII_TX_CLK

MII_TX_EN/RMII_TX_EN

MII_RXD[3:0]/RMII_RXD[1:0]

MII_RX_ER/RMII_RX_ER

MII_RX_CLK/RMII_REF_CLK

MII_RX_DV/RMII_CRS_DV

MII_CRS

MII_COL/RMII_COL

MDC

MDIO

PPS_OUT

SOF

VBUS

ID

DM

DP

80 AF

PA[1 5:0]

PB[1 5:0]

PC[15:0 ]

PD[15:0 ]

PE[15:0 ]

4 Channels
4 compl. Channels

BKIN, ETR input as AF

MOSI,MISO,

SCK,NSS as AF

RX,TX, CTS, RTS,
CK as AF

16 ADC12_INs
common to
ADC1 & ADC2

V

REF–

V

REF+

TPIU

ETM

Trace/Trig

SW/JTAG

Cortex-M3 CPU

F

: 72 MHz

max

NVIC

GP DMA1

7 ch annels

GP DMA2

5 channels

Ethernet MAC

10/100

DMA Ethernet

DPRAM 2 KB DPRAM 2 KB

USB OTG FS

SRAM 1.25 KB

EXT.IT
WKUP

GPIO port AP

GPIO port BP

GPIO port C

GPIO port D

GPIO port E

TIM1

SPI1

USART1

Temp sensor

12bit ADC1

12bit ADC2

IF

IF

@VDDA

Dbus

System

Ibus

= 72 MHz

max

APB2 : F

Bus Matri x

AHB to
APB2

obl

Flashl

AHB

AHB to
APB1

Flash 256 KB

Int erface

SRAM

64 KB

Reset &
clock
control

64 bit

WWDG

TIM6

TIM7

PCLK1
PCLK2

HCLK
FCLK
PLL3

PLL

@V

RC HS

RC LS

PLL3

PLL2

DDA

V

Reset

= 36 MHz

max

APB1 : F

DD18

POR

Int

@V

RTC

AWU

Backup interface

2x(8x16bit)

2x(8x16bit)

SRAM 512B

IFIF

IF

Power

Voltage reg.

3.3 V to 1.8 V

@V

DD

Supply

supervision

POR / PDR

PVD

DDA

@V

XT

AL osc

3-25 MHz

IWDG

Standby

interface

@V

XTAL 32kHz

Backup
register

TIM2

TIM3

TIM4

TIM5

USART2

USART3

UART4

UART5

SPI2 / I2S2

SPI3 / I2S3

I2C1

I2C2

bxCAN1

bxCAN2

12bit DAC1

12bit DAC 2

@VDDA

DD

BAT

(1)

VDD = 2 to 3.6 V

V

SS

NRST
V

DDA

V

SSA

OSC_IN
OSC_OUTC_O

V

=1.8 V to 3.6 V

BAT

OSC32_IN

OSC32_OUT

TAMPER-RTC/
ALARM/SECOND OUT

4 Channels, ETR

as AF

4 Channels, ETR

as AF

4 Channels, ETR

as AF

4 Channel s, ETR

as AF
RX,TX, CTS, RTS,
CK as AF

RX,TX, CTS, RTS,

CK as AF

RX,TX as AF

RX,TX as AF

MOSI/SD, MISO, MCK,
SCK/CK, NSS/WS as AF

MOSI/SD, MISO, MCK,

SCK/CK, NSS/WS as AF

SCL,SDA,SMBA
as AF

SCL,SDA,SMBA
as AF

CAN1_TX as AF

CAN1_RX as AF

CAN2_TX as AF

CAN2_RX as AF

DAC_OUT1 as AF

DAC_OUT2 as AF

ai15411

1. TA = –40 °C to +85 °C (suffix 6, see Table 62) or –40 °C to +105 °C (suffix 7, see Table 62), junction temperature up to
105 °C or 125 °C, respectively.

2. AF = alternate function on I/O port pin.

12/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Description

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is
compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2 Embedded Flash memory

64 to 256 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

2.3.4 Embedded SRAM

64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.5 Nested vectored interrupt controller (NVIC)

The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt
controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

Doc ID 15274 Rev 6 13/104

Description STM32F105xx, STM32F107xx

2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 20 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).

A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG
FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency,
the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum
frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed
frequency of the low speed APB domain is 36 MHz. Refer to Figure 55: USB OTG FS +

Ethernet solution on page 96.

The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. In order to achieve audio class performance, an audio crystal can be used. In this
case, the I
96 kHz with less than 0.5% accuracy error. Refer to Figure 56: USB OTG FS + I2S (Audio)

solution on page 96.

To configure the PLLs, please refer to Table 63 on page 97, which provides PLL
configurations according to the application type.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from User Flash

● Boot from System Memory

● Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode
(DFU: device firmware upgrade). For remapped signals refer to Table 5: Pin definitions.

The USART peripheral operates with the internal 8 MHz oscillator (HSI), however the CAN
and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock
(HSE) is present.

For full details about the boot loader, please refer to AN2606.

2

S master clock can generate all standard sampling frequencies from 8 kHz to

14/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Description

2.3.9 Power supply schemes

● V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V

● V

SSA

, V

= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs

DDA

and PLL (minimum voltage to be applied to V

● V

and V

BAT

must be connected to VDD and VSS, respectively.

SSA

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

2.3.10 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V

is below a specified threshold, V

DD

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

generated when V
than the V

power supply and compares it to the V

DD/VDDA

threshold. The interrupt service routine can then generate a warning

PVD

drops below the V

message and/or put the MCU into a safe state. The PVD is enabled by software.

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop modes.

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)

DD

pins.

is 2.4 V when the ADC is used). V

DDA

is not present.

DD

POR/PDR

threshold. An interrupt can be

PVD

threshold and/or when VDD/V

PVD

, without the need for an

is higher

DDA

DDA

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.12 Low-power modes

The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to
achieve the best compromise between low power consumption, short startup time and
available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
OTG FS wakeup.

Doc ID 15274 Rev 6 15/104

Description STM32F105xx, STM32F107xx

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.13 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to­peripheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I
and advanced control timers TIMx, DAC, I

2

S and ADC.

2

C, USART, general-purpose, basic

In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see

Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support for

more information).

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
V

supply when present or through the V

DD

registers used to store 84 bytes of user application data when V
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.

For more information, please refer to AN2604: “STM32F101xx and STM32F103xx RTC
calibration”, available from www.st.com.

BAT

pin. The backup registers are forty-two 16-bit

power is not present.

DD

16/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Description

2.3.15 Timers and watchdogs

The STM32F105xx and STM32F107xx devices include an advanced-control timer, four
general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.

Ta bl e 4 compares the features of the general-purpose and basic timers.

Table 4. Timer feature comparison

Timer

Counter

resolution

TIM1 16-bit

Counter

type

Up,

down,

up/down

Prescaler

factor

Any integer

between 1

and 65536

DMA request

generation

Capture/compare

channels

Ye s 4 Ye s

Complementary

outputs

TIMx

(TIM2,

TIM3,
TIM4,

16-bit

Up,

down,

up/down

Any integer

between 1
and 65536

Ye s 4 N o

TIM5)

TIM6,

TIM7

16-bit Up

Any integer

between 1
and 65536

Ye s 0 N o

Advanced-control timer (TIM1)

The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:

● Input capture

● Output compare

● PWM generation (edge or center-aligned modes)

● One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded
in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based
on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent
channels each for input capture/output compare, PWM or one pulse mode output. This
gives up to 16 input captures / output compares / PWMs on the largest packages. They can
work together with the Advanced Control timer via the Timer Link feature for synchronization
or event chaining.

The counter can be frozen in debug mode.

Doc ID 15274 Rev 6 17/104

Description STM32F105xx, STM32F107xx

Any of the standard timers can be used to generate PWM outputs. Each of the timers has
independent DMA request generations.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

2.3.16 I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F105xx and STM32F107xx connectivity line embeds three universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and
two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other
available interfaces communicate at up to 2.25 Mbit/s.

18/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Description

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.

2.3.18 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC/SDHC

(a)

modes.

All SPIs can be served by the DMA controller.

2.3.19 Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
96 kHz are supported. When either or both of the I
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency with less than 0.5% accuracy error owing to the advanced clock
controller (see Section 2.3.7: Clocks and startup).

2

S interfaces is/are configured in master

Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral
interface (SPI)” section of the STM32F10xxx reference manual.

2.3.20 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral not available on STM32F105xx devices.

The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard media-independent
interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx
requires an external physical interface device (PHY) to connect to the physical LAN bus
(twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many
as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz
(RMII) output from the STM32F107xx.

The STM32F107xx includes the following features:

● Supports 10 and 100 Mbit/s rates

● Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM

and the descriptors (see the STM32F105xx/STM32F107xx reference manual for
details)

● Tagged MAC frame support (VLAN support)

● Half-duplex (CSMA/CD) and full-duplex operation

● MAC control sublayer (control frames) support

a. SDHC = Secure digital high capacity.

Doc ID 15274 Rev 6 19/104

Description STM32F105xx, STM32F107xx

● 32-bit CRC generation and removal

● Several address filtering modes for physical and multicast address (multicast and group

addresses)

● 32-bit status code for each transmitted or received frame

● Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive

FIFO are both 2 Kbytes, that is 4 Kbytes in total

● Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with

the timestamp comparator connected to the TIM2 trigger input

● Triggers interrupt when system time becomes greater than target time

2.3.21 Controller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total)
are not shared with any other peripheral.

2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS)

The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full­speed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS
peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It
has software-configurable endpoint setting and supports suspend/resume. The USB OTG
full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL
connected to the HSE oscillator. The major features are:

● 1.25 KB of SRAM used exclusively by the endpoints (not shared with any other

peripheral)

● 4 bidirectional endpoints

● HNP/SNP/IP inside (no need for any external resistor)

● for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

● the SOF output can be used to synchronize the external audio DAC clock in

isochronous mode

● in accordance with the USB 2.0 Specification, the supported transfer speeds are:

– in Host mode: full speed and low speed

– in Device mode: full speed

2.3.23 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current­capable.

The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

20/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Description

2.3.24 Remap capability

This feature allows the use of a maximum number of peripherals in a given application.
Indeed, alternate functions are available not only on the default pins but also on other
specific pins onto which they are remappable. This has the advantage of making board
design and port usage much more flexible.

For details refer to Table 5: Pin definitions; it shows the list of remappable alternate functions
and the pins onto which they can be remapped. See the STM32F10xxx reference manual
for software considerations.

2.3.25 ADCs (analog-to-digital converters)

Two 12-bit analog-to-digital converters are embedded into STM32F105xx and
STM32F107xx connectivity line devices and each ADC shares up to 16 external channels,
performing conversions in single-shot or scan modes. In scan mode, automatic conversion
is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

● Simultaneous sample and hold

● Interleaved sample and hold

● Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1)
can be internally connected to the ADC start trigger and injection trigger, respectively, to
allow the application to synchronize A/D conversion and timers.

2.3.26 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

● two DAC converters: one for each output channel

● 8-bit or 12-bit monotonic output

● left or right data alignment in 12-bit mode

● synchronized update capability

● noise-wave generation

● triangular-wave generation

● dual DAC channel independent or simultaneous conversions

● DMA capability for each channel

● external triggers for conversion

● input voltage reference V

REF+

Doc ID 15274 Rev 6 21/104

Description STM32F105xx, STM32F107xx

Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line
family. The DAC channels are triggered through the timer update outputs that are also
connected to different DMA channels.

2.3.27 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V

< 3.6 V. The temperature sensor is internally

DDA

connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.

2.3.28 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.3.29 Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.

22/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Pinouts and pin description

3 Pinouts and pin description

Figure 2. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout top view

87654321

109

PC14-

A

OSC32_IN

PC15-

B PC11PD2

OSC32_OUT

C

OSC_IN

D PD4

OSC_OUT V

E

F

G

PC0

V

SSA

PC13-

TAMPER-RTC

V

BAT

V

SS_5

DD_5

PC2

PC1

PA0-WKUP

PE2

PE4

PE5

PC3

PB9

PB8PE3

PE1

PE0

V

SS_4

V

DD_4

PC4PA4

PB7

PB6

PB5

PB4

PD5

PD6

BOOT0 PD7

V

SS_3

DD_3

PB2

V

V

DD_2

PE10

SS_2

PB3

PD3

V

SS_1

V

DD_1

PE14

PA15

PC12

PD0

PD1PE6NRST

NCV

PB15

PA14

PC10

PA9

PA8

PC9

PC8

PD11

PA13

PA12

PA11

PA10

PC7

PC6

PD15

H

V

REF–

J

V

REF+

K

DDA

PA1

PA2

PA3

PC5PA5

PB0PA6

PE8

PB1PA7

PE11PE7

PE12

PE13PE9V

PE15

PB10

PB11

PB14

PB13

PB12

PD10

PD14

PD9 PD13

PD8

PD12

AI16001c

Doc ID 15274 Rev 6 23/104

Pinouts and pin description STM32F105xx, STM32F107xx

100

9998979695949392919089888786858483828180797877

76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VDD_2
VSS_2
NC
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

VDD_1

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

26272829303132333435363738394041424344454647484950

PE2
PE3
PE4
PE5
PE6

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

OSC_IN

OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VREF-

VREF+

VDDA

PA 0- W K UP

PA 1
PA 2

ai14391

LQFP100

Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout

24/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Pinouts and pin description

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

V

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

PC0
PC1
PC2
PC3

V

SSA

V

DDA

PA 0- W K UP

PA 1
PA 2

V

DD_3

V

SS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA 1 5

PA 14

V

DD_2

V

SS_2

PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12

PA 3

V

SS_4

V

DD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

V

SS_1

V

DD_1

LQFP64

ai14392

Figure 4. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout

Doc ID 15274 Rev 6 25/104

Pinouts and pin description STM32F105xx, STM32F107xx

Table 5. Pin definitions

Pins

BGA100

A3 - 1 PE2 I/O

B3 - 2 PE3 I/O

C3 - 3 PE4 I/O

D3 - 4 PE5 I/O

E3 - 5 PE6 I/O

B2 1 6 V

A2 2 7

A1 3 8

B1 4 9

C2 - 10 V

D2 - 11 V

LQFP64

LQFP100

PC13-TAMPER-

OSC32_OUT

Pin name

BAT

(5)

RTC

PC14-

OSC32_IN

PC15-

SS_5

DD_5

(2)

(1)

Typ e

function

(after reset)

I / O Level

FT

FT

FT

FT

FT

SV

I/O PC13

I/O PC14

(5)

I/O PC15

(5)

SV

SV

Main

(3)

Default Remap

PE2 TRACECK

PE3 TRACED0

PE4 TRACED1

PE5 TRACED2

PE6 TRACED3

BAT

(6)

(6)

(6)

SS_5

DD_5

TAMPER-RTC

OSC32_IN

OSC32_OUT

C1 5 12 OSC_IN I OSC_IN

D1 6 13 OSC_OUT O OSC_OUT

E1 7 14 NRST I/O NRST

F1 8 15 PC0 I/O PC0 ADC12_IN10

F2 9 16 PC1 I/O PC1

ADC12_IN11/ ETH_MII_MDC/

ETH_RMII_MDC

E2 10 17 PC2 I/O PC2 ADC12_IN12/ ETH_MII_TXD2

F3 11 18 PC3 I/O PC3

G1 12 19 V

H1 - 20 V

J1 - 21 V

K1 13 22 V

SSA

REF-

REF+

DDA

SV

SV

SV

SV

SSA

REF-

REF+

DDA

ADC12_IN13/

ETH_MII_TX_CLK

WKUP/USART2_CTS

G2 14 23 PA0-WKUP I/O PA0

ADC12_IN0/TIM2_CH1_ETR

TIM5_CH1/

ETH_MII_CRS_WKUP

USART2_RTS

H 2 15 2 4 PA 1 I / O PA 1

TIM5_CH2 /TIM2_CH2

ETH_MII_RX_CLK/

ETH_RMII_REF_CLK

Alternate functions

(7)

(7)

/ ADC12_IN1/

(7)

/

(4)

26/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Pinouts and pin description

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

Pin name

LQFP100

(2)

(1)

Typ e

Main

function

(after reset)

I / O Level

J 2 1 6 25 PA 2 I /O PA 2

(3)

USART2_TX

TIM5_CH3/ADC12_IN2/

TIM2_CH3

Alternate functions

Default Remap

(7)

/

(7)

/ ETH_MII_MDIO/

ETH_RMII_MDIO

(7)

/

/ ETH_MII_COL

/DAC_OUT1 /

(7)

/ ADC12_IN4

(7)

/

(7)

/ADC12_IN6 /

(7)

(7)

/ADC12_IN7 /

(7)

/

(8)

/

K 2 1 7 2 6 PA 3 I / O PA 3

E4 18 27 V

F4 19 28 V

SS_4

DD_4

SV

SV

SS_4

DD_4

G 3 2 0 2 9 PA 4 I /O PA 4

H 3 2 1 3 0 PA 5 I / O PA 5

J 3 2 2 31 PA 6 I /O PA 6

K 3 2 3 32 PA 7 I/ O PA 7

USART2_RX

TIM5_CH4/ADC12_IN3 /

TIM2_CH4

SPI1_NSS

(7)

(7)

USART2_CK

SPI1_SCK

DAC_OUT2 / ADC12_IN5

SPI1_MISO

TIM3_CH1

SPI1_MOSI

TIM3_CH2

ETH_MII_RX_DV

ETH_RMII_CRS_DV

G4 24 33 PC4 I/O PC4

ADC12_IN14/

ETH_MII_RXD0

(8)

/

ETH_RMII_RXD0

H4 25 34 PC5 I/O PC5

ADC12_IN15/

ETH_MII_RXD1

(8)

/

ETH_RMII_RXD1

J4 26 35 PB0 I/O PB0

K4 27 36 PB1 I/O PB1

G5 28 37

PB2 I/O FT PB2/BOOT1

ADC12_IN8/TIM3_CH3/

ETH_MII_RXD2

ADC12_IN9/TIM3_CH4

ETH_MII_RXD3

(8)

(8)

(7)

/

H5 - 38 PE7 I/O FT PE7 TIM1_ETR

J5 - 39 PE8 I/O FT PE8 TIM1_CH1N

K5 - 40 PE9 I/O FT PE9 TIM1_CH1

--- V

--- V

G6 - 41 PE10 I/O FT PE10 TIM1_CH2N

SS_7

DD_7

S

S

H6 - 42 PE11 I/O FT PE11 TIM1_CH2

J6 - 43 PE12 I/O FT PE12 TIM1_CH3N

(4)

SPI3_NSS/I2S3_WS

TIM1_BKIN

TIM1_CH1N

TIM1_CH2N

TIM1_CH3N

Doc ID 15274 Rev 6 27/104

Pinouts and pin description STM32F105xx, STM32F107xx

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

LQFP100

Pin name

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

Alternate functions

Default Remap

K6 - 44 PE13 I/O FT PE13 TIM1_CH3

G7 - 45 PE14 I/O FT PE14 TIM1_CH4

H7 - 46 PE15 I/O FT PE15 TIM1_BKIN

J7 29 47 PB10 I/O FT PB10

K7 30 48 PB11 I/O FT PB11

I2C2_SCL

ETH_MII_RX_ER

I2C2_SDA

ETH_MII_TX_EN/

(8)

/USART3_TX

(8)

/USART3_RX

(7)

(7)

/

/

ETH_RMII_TX_EN

E7 31 49 V

F7 32 50 V

SS_1

DD_1

K8 33 51 PB12 I/O FT PB12

SV

SV

SS_1

DD_1

SPI2_NSS

I2C2_

USART3_CK

(8)

/I2S2_WS

(8)

SMBA

(7)

/ TIM1_BKIN

(8)

/

/

(7)

/

CAN2_RX/ ETH_MII_TXD0/

ETH_RMII_TXD0

J8 34 52 PB13 I/O FT PB13

SPI2_SCK

(8)

/ I2S2_CK

USART3_CTS

TIM1_CH1N/CAN2_TX/

(7)

(8)

/

/

ETH_MII_TXD1/

ETH_RMII_TXD1

(8)

H8 35 53 PB14 I/O FT PB14

G8 36 54 PB15 I/O FT PB15

SPI2_MISO

SPI2_MOSI

/ TIM1_CH2N /

USART3_RTS

(8)

/ I2S2_SD

TIM1_CH3N

(7)

(7)

(8)

/

K9 - 55 PD8 I/O FT PD8

J9 - 56 PD9 I/O FT PD9

H9 - 57 PD10 I/O FT PD10

G9 - 58 PD11 I/O FT PD11

K10 - 59 PD12 I/O FT PD12

J10 - 60 PD13 I/O FT PD13 TIM4_CH2

H10 - 61 PD14 I/O FT PD14 TIM4_CH3

(4)

TIM2_CH3

TIM2_CH4

USART3_TX/

ETH_MII_RX_DV/

ETH_RMII_CRS_DV

USART3_RX/

ETH_MII_RXD0/

ETH_RMII_RXD0

USART3_CK/

ETH_MII_RXD1/

ETH_RMII_RXD1

USART3_CTS/

ETH_MII_RXD2

TIM4_CH1 /

USART3_RTS/

ETH_MII_RXD3

28/104 Doc ID 15274 Rev 6

STM32F105xx, STM32F107xx Pinouts and pin description

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

LQFP100

Pin name

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

Alternate functions

Default Remap

G10 - 62 PD15 I/O FT PD15 TIM4_CH4

F10 37 63 PC6 I/O FT PC6 I2S2_MCK/ TIM3_CH1

E10 38 64 PC7 I/O FT PC7 I2S3_MCK TIM3_CH2

F9 39 65 PC8 I/O FT PC8 TIM3_CH3

E9 40 66 PC9 I/O FT PC9 TIM3_CH4

D 9 4 1 6 7 PA 8 I / O F T PA8

C 9 4 2 6 8 PA 9 I / O F T PA9

D10 43 69 PA10 I/O FT PA10

C10 44 70 PA11 I/O FT PA11

B10 45 71 PA12 I/O FT PA12

USART1_CK/OTG_FS_SOF /

TIM1_CH1

USART1_TX

(8)

/MCO

(7)

/ TIM1_CH2

(7)

OTG_FS_VBUS

(7)

USART1_RX

TIM1_CH3

USART1_CTS / CAN1_RX /

TIM1_CH4

USART1_RTS / OTG_FS_DP /

CAN1_TX

(7)

(7)

/OTG_FS_DM

(7)

/ TIM1_ETR

/

/OTG_FS_ID

(7)

/

A10 46 72 PA13 I/O FT JTMS-SWDIO

F8 - 73 Not connected

E6 47 74

F6 48 75

A9 49 76

A8 50 77

B9 51 78

B8 52 79

C8 53 80

--81

--82

B7 54 83

C7 - 84

D7 - 85

B6 - 86

C6 - 87

D6 - 88

V

V

SS_2

DD_2

SV

SV

SS_2

DD_2

PA14 I/O FT JTCK-SWCLK PA14

PA15 I/O FT JTDI SPI3_NSS / I2S3_WS

PC10 I/O FT PC10 UART4_TX

PC11 I/O FT PC11 UART4_RX

PC12 I/O FT PC12 UART5_TX

PD0 I/O FT PD0 OSC_IN

PD1 I/O FT PD1 OSC_OUT

PD2 I/O FT PD2 TIM3_ETR / UART5_RX

PD3 I/O FT PD3

PD4 I/O FT PD4

PD5 I/O FT PD5

PD6 I/O FT PD6

PD7 I/O FT PD7

(4)

PA 1 3

TIM2_CH1_ETR

SPI1_NSS

USART3_TX/

SPI3_SCK/I2S3_CK

USART3_RX/

SPI3_MISO

USART3_CK/

SPI3_MOSI/I2S3_SD

(9)

(9)

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

/ PA15

/

CAN1_RX

/

CAN1_TX

Doc ID 15274 Rev 6 29/104

Pinouts and pin description STM32F105xx, STM32F107xx

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

A7 55 89

A6 56 90

Pin name

LQFP100

PB3 I/O FT JTDO SPI3_SCK / I2S3_CK

PB4 I/O FT NJTRST SPI3_MISO

(2)

(1)

Typ e

Main

function

(after reset)

I / O Level

C5 57 91 PB5 I/O PB5

(3)

I2C1_

SMBA

ETH_MII_PPS_OUT /

Alternate functions

Default Remap

/ SPI3_MOSI /

I2S3_SD

ETH_RMII_PPS_OUT

B5 58 92 PB6 I/O FT PB6 I2C1_SCL

A5 59 93 PB7 I/O FT PB7 I2C1_SDA

(7)

/TIM4_CH1

(7)

/TIM4_CH2

(7)

(7)

D5 60 94 BOOT0 I BOOT0

B4 61 95 PB8 I/O FT PB8 TIM4_CH3

A4 62 96 PB9 I/O FT PB9 TIM4_CH4

(7)

/ ETH_MII_TXD3 I2C1_SCL/CAN1_RX

(7)

D4 - 97 PE0 I/O FT PE0 TIM4_ETR

C4 - 98 PE1 I/O FT PE1

E5 63 99 V

F5 64 100 V

SS_3

DD_3

1. I = input, O = output, S = supply, HiZ = high impedance.

2. FT = 5 V tolerant. All I/Os are V

3. Function availability depends on the chosen device.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.

8. SPI2/I2S2 and I2C2 are not available when the Ethernet is being used.

9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and BGA100 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual.

SV

SV

capable.

DD

SS_3

DD_3

(4)

PB3 / TRACESWO/

TIM2_CH2 / SPI1_SCK

TIM3_CH1/

PB4 /

SPI1_MISO

TIM3_CH2/SPI1_MOSI/

CAN2_RX

USART1_TX/CAN2_TX

USART1_RX

I2C1_SDA / CAN1_TX

30/104 Doc ID 15274 Rev 6