ST STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC User Manual

STM32F105xx

FBGA

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LFBGA100 10 × 10 mm

STM32F107xx

Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB

OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces

Preliminary Data

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access

– Single-cycle multiplication and hardware

division

■ Memories

– 64 to 256 Kbytes of Flash memory
– up to 64 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage

detector (PVD)
– 3-to-25 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes
–V

■ 2 × 12-bit, 1 µs A/D converters (16 channels)

supply for RTC and backup registers

BAT

– Conversion range: 0 to 3.6 V
– Sample and hold capability
– Temperature sensor
– up to 2 MSps in interleaved mode

■ 2 × 12-bit D/A converters

■ DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

2

I

Ss, SPIs, I2Cs and USARTs

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™

■ Up to 80 fast I/O ports

– 51/80 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

■ Up to 10 timers

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input

– 1 × 16-bit motor control PWM timer with

dead-time generation and emergency stop

– 2 × watchdog timers (Independent and

Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC

■ Up to 14 communication interfaces

– Up to 2 × I

2

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with a

multiplexed I

2

S interface that offers audio

class accuracy via advanced PLL schemes
– 2 × CAN interfaces (2.0B Active) with

512 bytes of dedicated SRAM
– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY that supports

HNP/SRP/ID with 1.25 Kbytes of dedicated

SRAM
– 10/100 Ethernet MAC with dedicated DMA

and SRAM (4 Kbytes): IEEE1588 hardware

support, MII/RMII available on all packages

■ CRC calculation unit, 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F105R8, STM32F105V8

STM32F105xx

STM32F107xx

STM32F105RB, STM32F105VB
STM32F105RC, STM32F105VC

STM32F107RB, STM32F107VB
STM32F107RC, STM32F107VC

February 2009 Rev 2 1/90

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

www.st.com

1

Contents STM32F105xx, STM32F107xx

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 ARM® CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . 11

2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 12

2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 12

2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 15

2.4 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4.7 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.8 Universal synchronous/asynchronous receiver transmitters (USARTs) 17

2.4.9 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.10 Inter-integrated sound (I

2.4.11 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 17

2.4.12 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2

S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.13 Universal serial bus on-the-go full-speed (USB OTG FS) . . . . . . . . . . . 18

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STM32F105xx, STM32F107xx Contents

2.4.14 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.15 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.16 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.17 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.18 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.19 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 35

5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 53

5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Contents STM32F105xx, STM32F107xx

5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Appendix A Applicative block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

A.1 USB OTG FS interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

A.2 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

A.3 Complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A.4 USB OTG FS interface + Ethernet/I

2

S interface solutions . . . . . . . . . . . . 87

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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STM32F105xx, STM32F107xx List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F105xx and STM32F107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10

Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family . . . . . . . . . . . . . . 11

Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 12. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 14. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 39

Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 40

Table 17. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18. Typical current consumption in Sleep mode, code with data processing

code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 22. HSE 3-25 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 23. LSE oscillator characteristics (f

Table 24. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 27. PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 28. PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 31. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 32. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 33. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 34. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 36. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 37. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 38. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 39. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 40. I
Table 41. SCL frequency (f

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

PCLK1

Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 43. I

2

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 44. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LSE

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List of tables STM32F105xx, STM32F107xx

Table 45. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 46. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 47. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 48. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 49. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 50. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 51. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

ADC

Table 52. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 53. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 54. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 55. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 56. LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 76

Table 57. LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 78

Table 58. LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 79

Table 59. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 60. PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 61. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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STM32F105xx, STM32F107xx List of figures

List of figures

Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 21

Figure 2. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 22

Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 23

Figure 4. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout. . . . . . . . . . . . . . . 24

Figure 5. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 6. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 7. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 8. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 10. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 38

Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 38

Figure 12. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at different V
Figure 13. Current consumption in Stop mode with regulator in Low-power mode versus

temperature at different V
Figure 14. Current consumption in Standby mode versus temperature at different V

Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 16. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 19. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 20. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 21. I

2

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 23. SPI timing diagram - slave mode and CPHA = 1
Figure 24. SPI timing diagram - master mode
Figure 25. I
Figure 26. I

2

S slave timing diagram

2

S master timing diagram

Figure 27. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 66

Figure 28. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 29. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 30. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 31. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 32. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 33. Power supply and reference decoupling (V
Figure 34. Power supply and reference decoupling (V

Figure 35. LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 76

Figure 36. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 77

Figure 37. LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 38. Recommended footprint

Figure 39. LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 40. Recommended footprint

Figure 41. USB OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 42. Host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 43. OTG connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 44. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DD

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DD

(1)

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

REF+

REF+

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

not connected to V
connected to V

DDA

). . . . . . . . . . . . . . . . . 72

DDA

values . . . . . 41

DD

). . . . . . . . . . . . . . 72

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List of figures STM32F105xx, STM32F107xx

Figure 45. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 46. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 47. RMII with a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 48. Complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 49. Complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 50. USB OTG FS + Ethernet solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 51. USB OTG FS + I

2

S (Audio) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8/90

STM32F105xx, STM32F107xx Introduction

1 Introduction

This datasheet provides the description of the STM32F105xx and STM32F107xx
connectivity line microcontrollers. For more details on the whole STMicroelectronics
STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family.

The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the
STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

2 Description

The STM32F105xx and STM32F107xx connectivity line family incorporates the high­performance ARM
speed embedded memories (Flash memory up to 256 Kbytes and SRAM up to 64 Kbytes),
and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer two 12-bit ADCs, four general-purpose 16-bit timers plus a PWM timer, as well
as standard and advanced communication interfaces: up to two I
five USARTs, an USB OTG FS and two CANs. Ethernet is available on the STM32F107xx
only.

The STM32F105xx and STM32F107xx connectivity line family operates in the –40 to +105
°C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power­saving mode allows the design of low-power applications.

The STM32F105xx and STM32F107xx connectivity line family offers devices in three
different package types: from 64 pins to 100 pins. Depending on the device chosen, different
sets of peripherals are included, the description below gives an overview of the complete
range of peripherals proposed in this family.

®

Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-

2

Cs, three SPIs, two I2Ss,

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Description STM32F105xx, STM32F107xx

These features make the STM32F105xx and STM32F107xx connectivity line
microcontroller family suitable for a wide range of applications:

● Motor drive and application control

● Medical and handheld equipment

● Industrial applications: PLC, inverters, printers, and scanners

● Alarm systems, Video intercom, and HVAC

● Car audio, home audio equipment

Figure 1 shows the general block diagram of the device family.

2.1 Device overview

Table 2. STM32F105xx and STM32F107xx features and peripheral counts

Peripherals STM32F105Rx STM32F107Rx STM32F105Vx STM32F107Vx

Flash memory in Kbytes 64 128 256 128 256 64 128 256 128 256

SRAM in Kbytes 20 32 64 48 64 20 32 64 48 64

Ethernet No Yes No Yes

General-purpose 4

Timers

Advanced-control 1

Basic 2

Communication
interfaces

2S)(1)

SPI(I

2

I

C2

USART 5

3(2)

USB OTG FS Yes

CAN 2

GPIOs 51 80

12-bit ADC
Number of channels

12-bit DAC
Number of channels

2

16

2
2

CPU frequency 72 MHz

Operating voltage 2.0 to 3.6 V

Operating temperatures

Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Junction temperature: –40 to + 125 °C

Package LQFP64 LQFP100, BGA100

1. The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I2S audio mode.

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STM32F105xx, STM32F107xx Description

2.2 Full compatibility throughout the family

The STM32F105xx and STM32F107xx constitute the connectivity line family whose
members are fully pin-to-pin, software and feature compatible.

The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density
(STM32F103x4/6), medium-density (STM32F103x8/B) and high-density
(STM32F103xC/D/E) performance line devices, allowing the user to try different memory
densities and peripherals providing a greater degree of freedom during the development
cycle.

Table 3. STM32F105xx and STM32F107xx family versus STM32F103xx family

STM32
device

Low-density

STM32F103xx

devices

Medium-density

STM32F103xx devices

High-density

STM32F103xx devices

STM32F105xx STM32F107xx

Flash

size (KB)

RAM

size (KB)

144 pins

100 pins

64 pins

48 pins

36 pins

1. Ports F and G are not available in devices delivered in 100-pin packages.

16 32 32 64 128 256 384 512 64 128 256 128 256

610 10 202048646420326448 64

5 × USARTs

2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I
USB, CAN,
1 × PWM timer
2 × ADCs

2

C,

2 × USARTs
2 × 16-bit
timers
1 × SPI,

2

1 × I

C,
USB, CAN,
1 × PWM
timer
2 × ADCs

3 × USARTs
3 × 16-bit
timers
2 × SPIs,

2

2 × I

Cs, USB,
CAN,
1 × PWM timer
2 × ADCs

4 × 16-bit timers,
2 × basic timers, 3 × SPIs,

2

2 × I

Ss, 2 × I2Cs, USB,
CAN, 2 × PWM timers
3 × ADCs, 1 × DAC,
1 × SDIO, FSMC (100­and 144-pin packages

5 × USARTs,
4 × 16-bit timers,
2 × basic timers, 3 × SPIs,

2

2 × I

Ss, 2 × I2Cs,
USB OTG FS,
2 × CANs, 1 × PWM timer,

(1)

)

2 × ADCs, 1 × DAC

2.3 Overview

2.3.1 ARM® CortexTM-M3 core with embedded Flash and SRAM

5 × USARTs,
4 × 16-bit timers,
2 × basic timers,
3 × SPIs, 2 × I
2 × I2Cs,
USB OTG FS,
2 × CANs,
1 × PWM timer,
2 × ADCs,
1 × DAC, Ethernet

2

Ss,

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is
compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

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Description STM32F105xx, STM32F107xx

2.3.2 Embedded Flash memory

64 to 256 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

2.3.4 Embedded SRAM

20 to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.

2.3.5 Nested vectored interrupt controller (NVIC)

The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt
controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 20 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

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STM32F105xx, STM32F107xx Description

interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).

A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG
FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency,
the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum
frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed
frequency of the low speed APB domain is 36 MHz. Refer to Figure 50: USB OTG FS +

Ethernet solution on page 87.

The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. In order to achieve audio class performance, an audio crystal can be used. In this
case, the I
96 kHz with less than 0.5% accuracy error. Refer to Figure 51: USB OTG FS + I

2

S master clock can generate all standard sampling frequencies from 8 kHz to

2

S (Audio)

solution on page 87.

To configure the PLLs, please refer to Table 60 on page 88, which provides PLL
configurations according to the application type.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from User Flash

● Boot from System Memory

● Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1, USART2 (remapped), CAN2 (remapped), USB OTG FS in device mode
(DFU: device firmware upgrade) and Ethernet.

2.3.9 Power supply schemes

● V

● V

● V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V

, V

SSA

= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs

DDA

and PLL (minimum voltage to be applied to V
and V

BAT

must be connected to VDD and VSS, respectively.

SSA

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

2.3.10 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

generated when V
than the V

power supply and compares it to the V

DD/VDDA

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

is below a specified threshold, V

DD

drops below the V

DD

pins.

is 2.4 V when the ADC is used). V

DDA

is not present.

DD

POR/PDR

threshold. An interrupt can be

PVD

threshold and/or when VDD/V

PVD

, without the need for an

is higher

DDA

DDA

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Description STM32F105xx, STM32F107xx

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop modes.

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.12 Low-power modes

The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to
achieve the best compromise between low power consumption, short startup time and
available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
OTG FS wakeup.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.13 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to­peripheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I
and advanced control timers TIMx, DAC, I

14/90

2

S and ADC.

2

C, USART, general-purpose, basic

STM32F105xx, STM32F107xx Description

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
V

supply when present or through the V

DD

registers used to store 84 bytes of user application data when V

pin. The backup registers are forty-two 16-bit

BAT

power is not present.

DD

They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.4 Timers and watchdogs

The STM32F105xx and STM32F107xx devices include six general-purpose timers, two
basic timers and two watchdog timers.

Ta bl e 4 compares the features of the general-purpose and basic timers.

Table 4. Timer feature comparison

Timer

TIM1 16-bit

TIMx

(TIM2,

TIM3,
TIM4,

TIM5)

TIM6,

TIM7

Counter

resolution

16-bit

16-bit Up

Counter

type

Up,

down,

up/down

Up,

down,

up/down

Prescaler

factor

Any integer

between 1
and 65536

Any integer

between 1
and 65536

Any integer

between 1
and 65536

2.4.1 Advanced-control timer (TIM1)

The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:

● Input capture

● Output compare

● PWM generation (edge or center-aligned modes)

● One-pulse mode output

DMA request

generation

Ye s 4 Ye s

Ye s 4 N o

Ye s 0 N o

Capture/compare

channels

Complementary

outputs

15/90

Description STM32F105xx, STM32F107xx

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.

2.4.2 General-purpose timers (TIMx)

There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded
in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based
on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent
channels each for input capture/output compare, PWM or one pulse mode output. This
gives up to 16 input captures / output compares / PWMs on the largest packages. They can
work together with the Advanced Control timer via the Timer Link feature for synchronization
or event chaining.

The counter can be frozen in debug mode.

Any of the standard timers can be used to generate PWM outputs. Each of the timers has
independent DMA request generations.

2.4.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.

2.4.4 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.

2.4.5 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

2.4.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

16/90

STM32F105xx, STM32F107xx Description

2.4.7 I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.4.8 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F105xx and STM32F107xx connectivity line embeds three universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and
two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other
available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.

2.4.9 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.4.10 Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
96 kHz are supported. When either or both of the I
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency with less than 0.5% accuracy error owing to the advanced clock
controller (see Section 2.3.7: Clocks and startup).

Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral
interface (SPI)” section of the STM32F10xxx reference manual.

2

S interfaces is/are configured in master

2.4.11 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral not available on STM32F105xx devices.

The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard media-independent
interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx
requires an external physical interface device (PHY) to connect to the physical LAN bus

17/90

Description STM32F105xx, STM32F107xx

(twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many
as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz
(RMII) output from the STM32F107xx.

The STM32F107xx includes the following features:

● Supports 10 and 100 Mbit/s rates

● Dedicated DMA channel

● Tagged MAC frame support (VLAN support)

● Half-duplex (CSMA/CD) and full-duplex operation

● MAC control sublayer (control frames) support

● 32-bit CRC generation and removal

● Several address filtering modes for physical and multicast address (multicast and group

addresses)

● 32-bit status code for each transmitted or received frame

● Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive

FIFO are both 2 Kbytes (512 × 35 bits), that is 4 Kbytes in total

● Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 1.0

with the timestamp comparator connected to the TIM2 trigger input

● Triggers interrupt when system time becomes greater than target time

2.4.12 Controller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total)
are not shared with any other peripheral.

2.4.13 Universal serial bus on-the-go full-speed (USB OTG FS)

The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full­speed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS
peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It
has software-configurable endpoint setting and supports suspend/resume. The USB OTG
full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL
connected to the HSE oscillator. The major features are:

● 1.25 KB of SRAM used exclusively by the endpoints (not shared with any other

peripheral)

● 4 bidirectional endpoints

● HNP/SNP/IP inside (no need for any external resistor)

● for OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

● the SOF output can be used to synchronize the external audio DAC clock in

isochronous mode

● in accordance with the USB 2.0 Specification, the supported transfer speeds are:

– in Host mode: full speed and low speed

– in Device mode: full speed

18/90

STM32F105xx, STM32F107xx Description

2.4.14 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current­capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

I/Os on APB2 with up to 18 MHz toggling speed

2.4.15 ADCs (analog-to-digital converters)

Two 12-bit analog-to-digital converters are embedded into STM32F105xx and
STM32F107xx connectivity line devices and each ADC shares up to 16 external channels,
performing conversions in single-shot or scan modes. In scan mode, automatic conversion
is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

● Simultaneous sample and hold

● Interleaved sample and hold

● Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1)
can be internally connected to the ADC start trigger and injection trigger, respectively, to
allow the application to synchronize A/D conversion and timers.

2.4.16 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.

This dual digital Interface supports the following features:

● two DAC converters: one for each output channel

● 8-bit or 12-bit monotonic output

● left or right data alignment in 12-bit mode

● synchronized update capability

● noise-wave generation

● triangular-wave generation

● dual DAC channel independent or simultaneous conversions

● DMA capability for each channel

● external triggers for conversion

● input voltage reference V

REF+

19/90

Description STM32F105xx, STM32F107xx

Eight DAC trigger inputs are used in the STM32F105xx and STM32F107xx connectivity line
family. The DAC channels are triggered through the timer update outputs that are also
connected to different DMA channels.

2.4.17 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.

< 3.6 V. The temperature sensor is internally

DDA

2.4.18 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.4.19 Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB OTG FS,
Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can
be recorded and then formatted for display on the host computer running debugger
software. TPA hardware is commercially available from common development tool vendors.
It operates with third party debugger software tools.

20/90

PA[1 5:0]

EXT.IT

WWDG

12bit ADC1

16 ADC12_INs
common to
ADC1 & ADC2

JTDI
JTCK /SWCLK
JTMS/SWDIO

JNTRST

JTDO

NRST

VDD = 2 to 3.6 V

80 AF

PB[1 5:0]

PC[15:0 ]

AHB2

CAN1_RX as AF

2x(8x16bi t)

WKUP

GPIO port AP

GPIO port BP

F

max

: 48 / 72 MHz

V

SS

SCL,SDA,SM BAL

I2C2

GP DMA1

TIM2

TIM3

XT

AL osc

3-25 MHz

XTAL 32kH z

OSC_IN
OSC_OUTC_O

OSC32_OUT

OSC32_IN

APB1 : F

max

=24 / 36 MHz

HCLK

MANAGT

as AF

Flash 256 KB

Voltage reg.

3.3 V to 1.8 V

V

DD18

Power

Backup interface

as AF

TIM4

Bus Matrix

64 bit

Int erfa ce

RTC

RC HS

Cortex-M3 CPU

Ibus

Dbus

obl

Flashl

SRAM 512B

USART1

USART2

SPI2 / I2S2

bxCAN1 dev ice

7 ch ann els

Back up
register

4 Channels

TIM1

4 compl. Channels

SCL,SDA,SMBAL

I2C1

as AF

RX,TX, CTS, RTS,

USART3

Temp se nsor

PD[15:0 ]

PE[15:0 ]

BKIN, ETR input as AF

4 Channe ls , ETR

4 Channe ls , ETR

4 Channe ls , ETR

FCLK

RC LS

Standby

IWDG

@V

DD

@V

BAT

POR / PDR

Supply

supervision

@V

DDA

V

DDA

V

SSA

@VDDA

V

BAT

=1.8 V to 3.6 V

CK as A F

RX,TX, CTS, RTS,
CK as AF

RX,TX, CTS, RTS,
CK as AF

APB2 : F

max

=48 / 72 MHz

NVIC

SPI1

MOSI,MISO,

SCK,NSS as AF

12bit ADC2

IF

IF

interface

PVD

Reset

Int

@V

DD

AHB2

APB2

APB1

AWU

POR

TAMPER-RTC/
ALARM/SECOND OUT

System

2x(8x16bi t)

SPI3 / I2S3

UART4

RX,TX as AF

UART5

RX,TX as AF

TIM5

4 Channel s, ETR

Reset &
clock
control

12bit DAC1

IFIF

IF

12bit DAC 2

@VDDA

USB OTG FS

SOF

VBUS

ID

DM

DP

SRAM

64 KB

GP DMA2

5 ch ann els

TIM6

TIM7

CAN1_TX as AF

SW/JTAG

TPIU

ETM

Trac e/Tri g

TRACECLK

TRACED[ 0:3]

as AF

as AF

as AF

as AF

as AF

Ethernet MAC

10/100

SRAM 1.25KB

DPRAM 2KB DPRAM 2KB

MII_TXD[3:0]/RMII_TXD[1:0]

MII_TX_CLK/RMII_TX_CLK

MII_TX_EN/RMII_TX_EN

MII_RXD[3:0]/RMII_RXD[1:0]

MII_RX_ER/RMII_RX_ER

MII_RX_CLK/RMII_REF_CLK

MII_RX_DV/RMII_CRS_DV

MII_CRS

MII_COL/RMII_COL

MDC

MDIO

PPS_OUT

bxCA N2 device

CAN2_RX as AF

CAN2_TX as AF

ai15411

DAC_OUT1 as AF

DAC_OUT2 as AF

@V

DDA

PLL1

GPIO port C

GPIO port D

GPIO port E

V

REF+

V

REF–

V

REF+

MOSI/SD, MISO, MCK,
SCK/CK, NSS/WS as AF

MOSI/SD, MISO, MCK,
SCK/CK, NSS/WS as AF

PCLK1
PCLK2

PLL2

PLL3

STM32F105xx, STM32F107xx Description

Figure 1. STM32F105xx and STM32F107xx connectivity line block diagram

1. TA = –40 °C to +85 °C (suffix 6, see Table 59) or –40 °C to +105 °C (suffix 7, see Table 59), junction temperature up to
105 °C or 125 °C, respectively.

2. AF = alternate function on I/O port pin.

21/90

Pin descriptions STM32F105xx, STM32F107xx

100

9998979695949392919089888786858483828180797877

76

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VDD_2
VSS_2
NC
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

VDD_1

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

26272829303132333435363738394041424344454647484950

PE2
PE3
PE4
PE5
PE6

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

OSC_IN

OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VREF-

VREF+

VDDA

PA 0- W K UP

PA 1
PA 2

ai14391

LQFP100

3 Pin descriptions

Figure 2. STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout

22/90

STM32F105xx, STM32F107xx Pin descriptions

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47
46

45
44
43

42

41

40

39

38

37

36

35

34

33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1

2
3

4

5
6

7

8

9

10
11
12

13

14
15

16

V

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

PC0
PC1
PC2
PC3

V

SSA

V

DDA

PA 0- W K UP

PA 1
PA 2

V

DD_3

V

SS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA 1 5

PA 14

V

DD_2

V

SS_2

PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12

PA 3

V

SS_4

V

DD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

V

SS_1

V

DD_1

LQFP64

ai14392

Figure 3. STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout

23/90

Pin descriptions STM32F105xx, STM32F107xx

AI16001c

PE10

PC14-

OSC32_IN

PC5PA5

PC3

PB4

PE15

PB2

PC4PA4

H

PE14

PE11PE7

D PD4

PD3

PB8PE3

C

PD0

PC12

PE5

PB5

PC0

PE2

B PC11PD2

PC15-

OSC32_OUT

PB7

PB6

A

87654321

V

SS_5

OSC_IN

OSC_OUT V

DD_5

G

F

E

PC1

V

REF–

PC13-

TAMPER-RTC

PB9

PA15

PB3

PE4

PE1

PE0

V

SS_1

PD1PE6NRST

PC2

V

SS_3

V

SS_4

NCV

DD_3

V

DD_4

PB15

V

BAT

PD5

PD6

BOOT0 PD7

V

SS_2

V

SSA

PA1

V

DD_2

V

DD_1

PB14

PA0-WKUP

109

K

J

PD10

PD11

PA8

PA9

PA10

PA11

PA12

PC10

PA13

PA14

PC9

PC7

PC6

PD15

PC8

PD14

PE12

PB1PA7

PB11

PE8

PB0PA6

PB10

PE13PE9V

DDA

PB13

V

REF+

PA3

PB12

PA2

PD8

PD9 PD13

PD12

Figure 4. STM32F105xxx and STM32F107xxx connectivity line BGA100 ballout

24/90

STM32F105xx, STM32F107xx Pin descriptions

Table 5. Pin definitions

Pins

BGA100

A3 - 1 PE2 I/O

B3 - 2 PE3 I/O

C3 - 3 PE4 I/O

D3 - 4 PE5 I/O

E3 - 5 PE6 I/O

B2 1 6 V

A2 2 7

A1 3 8

B1 4 9

C2 - 10 V

D2 - 11 V

LQFP64

LQFP100

PC13-TAMPER-

OSC32_OUT

Pin name

BAT

(4)

RTC

PC14-

OSC32_IN

PC15-

SS_5

DD_5

(2)

(1)

Typ e

function

(after reset)

I / O Level

FT

FT

FT

FT

FT

SV

I/O PC13

I/O PC14

(4)

I/O PC15

(4)

SV

SV

Main

(3)

Default Remap

PE2 TRACECK

PE3 TRACED0

PE4 TRACED1

PE5 TRACED2

PE6 TRACED3

BAT

(5)

(5)

(5)

SS_5

DD_5

TAMPER-RTC

OSC32_IN

OSC32_OUT

Alternate functions

C1 5 12 OSC_IN I OSC_IN

D1 6 13 OSC_OUT O OSC_OUT

E1 7 14 NRST I/O NRST

F1 8 15 PC0 I/O PC0 ADC12_IN10

F2 9 16 PC1 I/O PC1

ADC12_IN11/ ETH_MII_MDC/

ETH_RMII_MDC

E2 10 17 PC2 I/O PC2 ADC12_IN12/ ETH_MII_TXD2

F3 11 18 PC3 I/O PC3

G1 12 19 V

H1 - 20 V

J1 - 21 V

K1 13 22 V

SSA

REF-

REF+

DDA

SV

SV

SV

SV

SSA

REF-

REF+

DDA

G2 14 23 PA0-WKUP I/O PA0

ADC12_IN0/TIM2_CH1_ETR

ADC12_IN13/

ETH_MII_TX_CLK

WKUP/USART2_CTS

TIM5_CH1/

(6)

ETH_MII_CRS_WKUP

(6)

/ ADC12_IN1/

(6)

H 2 15 2 4 PA 1 I / O PA 1

USART2_RTS

TIM5_CH2 /TIM2_CH2

ETH_MII_RX_CLK/

ETH_RMII_REF_CLK

/

25/90

Pin descriptions STM32F105xx, STM32F107xx

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

Pin name

LQFP100

(2)

(1)

Typ e

Main

function

(after reset)

I / O Level

J 2 1 6 25 PA 2 I / O PA2

(3)

USART2_TX

TIM5_CH3/ADC12_IN2/

TIM2_CH3

Alternate functions

Default Remap

(6)

/

(6)

/ ETH_MII_MDIO/

ETH_RMII_MDIO

(6)

/

/ ETH_MII_COL

(6)

/DAC_OUT1

(6)

ADC12_IN4

(6)

(6)

/ADC12_IN6

(6)

(6)

/ADC12_IN7

(6)

/

TIM1_BKIN

TIM1_CH1N

K 2 1 7 2 6 PA 3 I / O PA 3

E4 18 27 V

F4 19 28 V

SS_4

DD_4

SV

SV

SS_4

DD_4

G 3 2 0 2 9 PA 4 I /O PA 4

H 3 2 1 3 0 PA 5 I / O PA5

J 3 2 2 31 PA 6 I / O PA6

K 3 2 3 32 PA 7 I /O PA 7

USART2_RX

TIM5_CH4/ADC12_IN3

TIM2_CH4

(6)

SPI1_NSS

USART2_CK

SPI1_SCK

DAC_OUT2 ADC12_IN5

SPI1_MISO

TIM3_CH1

SPI1_MOSI

TIM3_CH2

ETH_MII_RX_DV/

ETH_RMII_CRS_DV

ADC12_IN14/

G4 24 33 PC4 I/O PC4

ETH_MII_RXD0/

ETH_RMII_RXD0

ADC12_IN15/

H4 25 34 PC5 I/O PC5

ETH_MII_RXD1/

ETH_RMII_RXD1

J4 26 35 PB0 I/O PB0

K4 27 36 PB1 I/O PB1

G5 28 37

PB2 I/O FT PB2/BOOT1

ADC12_IN8/TIM3_CH3/

ETH_MII_RXD2

ADC12_IN9/TIM3_CH4

ETH_MII_RXD3

(6)

TIM1_CH2N

/

TIM1_CH3N

H5 - 38 PE7 I/O FT PE7 TIM1_ETR

J5 - 39 PE8 I/O FT PE8 TIM1_CH1N

K5 - 40 PE9 I/O FT PE9 TIM1_CH1

--- V

--- V

SS_7

DD_7

S

S

G6 - 41 PE10 I/O FT PE10 TIM1_CH2N

H6 - 42 PE11 I/O FT PE11 TIM1_CH2

J6 - 43 PE12 I/O FT PE12 TIM1_CH3N

26/90

STM32F105xx, STM32F107xx Pin descriptions

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

LQFP100

Pin name

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

Alternate functions

Default Remap

K6 - 44 PE13 I/O FT PE13 TIM1_CH3

G7 - 45 PE14 I/O FT PE14 TIM1_CH4

H7 - 46 PE15 I/O FT PE15 TIM1_BKIN

J7 29 47 PB10 I/O FT PB10

K7 30 48 PB11 I/O FT PB11

I2C2_SCL/USART3_TX

ETH_MII_RX_ER

I2C2_SDA/USART3_RX

ETH_MII_TX_EN/

(6)

(6)

/

TIM2_CH3

/

TIM2_CH4

ETH_RMII_TX_EN

E7 31 49 V

F7 32 50 V

SS_1

DD_1

K8 33 51 PB12 I/O FT PB12

SV

SV

SS_1

DD_1

SPI2_NSS/I2S2_WS/

I2C2_SMBAL// USART3_CK

TIM1_BKIN

(6)

/CAN2_RX/

(6)

/

ETH_MII_TXD0/

ETH_RMII_TXD0

J8 34 52 PB13 I/O FT PB13

SPI2_SCK/I2S2_CK

USART3_CTS

TIM1_CH1N/CAN2_TX/

(6)

/

ETH_MII_TXD1/

ETH_RMII_TXD1

H8 35 53 PB14 I/O FT PB14

G8 36 54 PB15 I/O FT PB15

K9 - 55 PD8 I/O FT PD8

J9 - 56 PD9 I/O FT PD9

H9 - 57 PD10 I/O FT PD10

G9 - 58 PD11 I/O FT PD11

SPI2_MISO/TIM1_CH2N

USART3_RTS

SPI2_MOSI/I2S2_SD

TIM1_CH3N

(6)

(6)

USART3_TX/

ETH_MII_RX_DV

USART3_RX/

ETH_MII_RX_D0

USART3_CK/

ETH_MII_RX_D1

USART3_CTS/

ETH_MII_RX_D2

TIM4_CH1 /

K10 - 59 PD12 I/O FT PD12

USART3_RTS/

ETH_MII_RX_D3

J10 - 60 PD13 I/O FT PD13 TIM4_CH2

H10 - 61 PD14 I/O FT PD14 TIM4_CH3

G10 - 62 PD15 I/O FT PD15 TIM4_CH4

F10 37 63 PC6 I/O FT PC6 I2S2_MCK/ TIM3_CH1

27/90

Pin descriptions STM32F105xx, STM32F107xx

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

LQFP100

Pin name

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

Alternate functions

Default Remap

E10 38 64 PC7 I/O FT PC7 I2S3_MCK/ TIM3_CH2

F9 39 65 PC8 I/O FT PC8 TIM3_CH3

E9 40 66 PC9 I/O FT PC9 TIM3_CH4

D 9 4 1 6 7 PA 8 I / O FT PA 8

C 9 4 2 6 8 PA 9 I / O FT PA 9

D10 43 69 PA10 I/O FT PA10

C10 44 70 PA11 I/O FT PA11

B10 45 71 PA12 I/O FT PA12

A10 46 72 PA13 I/O FT JTMS-SWDIO

USART1_CK/OTG_FS_SOF

TIM1_CH1

USART1_TX

(6)

/MCO

(6)

/ TIM1_CH2

OTG_FS_VBUS

USART1_RX

TIM1_CH3

USART1_CTS/CAN1_RX

TIM1_CH4

USART1_RTS/OTG_FS_DP

CAN1_TX

(6)

(6)

(6)

(6)

/

/OTG_FS_ID

/OTG_FS_DM

/TIM1_ETR

(6)

(6)

/

PA 1 3

F8 - 73 Not connected

E6 47 74

F6 48 75

A9 49 76

A8 50 77

B9 51 78

B8 52 79

C8 53 80

D8 5 81

E8 6 82

B7 54 83

C7 - 84

D7 - 85

B6 - 86

C6 - 87

D6 - 88

A7 55 89

V

V

SS_2

DD_2

SV

SV

SS_2

DD_2

PA14 I/O FT JTCK-SWCLK PA14

PA15 I/O FT JTDI SPI3_NSS/

PC10 I/O FT PC10 UART4_TX

PC11 I/O FT PC11 UART4_RX

PC12 I/O FT PC12 UART5_TX

PD0 I/O FT OSC_IN

PD1 I/O FT OSC_OUT

(7)

(7)

TIM2_CH1_ETR

SPI1_NSS

USART3_TX/ SPI3_SCK

USART3_RX/

SPI3_MISO

USART3_CK/

SPI3_MOSI

CAN1_RX

CAN1_TX

PD2 I/O FT PD2 TIM3_ETR/UART5_RX

PD3 I/O FT PD3

PD4 I/O FT PD4

PD5 I/O FT PD5

PD6 I/O FT PD6

PD7 I/O FT PD7

PB3 I/O FT JTDO SPI3_SCK

USART2_CTS

USART2_RTS

USART2_TX

USART2_RX

USART2_CK

PB3 / TRACESWO/

TIM2_CH2 / SPI1_SCK

/ PA15

28/90

STM32F105xx, STM32F107xx Pin descriptions

Table 5. Pin definitions (continued)

Pins

LQFP64

BGA100

A6 56 90

Pin name

LQFP100

PB4 I/O FT JNTRST SPI3_MISO

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O Level

I2C1_SMBAl/ SPI3_MOSI/

C5 57 91 PB5 I/O PB5

ETH_MII_PPS_OUT/

ETH_RMII_PPS_OUT

B5 58 92 PB6 I/O FT PB6 I2C1_SCL

A5 59 93 PB7 I/O FT PB7 I2C1_SDA

Alternate functions

Default Remap

TIM3_CH1/

PB4 /

SPI1_MISO

TIM3_CH2/SPI1_MOSI/

CAN2_RX

(6)

/TIM4_CH1

(6)

/TIM4_CH2

(6)

USART1_TX/CAN2_TX

(6)

USART1_RX

D5 60 94 BOOT0 I BOOT0

B4 61 95 PB8 I/O FT PB8 TIM4_CH3

A4 62 96 PB9 I/O FT PB9 TIM4_CH4

(6)

/ ETH_MII_TXD3 I2C1_SCL/CAN1_RX

(6)

I2C1_SDA / CAN1_TX

D4 - 97 PE0 I/O FT PE0 TIM4_ETR

C4 - 98 PE1 I/O FT PE1

E5 63 99 V

F5 64 100 V

1. I = input, O = output, S = supply, HiZ = high impedance.

2. FT = 5 V tolerant.

3. Function availability depends on the chosen device.

4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in output mode is limited: they can be used
only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time.

5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.

6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.

7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and BGA100 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual.

SS_3

DD_3

SV

SV

SS_3

DD_3

29/90

Memory mapping STM32F105xx, STM32F107xx

512-Mbyte

block 7

Cortex-M3's

internal

peripherals

512-Mbyte

block 6

Not used

512-Mbyte

block 5

Not used

512-Mbyte

block 4

Not used

512-Mbyte

block 3

Not used

512-Mbyte

block 2

Peripherals

512-Mbyte

block 1

SRAM

0x0000 0000

0x1FFF FFFF

0x2000 0000

0x3FFF FFFF

0x4000 0000

0x5FFF FFFF

0x6000 0000

0x7FFF FFFF

0x8000 0000

0xAFFF FFFF

0xB000 0000

0xBFFF FFFF

0xC000 0000

0xDFFF FFFF

0xE000 0000

0xFFFF FFFF

512-Mbyte

block 0

Code

Flash

0x0804 0000

0x1FFF 7FFF

0x1FFF 8000 - 0x1FFF F7FF

0x0800 0000

0x0803 FFFF

0x0008 0000

0x07FF FFFF

0x0000 0000

0x0007 FFFF

System memory

Reserved

Reserved

Aliased to Flash or system

memory depending on

BOOT pins

SRAM (aliased
by bit-banding)

Reserved

0x2000 0000

0x2000 FFFF

0x2001 0000

0x3FFF FFFF

RTC

WWDG

0x4000 2800 - 0x4000 2BFF

IWDG

Reserved

SPI2/I2S2

SPI3/I2S1

Reserved

0x4000 2C00 - 0x4000 2FFF

0x4000 3000 - 0x4000 33FF

0x4000 3400 - 0x4000 37FF

0x4000 3800 - 0x4000 3BFF

0x4000 3C00 - 0x4000 3FFF

0x4000 4000 - 0x4000 43FF

USART2

0x4000 4400 - 0x4000 47FF

USART3

0x4000 4800 - 0x4000 4BFF

UART4

0x4000 4C00 - 0x4000 4FFF

UART5

0x4000 5000 - 0x4000 53FF

I2C1

0x4000 5400 - 0x4000 57FF

I2C2

0x4000 5800 - 0x4000 5BFF

Reserved

0x4000 5C00 - 0x4000 63FF

0x4000 6400 - 0x4000 67FF

bxCAN1

bxCAN2

0x4000 6800 - 0x4000 6BFF

BKP

0x4000 6C00 - 0x4000 6FFF

PWR

0x4000 7000 - 0x4000 73FF

DAC

0x4000 7400 - 0x4000 77FF

AFIO 0x4001 0000 - 0x4001 3FFF

EXTI 0x4001 0400 - 0x4001 07FF

Por t A

0x4001 0800 - 0x4001 0BFF

Port B 0x4001 0C00 - 0x4001 0FFF

Por t C

0x4001 1000 - 0x4001 13FF

Por t D

0x4001 1400 - 0x4001 17FF

Por t E

0x4001 1800 - 0x4001 1BFF

Reserved

0x4001 1C00 - 0x4001 23FF

ADC1

0x4001 2400 - 0x4001 27FF

ADC2

0x4001 2800 - 0x4001 2BFF

TIM1

0x4001 2C00 - 0x4001 2FFF

SPI1

0x4001 3000 - 0x4001 33FF

Reserved 0x4001 3400 - 0x4001 37FF

USART1 0x4001 3800 - 0x4001 3BFF

Reserved

0x4001 3C00 - 0x4001 FFFF

DMA2

0x4002 0400 - 0x4002 07FF

Reserved

0x4002 1400 - 0x4002 1FFF

Flash interface

0x4002 2000 - 0x4002 23FF

Reserved

0x4002 2400 - 0x4002 2FFF

CRC

0x4002 3000 - 0x4002 33FF

Reserved

0x4002 3400 - 0x4002 7FFF

Ethernet

0x4002 8000 - 0x4002 9FFF

Reserved

0x4003 0000 - 0x4FFF FFFF

USB OTG FS

0x5000 0000 - 0x5000 03FF

Reserved

0x5000 0400 - 0x5FFF FFFF

ai15412

0x4002 0800 - 0x4002 0FFF

0x4002 1000 - 0x4002 13FF

Reserved

RCC

DMA1

0x4002 0000 - 0x4002 03FF

Reserved

0x4000 7800 - 0x4000 FFFF

APB2

AHB

0x4000 1800 - 0x4000 27FF

0x4000 0800 - 0x4000 0BFF

0x4000 0C00 - 0x4000 0FFF

0x4000 1000 - 0x4000 13FF

0x4000 1400 - 0x4000 17FF

0x4000 0000 - 0x4000 03FF

0x4000 0400 - 0x4000 07FF

Reserved

TIM7

TIM6

TIM5

TIM4

TIM3

TIM2

APB1

Option bytes 0x1FFF F800 - 0x1FFF FFFF

4 Memory mapping

The memory map is shown in Figure 5.

Figure 5. Memory map

30/90

STM32F105xx, STM32F107xx Electrical characteristics

ai15664

C = 50 pF

STM32F10xxx pin

5 Electrical characteristics

5.1 Test conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).

5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2V≤V
tested.

≤3.6 V voltage range). They are given only as design guidelines and are not

DD

= 25 °C and TA = TAmax (given by

A

Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 6.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 7.

Figure 6. Pin loading conditions Figure 7. Pin input voltage

(mean±2Σ).

STM32F10xxx pin

V

IN

ai15665

31/90

Electrical characteristics STM32F105xx, STM32F107xx

ai14125d

V

DD

1/2/3/4/5

Analo g:

RCs, PLL,

...

Power switch

V

BAT

GP I/O s

OUT

IN

Kernel logic

(CPU,
Digital

& Memories)

Backup circuitry

(OSC32K,RTC,

Backup registers)

Wake-up logic

5 × 100 nF
+ 1 × 4.7 µF

1.8-3.6V

Regulator

V

SS

1/2/3/4/5

V

DDA

V

REF+

V

REF-

V

SSA

ADC

Level shifter

IO

Logic

V

DD

10 nF

+ 1 µF

V

REF

10 nF

+ 1 µF

V

DD

ai14126

V

BAT

V

DD

V

DDA

IDD_V

BAT

I

DD

5.1.6 Power supply scheme

Figure 8. Power supply scheme

Caution: In Figure 8, the 4.7 µF capacitor must be connected to V

5.1.7 Current consumption measurement

Figure 9. Current consumption measurement scheme

DD3

.

32/90

STM32F105xx, STM32F107xx Electrical characteristics

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics,

Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

Table 6. Voltage characteristics

Symbol Ratings Min Max Unit

VDD–V

External main supply voltage (including V

SS

and VDD)

(1)

Input voltage on five volt tolerant pin

V

IN

|ΔV

DDx

− VSS| Variations between all the different ground pins 50

|V

SSX

V

ESD(HBM)

1. All main power (VDD, V
supply, in the permitted range.

2. I

INJ(PIN)

maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the I
induced by V

Table 7. Current characteristics

Input voltage on any other pin

| Variations between different VDD power pins 50

Electrostatic discharge voltage (human body
model)

) and ground (VSS, V

DDA

must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN

value. A positive injection is induced by VIN> VINmax while a negative injection is

INJ(PIN)

< VSS.

IN

(2)

) pins must always be connected to the external power

SSA

(2)

DDA

–0.3 4.0

V

− 0.3 +5.5

SS

VSS − 0.3 VDD+0.3

see Section 5.3.11:

Absolute maximum ratings
(electrical sensitivity)

Symbol Ratings Max. Unit

(1)

(1)

150

150

I

VDD

I

VSS

Total current into VDD/V

Total current out of V

SS

power lines (source)

DDA

ground lines (sink)

Output current sunk by any I/O and control pin 25

I

IO

Output current source by any I/Os and control pin − 25

Injected current on NRST pin ± 5

(2)(3)

I

INJ(PIN)

ΣI

INJ(PIN)

1. All main power (VDD, V
supply, in the permitted range.

2. I

3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC

4. When several inputs are submitted to a current injection, the maximum ΣI

must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

INJ(PIN)

cannot be respected, the injection current must be limited externally to the I
injection is induced by V

characteristics.

positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣI

Injected current on HSE OSC_IN and LSE OSC_IN pins ± 5

Injected current on any other pin

(2)

Total injected current (sum of all I/O and control pins)

) and ground (VSS, V

DDA

> VDD while a negative injection is induced by V

IN

maximum current injection on four I/O port pins of the device.

INJ(PIN)

(4)

(4)

) pins must always be connected to the external power

SSA

INJ(PIN)

< VSS.

IN

INJ(PIN)

± 5

± 25

value. A positive

is the absolute sum of the

V

mV

mA

33/90

Electrical characteristics STM32F105xx, STM32F107xx

Table 8. Thermal characteristics

Symbol Ratings Value Unit

T

STG

T

J

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

5.3 Operating conditions

5.3.1 General operating conditions

Table 9. General operating conditions

Symbol Parameter Conditions Min Max Unit

f

HCLK

PCLK1

f

PCLK2

V

V

DDA

V

P

DD

BAT

T

D

A

Internal AHB clock frequency 0 72

Internal APB1 clock frequency 0 36

Internal APB2 clock frequency 0 72

Standard operating voltage 2 3.6 V

Analog operating voltage
(ADC not used)

(1)

Analog operating voltage
(ADC used)

Backup operating voltage 1.8 3.6 V

Power dissipation at T
for suffix 6 or TA = 105 °C for

(3)

suffix 7

= 85 °C

A

Ambient temperature for 6
suffix version

Ambient temperature for 7
suffix version

Must be the same potential

(2)

as V

DD

2.4 3.6

LFBGA100 487

LQFP100 434

LQFP64 444

LQFP48 363

VFQFPN36 1110

Maximum power dissipation –40 85

23.6

Low power dissipation

(4)

–40 105

Maximum power dissipation –40 105

Low power dissipation

(4)

–40 125

MHzf

V

mW

°C

°C

T

J Junction temperature range

1. When the ADC is used, refer to Table 50: ADC characteristics.

2. It is recommended to power VDD and V
between V

3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 8: Thermal

characteristics on page 34).

4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see

Table 8: Thermal characteristics on page 34).

DD

and V

can be tolerated during power-up and operation.

DDA

from the same source. A maximum difference of 300 mV

DDA

34/90

6 suffix version –40 105

°C

7 suffix version –40 125

STM32F105xx, STM32F107xx Electrical characteristics

5.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

Table 10. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

t

VDD

fall time rate 20 ∞

V

DD

5.3.3 Embedded reset and power control block characteristics

The parameters given in Tab l e 1 1 are derived from tests performed under ambient

VDD rise time rate 0 ∞

temperature and V

Table 11. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

PVD

supply voltage conditions summarized in Tab l e 9 .

DD

PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V

PLS[2:0]=000 (falling edge) 2 2.08 2.16 V

PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V

PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V

PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V

PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V

PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V

Programmable voltage
detector level selection

PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V

PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V

µs/V

PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V

PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V

PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V

PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V

PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V

PLS[2:0]=111 (rising edge) 2.76 2.88 3 V

PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V

(2)

V

PVDhyst

V

POR/PDR

V

PDRhyst

T

RSTTEMPO

1. The product behavior is guaranteed by design down to the minimum V

2. Guaranteed by design, not tested in production.

PVD hysteresis 100 mV

Power on/power down
reset threshold

(2)

PDR hysteresis 40 mV

(2)

Reset temporization 1 2.5 4.5 ms

Falling edge

Rising edge 1.84 1.92 2.0 V

35/90

POR/PDR

(1)

1.8

value.

1.88 1.96 V

Electrical characteristics STM32F105xx, STM32F107xx

5.3.4 Embedded reference voltage

The parameters given in Tab l e 1 2 are derived from tests performed under ambient
temperature and V

Table 12. Embedded internal reference voltage

Symbol Parameter Conditions Min

supply voltage conditions summarized in Tab l e 9 .

DD

Typ

Max Unit

V

REFINT

T

S_vrefint

Internal reference voltage

ADC sampling time when

(1)

reading the internal reference
voltage

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 9: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except when explicitly mentioned

● The Flash memory access time is adjusted to the f

to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)

● Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

The parameters given in Tab l e 1 3, Ta bl e 1 4 and Ta bl e 1 5 are derived from tests performed
under ambient temperature and V

supply voltage conditions summarized in Ta bl e 9 .

DD

–40 °C < T

–40 °C < T

PCLK1

= f

< +105 °C 1.16 1.20 1.26 V

A

< +85 °C 1.16 1.20 1.24 V

A

5.1

17.1

or VSS (no load)

DD

frequency (0 wait state from 0

HCLK

HCLK

/2, f

PCLK2

= f

HCLK

(2)

µs

36/90

STM32F105xx, STM32F107xx Electrical characteristics

Table 13. Maximum current consumption in Run mode, code with data processing

running from Flash

(1)

Max

Symbol Parameter Conditions f

HCLK

= 85 °C TA = 105 °C

T

A

Unit

72 MHz 69 70

48 MHz 50 50.5

External clock

(2)

peripherals enabled

36 MHz 39 39.5

, all

24 MHz 27 28

16 MHz 20 20.5

I

DD

Supply current in
Run mode

8 MHz 11 11.5

mA

72 MHz 37 37.5

48 MHz 28 28.5

External clock

(2)

peripherals disabled

36 MHz 22 22.5

, all

24 MHz 16.5 17

16 MHz 12.5 13

8 MHz 8 8

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f

Table 14. Maximum current consumption in Run mode, code with data processing

HCLK

> 8 MHz.

running from RAM

(1)

Max

Symbol Parameter Conditions f

72 MHz 66 67

48 MHz 43.5 45.5

External clock

(2)

peripherals enabled

36 MHz 33 35

, all

24 MHz 23 24.5

16 MHz 16 18

Supply

I

DD

current in
Run mode

8 MHz 9 10.5

72 MHz 33 33.5

48 MHz 23 23.5

External clock

(2)

peripherals disabled

36 MHz 18 18.5

, all

24 MHz 13 13.5

16 MHz 10 10.5

8 MHz 6 6.5

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

HCLK

T

= 85 °C TA = 105 °C

A

Unit

mA

37/90

Electrical characteristics STM32F105xx, STM32F107xx

0

10

20

30

40

50

60

70

-45 25 70 85 105

8 MHz
16 MHz
24 MHz
36 MHz
48 MHz
72 MHz

0

5

10

15

20

25

30

35

-45 25 70 85 105

Consumption

16 MHz
24 MHz
36 MHz
48 MHz
72 MHz

Figure 10. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

Consumption (mA)

Temperature (°C)

Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

8 MHz

(mA)

Temperature (°C)

38/90

STM32F105xx, STM32F107xx Electrical characteristics

Table 15. Maximum current consumption in Sleep mode, code running from Flash

or RAM

(1)

Max

Symbol Parameter Conditions f

72 MHz 66 67

48 MHz 43.5 45.5

External clock

(2)

peripherals enabled

36 MHz 33 35

, all

24 MHz 23 24.5

16 MHz 16 18

I

DD

Supply current in
Sleep mode

8 MHz 9 10.5

72 MHz 33 33.5

48 MHz 23 23.5

External clock

(2)

peripherals disabled

36 MHz 18 18.5

, all

24 MHz 13 13.5

16 MHz 10 10.5

8 MHz 6 6.5

HCLK

T

= 85 °C TA = 105 °C

A

Unit

mA

1. Based on characterization, tested in production at V

2. External clock is 8 MHz and PLL is on when f

HCLK

max and f

DD

> 8 MHz.

max with peripherals enabled.

HCLK

39/90

Electrical characteristics STM32F105xx, STM32F107xx

0

100

200

300

400

500

600

700

-45257085105

2.4V

2.7V

3.0V

3.3V

3.6V

Table 16. Typical and maximum current consumptions in Stop and Standby modes

Symbol Parameter Conditions

(1)

V

DD/VBAT

= 2.4 V

Typ

VDD/V

BAT

= 3.3 V

Max

TA =

85 °C

Regulator in Run mode, low-speed and
high-speed internal RC oscillators and
high-speed oscillator OFF (no

Supply current in
Stop mode

independent watchdog)

Regulator in Low Power mode, low­speed and high-speed internal RC
oscillators and high-speed oscillator

I

DD

OFF (no independent watchdog)

Low-speed internal RC oscillator and
independent watchdog ON

Supply current in
Standby mode

Low-speed internal RC oscillator ON,
independent watchdog OFF

Low-speed internal RC oscillator and
independent watchdog OFF, low-speed

34.5 35 379 1130

24.5 25 365 1110

33.8--

2.8 3.6 - -

1.9 2.1 5

(2)

oscillator and RTC OFF

I

DD_VBAT

Backup domain
supply current

Low-speed oscillator and RTC ON 1.1 1.4 2

(2)

TA =

105 °C

(2)

6.5

(2)

2.3

Unit

µA

1. Typical values are measured at TA = 25 °C.

2. Based on characterization, not tested in production.

Figure 12. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at different V

Consumption (µA)

values

DD

Temperature (°C)

40/90

STM32F105xx, STM32F107xx Electrical characteristics

0

100

200

300

400

500

600

700

-45257085105

2.4V

2.7V

3.0V

3.3V

3.6V

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

-45257085105

2.4V

2.7V

3.0V

3.3V

3.6V

Figure 13. Current consumption in Stop mode with regulator in Low-power mode versus

temperature at different V

Consumption (µA)

values

DD

Temperature (°C)

Figure 14. Current consumption in Standby mode versus temperature at different V

Consumption (µA)

Temperature (°C)

values

DD

41/90

Electrical characteristics STM32F105xx, STM32F107xx

Typical current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned.

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 48 MHz and 2 wait states above).

● Ambient temperature and V

● Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

f

/4

PCLK2

Table 17. Typical current consumption in Run mode, code with data processing

supply voltage conditions summarized in Tab le 9 .

DD

= f

PCLK1

HCLK

running from Flash

Symbol Parameter Conditions f

External clock

(3)

Supply

I

DD

current in
Run mode

Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
frequency

1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

All peripherals

72 MHz 51 30.5

48 MHz 34.6 20.7

36 MHz 26.6 16.2

24 MHz 18.5 11.4

16 MHz 12.8 8.2

8 MHz 7.2 5

4 MHz 4.2 3.1

2 MHz 2.7 2.1

1 MHz 2 1.7

500 kHz 1.6 1.4

125 kHz 1.3 1.2

64 MHz 45 27

48 MHz 34 20.1

36 MHz 26 15.6

24 MHz 17.9 10.8

16 MHz 12.2 7.6

8 MHz 6.6 4.4

4 MHz 3.6 2.5

2 MHz 2.1 1.5

1 MHz 1.4 1.1

500 kHz 1 0.8

125 kHz 0.7 0.6

> 8 MHz.

HCLK

or VSS (no load).

DD

/4, f

enabled

PCLK

2 = f

(2)

/2, f

HCLK

(1)

Typ

All peripherals

disabled

ADCCLK

=

Unit

mA

mA

42/90

STM32F105xx, STM32F107xx Electrical characteristics

Table 18. Typical current consumption in Sleep mode, code with data processing

code running from Flash or RAM

(1)

Typ

Symbol Parameter Conditions f

72 MHz 29.5 6.4

48 MHz 20 4.6

36 MHz 15.1 3.6

24 MHz 10.4 2.6

16 MHz 7.2 2

External clock

(3)

8 MHz 3.9 1.3

4 MHz 2.6 1.2

2 MHz 1.85 1.15

1 MHz 1.5 1.1

500 kHz 1.3 1.05

Supply

I

DD

current in
Sleep mode

125 kHz 1.2 1.05

64 MHz 25.6 5.1

48 MHz 19.4 4

HCLK

All peripherals

enabled

(2)

All peripherals

disabled

Unit

mA

36 MHz 14.5 3

24 MHz 9.8 2

Running on high
speed internal RC
(HSI), AHB prescaler
used to reduce the
frequency

16 MHz 6.6 1.4

8 MHz 3.3 0.7

4 MHz 2 0.6

2 MHz 1.25 0.55

1 MHz 0.9 0.5

500 kHz 0.7 0.45

125 kHz 0.6 0.45

1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

> 8 MHz.

43/90

Electrical characteristics STM32F105xx, STM32F107xx

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Ta bl e 1 9 . The MCU is placed
under the following conditions:

● all I/O pins are in input mode with a static value at V

● all peripherals are disabled unless otherwise mentioned

● the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

● ambient operating temperature and V

supply voltage conditions summarized in

DD

Ta bl e 6

Table 19. Peripheral current consumption

(1)

Peripheral Typical consumption at 25 °C Unit

TIM2 1.2

TIM3 1.2

TIM4 0.9

SPI2 0.2

APB1

USART2 0.35

USART3 0.35

I2C1 0.39

I2C2 0.39

or VSS (no load)

DD

mA

USB OTG FS 0.65

CAN 0.72

GPIO A 0.47

GPIO B 0.47

GPIO C 0.47

GPIO D 0.47

GPIO E 0.47

APB2

ADC1

ADC2 1.78

TIM1 1.6

SPI1 0.43

USART1 0.85

1. f

2. Specific conditions for ADC: f

= 72 MHz, f

HCLK

in the ADC_CR2 register is set to 1.

APB1

= f

HCLK

(2)

/2, f

HCLK

= f

APB2

HCLK

= 56 MHz, f

1.81

, default prescaler value for each peripheral.

= f

/2, f

= f

APB1

HCLK

APB2

HCLK

, f

ADCCLK

= f

APB2/4

mA

, ADON bit

44/90

STM32F105xx, STM32F107xx Electrical characteristics

5.3.6 External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Tab l e 2 0 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta bl e 9 .

Table 20. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HSE_ext

V

HSEH

V

HSEL

t

w(HSE)

t

w(HSE)

t

r(HSE)

t

f(HSE)

C

in(HSE)

DuCy

I

1. Guaranteed by design, not tested in production.

User external clock source
frequency

(1)

OSC_IN input pin high level voltage 0.7V

OSC_IN input pin low level voltage V

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

Duty cycle 45 55 %

(HSE)

OSC_IN Input leakage current VSS≤VIN≤V

L

(1)

(1)

(1)

DD

0825MHz

DD

SS

16

5pF

V

DD

0.3V

DD

20

±1 µA

Low-speed external user clock generated from an external source

The characteristics given in Tab l e 2 1 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta bl e 9 .

Table 21. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

ns

f

LSE_ext

V

LSEH

V

LSEL

t

w(LSE)

t

w(LSE)

t

r(LSE)

t

f(LSE)

C

in(LSE)

DuCy

I

1. Guaranteed by design, not tested in production.

User External clock source
frequency

(1)

OSC32_IN input pin high level
voltage

OSC32_IN input pin low level
voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN input capacitance

Duty cycle 30 70 %

(LSE)

OSC32_IN Input leakage current VSS≤VIN≤V

L

(1)

(1)

(1)

45/90

DD

0.7V

V

450

32.768 1000 kHz

DD

SS

5pF

V

DD

0.3V

DD

50

±1 µA

V

ns

Electrical characteristics STM32F105xx, STM32F107xx

ai14127b

OS C _I N

External

STM32F10xxx

clock source

V

HSEH

t

f(HSE)

t

W(HSE)

I

L

90%

10%

T

HSE

t

t

r(HSE)

t

W(HSE)

f

HSE_ext

V

HSEL

ai14140c

OSC32_IN

External

STM32F10xxx

clock source

V

LSEH

t

f(LSE)

t

W(LSE)

I

L

90%

10%

T

LSE

t

t

r(LSE)

t

W(LSE)

f

LSE_ext

V

LSEL

Figure 15. High-speed external clock source AC timing diagram

Figure 16. Low-speed external clock source AC timing diagram

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 25 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta bl e 2 2 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

46/90

STM32F105xx, STM32F107xx Electrical characteristics

ai14128b

OSC_OUT

OSC_IN

f

HSE

C

L1

R

F

STM32F10xxx

8 MHz
resonator

Resonator with
integrated capacitors

Bias

controlled

gain

R

EXT

(1)

C

L2

Table 22. HSE 3-25 MHz oscillator characteristics

(1) (2)

Symbol Parameter Conditions Min Typ Max Unit

f

OSC_IN

R

C

C

L2

g

t

SU(HSE

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. For CL1 and C
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and C
capacitance which is the series combination of C
included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.

4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.

5. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

Oscillator frequency 3 25 MHz

Feedback resistor 200 kΩ

F

Recommended load capacitance

L1

versus equivalent serial

(3)

resistance of the crystal (R

i

HSE driving current

2

Oscillator transconductance Startup 25 mA/V

m

(5)

Startup time VDD is stabilized 2 ms

it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.),

L2

are usually the same size. The crystal manufacturer typically specifies a load

L2,

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

(4)

)

S

RS = 30 Ω 30 pF

= 3.3 V, VIN=V

V

DD

SS

with 30 pF load

and CL2. PCB and MCU pin capacitance must be

L1

1mA

Figure 17. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.

EXT

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta bl e 2 3 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

47/90

Electrical characteristics STM32F105xx, STM32F107xx

ai14129b

OSC32_OUT

OSC32_IN

f

LSE

C

L1

R

F

STM32F10xxx

32.768 KHz
resonator

Resonator with
integrated capacitors

Bias

controlled

gain

C

L2

Note: For CL1 and C

it is recommended to use high-quality ceramic capacitors in the 5 pF to

L2

15 pF range selected to match the requirements of the crystal or resonator. C
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C
Load capacitance C
C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C

L

and CL2.

L1

between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of C

to use a resonator with a load capacitance C
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C
then C

Table 23. LSE oscillator characteristics (f

Symbol Parameter Conditions Min Typ Max Unit

t

SU(LSE)

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs above the table.

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with

4. t

= CL2 = 8 pF.

L1

R

C

C

L2

g

small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details

SU(LSE)

kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer

Feedback resistor 5 MΩ

F

Recommended load capacitance

L1

versus equivalent serial

(2)

resistance of the crystal (R

I

LSE driving current V

2

Oscillator Transconductance 5 µA/V

m

(4)

startup time VDD is stabilized 3 s

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768

(3)

)

S

and C

L1

stray

and CL2 (15 pF) it is strongly recommended

L1

≤

7 pF. Never use a resonator with a load

L

= 32.768 kHz)

LSE

= 6 pF, and C

L

(1)

stray

= 2 pF,

RS = 30 kΩ 15 pF

= 3.3 V, V

DD

IN

= V

SS

1.4 µA

are

L2,

where

5.3.7 Internal clock source characteristics

48/90

Figure 18. Typical application with a 32.768 kHz crystal

The parameters given in Tab l e 2 4 are derived from tests performed under ambient
temperature and V

supply voltage conditions summarized in Tab l e 9 .

DD

STM32F105xx, STM32F107xx Electrical characteristics

High-speed internal (HSI) RC oscillator

Table 24. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

(1) (2)

f

ACC

t

su(HSI)

I

DD(HSI)

1. Guaranteed by design, not tested in production.

2. V

Frequency 8 MHz

HSI

= –40 to 105 °C ±1 ±3%

T

A

T

= –10 to 85 °C ±1 ±2.5 %

Accuracy of HSI oscillator

HSI

A

= 0 to 70 °C ±1 ±2.2 %

T

A

= 25 °C ±1 ±2%

T

A

HSI oscillator start up time 1 2 µs

HSI oscillator power
consumption

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

DD

Low-speed internal (LSI) RC oscillator

Table 25. LSI oscillator characteristics

Symbol Parameter

(2)

f

LSI

t

su(LSI)

I

DD(LSI)

= 3 V, TA = –40 to 105 °C unless otherwise specified.

1. V

DD

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Frequency 30 40 60 kHz

(3)

LSI oscillator startup time 85 µs

(3)

LSI oscillator power consumption 0.65 1.2 µA

(1)

Min

80 100 µA

Typ Max Unit

Wakeup time from low-power mode

The wakeup times given in Ta bl e 2 6 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:

● Stop or Standby mode: the clock source is the RC oscillator

● Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V
voltage conditions summarized in Tabl e 9 .

49/90

supply

DD

Electrical characteristics STM32F105xx, STM32F107xx

Table 26. Low-power mode wakeup timings

Symbol Parameter Conditions Typ Unit

(1)

t

WUSLEEP

t

WUSTOP

t

WUSTDBY

1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.

Wakeup from Sleep mode Wakeup on HSI RC clock 1.8 µs

Wakeup from Stop mode
(regulator in run mode)

(1)

Wakeup from Stop mode
(regulator in low power mode)

(1)

Wakeup from Standby mode

HSI RC wakeup time = 2 µs 3.6

HSI RC wakeup time = 2 µs, Regulator
wakeup from LP mode time = 5 µs

HSI RC wakeup time = 2 µs, Regulator
wakeup from power down time = 38 µs

µs

5.4

50 µs

5.3.8 PLL characteristics

The parameters given in Tab l e 2 7 and Ta bl e 2 8 are derived from tests performed under
temperature and V

Table 27. PLL1 characteristics

Symbol Parameter

f

PLL_IN

supply voltage conditions summarized in Tab l e 9 .

DD

Val ue

Unit

PLL input clock

(2)

Min

(1)

Max

(1)

812MHz

Pulse width at high level 30 ns

f

PLL_OUT

f

VCO_OUT

t

LOCK

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f

Table 28. PLL2 and PLL3 characteristics

PLL multiplier output clock 48 72 MHz

PLL VCO output 96 144 MHz

PLL lock time 350 µs

.

PLL_OUT

Val ue

Symbol Parameter

f

PLL input clock

PLL_IN

f

PLL_OUT

f

VCO_OUT

t

LOCK

1. Based on characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f

Pulse width at high level 30 ns

PLL multiplier output clock 40 74 MHz

PLL VCO output 80 148 MHz

PLL lock time 350 µs

PLL_OUT

(2)

.

Min

(1)

Max

(1)

35MHz

Unit

50/90

STM32F105xx, STM32F107xx Electrical characteristics

5.3.9 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 105 °C unless otherwise specified.

Table 29. Flash memory characteristics

Symbol Parameter Conditions Min

(1)

Typ Max

(1)

Unit

t

t

ERASE

16-bit programming time TA = –40 to +105 °C 40 52.5 70 µs

prog

Page (1 KB) erase time TA = –40 to +105 °C 20 40 ms

Mass erase time TA = –40 to +105 °C 20 40 ms

t

ME

Read mode

= 72 MHz with 2 wait

f

HCLK

states, VDD = 3.3 V

I

DD

Supply current

Write / Erase modes
f

= 72 MHz, VDD = 3.3 V

HCLK

Power-down mode / Halt,

= 3.0 to 3.6 V

V

DD

V

1. Guaranteed by design, not tested in production.

Programming voltage 2 3.6 V

prog

Table 30. Flash memory endurance and data retention

Symbol Parameter Conditions

N

t

RET

END

Endurance

Data retention

TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)

1 kcycle

10 kcycles

(2)

at TA = 85 °C

(2)

at TA = 105 °C 10

(2)

at TA = 55 °C 20

Min

30

10

(1)

20 mA

5mA

50 µA

Val ue

Unit

Typ Max

kcycles

Years1 kcycle

1. Based on characterization, not tested in production.

2. Cycling performed over the whole temperature range.

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:

● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.

● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 1000-4-4 standard.

and

DD

51/90

Electrical characteristics STM32F105xx, STM32F107xx

A device reset allows normal operations to be resumed.

The test results are given in Tab l e 3 1. They are based on the EMS levels and classes
defined in application note AN1709.

Table 31. EMS characteristics

Symbol Parameter Conditions

= 3.3 V, TA = +25 °C,

V

V

V

FESD

EFTB

Voltage limits to be applied on any I/O pin to
induce a functional disturbance

Fast transient voltage burst limits to be
applied through 100 pF on VDD and V
pins to induce a functional disturbance

SS

DD

f

= 72 MHz

HCLK

conforms to IEC 1000-4-2

VDD = 3.3 V, TA = +25 °C,
f

= 72 MHz

HCLK

conforms to IEC 1000-4-4

Level/

Class

2B

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counter

● Unexpected reset

● Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.

To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.

52/90

STM32F105xx, STM32F107xx Electrical characteristics

Table 32. EMI characteristics

Symbol Parameter Conditions

Monitored

frequency band

0.1 to 30 MHz 12 12

= 3.3 V, TA = 25 °C,

V

DD

S

EMI

Peak level

LQFP100 package
compliant with SAE J
1752/3

130 MHz to 1GHz 23 29

SAE EMI Level 4 4 -

5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Table 33. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum value

Max vs. [f

HSE/fHCLK

8/48 MHz 8/72 MHz

(1)

]

Unit

dBµV30 to 130 MHz 22 19

Unit

= +25 °C

T

V

ESD(HBM)

Electrostatic discharge
voltage (human body model)

Electrostatic discharge

V

ESD(CDM)

voltage (charge device
model)

1. Based on characterization results, not tested in production.

A

conforming to
JESD22-A114

TA = +25 °C
conforming to
JESD22-C101

2 2000

II 500

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up
performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 34. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class T

= +105 °C conforming to JESD78A II level A

A

V

53/90

Electrical characteristics STM32F105xx, STM32F107xx

5.3.12 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Ta bl e 3 5 are derived from tests
performed under the conditions summarized in Tab l e 9 . All I/Os are CMOS and TTL
compliant.

Table 35. I/O static characteristics

Symbol Parameter Conditions Min Typ

V

Input low level voltage

IL

Standard IO input high level
voltage

V

IH

V

IL

V

IH

V

hys

I

lkg

(1)

IO FT

input high level voltage

Input low level voltage

Input high level voltage 0.65 V

Standard IO Schmitt trigger
voltage hysteresis

IO FT Schmitt trigger voltage
hysteresis

(2)

Input leakage current

(2)

(4)

TTL ports

CMOS ports

V

SS≤VIN≤VDD

Standard I/Os

= 5 V

V

IN

–0.5 0.8

2V

25.5V

–0.5 0.35 V

DD

200 mV

DD

(3)

5% V

I/O FT

Max Unit

DD

VDD+0.5

+0.5

±1

3

DD

V

V

mV

µA

R

R

1. FT = Five-volt tolerant.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable

Weak pull-up equivalent

PU

PD

C

IO

production.

PMOS/NMOS. This MOS/NMOS contribution

(5)

resistor

Weak pull-down equivalent

(5)

resistor

I/O pin capacitance 5 pF

V

= V

IN

SS

V

= V

IN

DD

to the series resistance is minimum (~10% order).

30 40 50 kΩ

30 40 50 kΩ

All I/Os are CMOS and TTL compliant (no software configuration required), their
characteristics consider the most strict CMOS-technology or TTL parameters:

● For V

–if V

–if V

● For V

–if V

–if V

:

IH

is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included

DD

is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included

DD

:

IL

is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included

DD

is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included

DD

54/90

STM32F105xx, STM32F107xx Electrical characteristics

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed V

OL

).

In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:

● The sum of the currents sourced by all the I/Os on V

consumption of the MCU sourced on V
I

(see Ta bl e 7 ).

VDD

● The sum of the currents sunk by all the I/Os on V

consumption of the MCU sunk on V
I

(see Ta bl e 7 ).

VSS

cannot exceed the absolute maximum rating

DD,

cannot exceed the absolute maximum rating

SS

plus the maximum Run

DD,

plus the maximum Run

SS

Output voltage levels

Unless otherwise specified, the parameters given in Ta bl e 3 6 are derived from tests
performed under ambient temperature and V

Ta bl e 9 . All I/Os are CMOS and TTL compliant.

Table 36. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

supply voltage conditions summarized in

DD

Output low level voltage for an I/O pin

(1)

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

OL

V

OH

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of I

2. The IIO current sourced by the device must always respect the absolute maximum rating specified in

Table 7 and the sum of IIO (I/O ports and control pins) must not exceed I

3. Based on characterization data, not tested in production.

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(2)

when 8 pins are sourced at same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(2)

when 8 pins are sourced at same time

Output low level voltage for an I/O pin

(1)(3)

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(2)(3)

when 8 pins are sourced at same time

Output low level voltage for an I/O pin

(1)(3)

when 8 pins are sunk at same time

Output high level voltage for an I/O pin

(2)(3)

when 8 pins are sourced at same time

(I/O ports and control pins) must not exceed I

IO

TTL port

= +8 mA

I

IO

2.7 V < V

< 3.6 V

DD

CMOS port

=+ 8mA

I

IO

2.7 V < V

I

IO

2.7 V < V

I

DD

= +20 mA

DD

= +6 mA

IO

< 3.6 V

< 3.6 V

2 V < VDD < 2.7 V

.

VSS

VDD

–0.4

V

DD

2.4

–1.3

V

DD

–0.4

V

DD

.

0.4

0.4

1.3

0.4

V

V

V

V

55/90

Electrical characteristics STM32F105xx, STM32F107xx

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 19 and

Ta bl e 3 7 , respectively.

Unless otherwise specified, the parameters given in Ta bl e 3 7 are derived from tests
performed under the ambient temperature and V
in Ta bl e 9 .

Table 37. I/O AC characteristics

(1)

supply voltage conditions summarized

DD

MODEx[1:0]

bit value

10

01

11

Symbol Parameter Conditions Min Max Unit

(1)

f

max(IO)out

t

f(IO)out

t

r(IO)out

f

max(IO)out

t

f(IO)out

t

r(IO)out

F

max(IO)out

t

f(IO)out

t

r(IO)out

Maximum frequency

Output high to low
level fall time

Output low to high
level rise time

Maximum frequency

Output high to low
level fall time

Output low to high
level rise time

Maximum frequency

Output high to low
level fall time

Output low to high
level rise time

(2)

CL = 50 pF, V

= 50 pF, V

C

L

(2)

CL = 50 pF, V

= 50 pF, V

C

L

CL = 30 pF, V

(2)

= 50 pF, VDD = 2.7 V to 3.6 V 30 MHz

C

L

= 50 pF, V

C

L

= 30 pF, V

C

L

= 50 pF, V

C

L

CL = 50 pF, V

= 30 pF, V

C

L

CL = 50 pF, V

CL = 50 pF, V

= 2 V to 3.6 V 2 MHz

DD

= 2 V to 3.6 V

DD

= 2 V to 3.6 V 10 MHz

DD

= 2 V to 3.6 V

DD

= 2.7 V to 3.6 V 50 MHz

DD

= 2 V to 2.7 V 20 MHz

DD

= 2.7 V to 3.6 V 5

DD

= 2.7 V to 3.6 V 8

DD

= 2 V to 2.7 V 12

DD

= 2.7 V to 3.6 V 5

DD

= 2.7 V to 3.6 V 8

DD

= 2 V to 2.7 V 12

DD

125

125

25

25

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

Pulse width of

-t

EXTIpw

external signals
detected by the EXTI

10 ns

controller

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 19.

3. Guaranteed by design, not tested in production.

ns

ns

ns

56/90

STM32F105xx, STM32F107xx Electrical characteristics

ai14131

10%

90%

50%

t

r(IO)out

OUTPUT

EXTERNAL

ON 50pF

Maximum fr equency is achieved if (tr + tf) £ 2/3) T and if the duty cycle is (45-55%)

10 %

50%

90%

when loaded by 50pF

T

t

r(IO)out

Figure 19. I/O AC characteristics definition

5.3.13 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R

Unless otherwise specified, the parameters given in Ta bl e 3 8 are derived from tests
performed under the ambient temperature and V
in Ta bl e 9 .

Table 38. NRST pin characteristics

(see Ta bl e 3 5).

PU

supply voltage conditions summarized

DD

Symbol Parameter Conditions Min Typ Max Unit

(1)

V

IL(NRST)

V

IH(NRST)

V

hys(NRST)

R

PU

V

F(NRST)

V

NF(NRST)

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution

to the series resistance must be minimum (~10% order).

NRST Input low level voltage –0.5 0.8

(1)

NRST Input high level voltage 2 VDD+0.5

NRST Schmitt trigger voltage
hysteresis

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse 100 ns

(1)

NRST Input not filtered pulse 300 ns

(2)

V

IN

= V

SS

30 40 50 kΩ

200 mV

V

57/90

Electrical characteristics STM32F105xx, STM32F107xx

ai14132b

STM32F10xxx

R

PU

NRST

(2)

V

DD

FILTER

Internal Reset

0.1 µF

External
reset circuit

(1)

Figure 20. Recommended NRST pin protection

2. The reset network protects the device against parasitic resets.

3. The user must ensure that the level on the NRST pin can go below the V

Table 38. Otherwise the reset will not be taken into account by the device.

max level specified in

IL(NRST)

5.3.14 TIM timer characteristics

The parameters given in Tab l e 3 9 are guaranteed by design.

Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 39. TIMx

(1)

characteristics

Symbol Parameter Conditions Min Max Unit

1

t

res(TIM)

f

EXT

Res

t

COUNTER

Timer resolution time

f

Timer external clock
frequency on CH1 to CH4

Timer resolution 16 bit

TIM

0

f

TIMxCLK

16-bit counter clock period

TIMxCLK

= 72 MHz

= 72 MHz

13.9 ns

f

TIMxCLK

036MHz

1 65536
when internal clock is
selected

f

TIMxCLK

= 72 MHz

0.0139 910 µs

/2

65536 × 65536

t

MAX_COUNT

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

Maximum possible count

f

TIMxCLK

= 72 MHz

59.6 s

t

TIMxCLK

MHz

t

TIMxCLK

t

TIMxCLK

58/90

STM32F105xx, STM32F107xx Electrical characteristics

5.3.15 Communications interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 0 are derived from tests
performed under the ambient temperature, f
conditions summarized in Ta bl e 9 .

2

The STM32F105xx and STM32F107xx
standard I

2

C communication protocol with the following restrictions: the I/O pins SDA and

I

C interface meets the requirements of the

SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V

2

The I

C characteristics are described in Ta b le 4 0 . Refer also to Section 5.3.12: I/O port

characteristics

and SCL)

Table 40. I2C characteristics

Symbol Parameter

for more details on the input/output alternate function characteristics (SDA

.

is disabled, but is still present.

DD

Standard mode I

Min Max Min Max

frequency and VDD supply voltage

PCLK1

2C(1)

Fast mode I2C

(1)(2)

Unit

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

h(STA)

t

su(STA)

t

su(STO)

t

w(STO:STA)

C

Guaranteed by design, not tested in production.

1.

2. f

PCLK1

higher than 4 MHz to achieve the maximum fast mode I

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

3.
period of SCL signal.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the

4.
undefined region of the falling edge of SCL.

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100

SDA data hold time 0

(3)

SDA and SCL rise time 1000 20 + 0.1C

(4)

0

900

300

b

SDA and SCL fall time 300 300

Start condition hold time 4.0 0.6

Repeated Start condition
setup time

4.7 0.6

Stop condition setup time 4.0 0.6 μs

Stop to Start condition time
(bus free)

Capacitive load for each bus

b

line

must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be

4.7 1.3 μs

400 400 pF

2

C frequency.

µs

(3)

ns

µs

59/90

Electrical characteristics STM32F105xx, STM32F107xx

ai14133c

START

SD A

100 Ω

4.7kΩ

I²C bus

4.7kΩ

100 Ω

V

DD

V

DD

STM32F10xxx

SDA

SCL

t

f(SDA)

t

r(SDA)

SCL

t

h(STA)

t

w(SCKH)

t

w(SCKL)

t

su(SDA)

t

r(SCK)

t

f(SCK)

t

h(SDA)

S TART REPEATED

START

t

su(STA)

t

su(STO)

S TOP

t

su(STA:STO)

Figure 21. I2C bus AC waveforms and measurement circuit

Measurement points are done at CMOS levels: 0.3V

1.

Table 41. SCL frequency (f

PCLK1

= 36 MHz.,VDD = 3.3 V)

and 0.7VDD.

DD

(1)(2)

I2C_CCR value

f

(kHz)

SCL

R

= 4.7 kΩ

P

400 0x801E

300 0x8028

200 0x803C

100 0x00B4

50 0x0168

20 0x0384

= External pull-up resistance, f

1. R

P

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.

= I2C speed,

SCL

60/90

STM32F105xx, STM32F107xx Electrical characteristics

I2S - SPI interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 2 for SPI or in Tab l e 4 3 for I2S
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in Ta b le 9 .

frequency and VDD

PCLKx

Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I

Table 42. SPI characteristics

Symbol Parameter Conditions Min Max Unit

f

SCK

1/t

c(SCK)

t

r(SCK)

t

f(SCK)

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

SPI clock frequency

SPI clock rise and fall
time

(2)

NSS setup time Slave mode 4 t

(2)

NSS hold time Slave mode 73

(2)

SCK high and low time

(2)

Data input setup time

(2)

Master mode

Data input setup time

(2)

Slave mode

Data input hold time

(2)

Master mode

(1)

Master mode 0 18

Slave mode 0 18

Capacitive load: C = 30 pF 8

PCLK

Master mode, f
presc = 4

= 36 MHz,

PCLK

50 60

SPI1 1

SPI2 5

1

SPI1 1

SPI2 5

2

S).

MHz

ns

Data input hold time

(2)

t

h(SI)

t

a(SO)

t

dis(SO)

t

v(SO)

t

v(MO)

t

h(SO)

t

h(MO)

1. Remapped SPI1 characteristics to be determined.

2. Based on characterization, not tested in production.

3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.

4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z

Slave mode

Data output access

(2)(3)

Slave mode, f
presc = 4

PCLK

= 36 MHz,

time

Slave mode, f

Data output disable

(2)(4)

time

(2)(1)

Data output valid time Slave mode (after enable edge) 25

(2)(1)

Data output valid time Master mode (after enable edge) 3

(2)

Data output hold time

(2)

Slave mode 10

Slave mode (after enable edge) 25

Master mode (after enable edge) 4

= 24 MHz 0 4 t

PCLK

3

055

PCLK

61/90

Electrical characteristics STM32F105xx, STM32F107xx

ai14134c

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 O UT

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

NSS input

Figure 22. SPI timing diagram - slave mode and CPHA = 0

Figure 23. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

DD

.

(1)

62/90

STM32F105xx, STM32F107xx Electrical characteristics

ai14136

SCK Input

CPHA=0

MOSI

OUTUT

MISO

INP UT

CPHA=0

MSBIN

M SB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

r(SCK)

t

f(SCK)

t

h(MI)

High

SCK Input

CPHA=1

CPHA=1

CPOL=0

CPOL=1

t

su(MI)

t

v(MO)

t

h(MO)

Figure 24. SPI timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

DD

DD

.

63/90

Electrical characteristics STM32F105xx, STM32F107xx

Table 43. I2S characteristics

(1)

Symbol Parameter Conditions Min Max Unit

f

CK

1/t

c(CK)

t

r(CK)

t

f(CK)

(2)

t

v(WS)

(2)

t

h(WS)

(2)

t

su(WS)

(2)

t

h(WS)

(2)

t

w(CKH)

(2)

t

w(CKL)

t

su(SD_MR)

t

su(SD_SR)

t

h(SD_MR)

t

h(SD_SR)

t

h(SD_MR)

t

h(SD_SR)

t

v(SD_ST)

t

h(SD_ST)

t

v(SD_MT)

t

h(SD_MT)

1. TBD = to be determined.

2. Based on design simulation and/or characterization results, not tested in production.

3. Depends on f

I2S clock frequency

I2S clock rise and fall time

WS valid time Master TBD

WS hold time Master TBD

WS setup time Slave TBD

WS hold time Slave TBD

CK high and low time

(2)

Data input setup time

(2)

(2)(3)

Data input hold time

(2)(3)

(2)

Data input hold time

(2)

(2)(3)

Data output valid time

(2)

Data output hold time

(2)(3)

Data output valid time

(2)

Data output hold time

. For example, if f

PCLK

=8 MHz, then T

PCLK

Master TBD TBD

Slave 0 TBD

capacitive load

= 50 pF

C

L

Master f
presc = TBD

Master receiver
Slave receiver

Master receiver
Slave receiver

Master f
Slave f

PCLK

PCLK

PCLK

= TBD,

= TBD

= TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

Slave transmitter
(after enable edge)

= TBD TBD

f

PCLK

Slave transmitter
(after enable edge)

TBD

Master transmitter
(after enable edge)

f

= TBD

PCLK

Master transmitter
(after enable edge)

= 1/f

PCLK

PLCLK

TBD TBD

TBD

=125 ns.

TBD

TBD

TBD

MHz

ns

64/90

STM32F105xx, STM32F107xx Electrical characteristics

CK Input

CPOL = 0

CPOL = 1

t

c(CK)

WS input

SD

transmit

SD

receive

t

w(CKH)

t

w(CKL)

t

su(WS)

t

v(SD_ST)

t

h(SD_ST)

t

h(WS)

t

su(SD_SR)

t

h(SD_SR)

MSB receive Bit1 receive LSB receive

MSB transmit Bitn transmit LSB transmit

ai14881

CK output

CPOL = 0

CPOL = 1

t

c(CK)

WS output

SD

receive

SD

transmit

t

w(CKH)

t

w(CKL)

t

su(SD_MR)

t

v(SD_MT)

t

h(SD_MT)

t

h(WS)

t

h(SD_MR)

MSB transmit Bitn transmit LSB transmit

MSB receive Bitn receive LSB receive

ai14884

t

f(CK)

t

r(CK)

t

v(WS)

(1)

Figure 25. I2S slave timing diagram

1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.

Figure 26. I2S master timing diagram

(1)

1. Based on characterization, not tested in production.

65/90

Electrical characteristics STM32F105xx, STM32F107xx

ai14137

t

f

Differen tial

data lines

V

SS

V

CR S

t

r

Crossover

points

USB OTG FS characteristics

The USB OTG interface is USB-IF certified (Full-Speed).

Table 44. USB OTG FS startup time

Symbol Parameter Max Unit

t

STARTUP

1. Guaranteed by design, not tested in production.

Table 45. USB OTG FS DC electrical characteristics

(1)

USB OTG FS transceiver startup time 1 µs

Symbol Parameter Conditions Min.

(1)

Max.

(1)

Unit

USB OTG FS operating

V

DD

Input

levels

Output

levels

1. All the voltages are measured from the local ground potential.

2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.

3. The STM32F105xx and STM32F107xx USB OTG FS functionality is ensured down to 2.7 V but not the full
USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V V

4. Guaranteed by design, not tested in production.

is the load connected on the USB OTG FS drivers

R

5.

L

(4)

V

DI

(4)

CM

(4)

V

SE

V

OL

V

OH

(2)

voltage

Differential input sensitivity I(USBDP, USBDM) 0.2

Differential common mode range Includes V

range 0.8 2.5

DI

Single ended receiver threshold 1.3 2.0

SS

(5)

(5)

Static output level low RL of 1.5 kΩ to 3.6 V

Static output level high RL of 15 kΩ to V

(3)

3.0

2.8 3.6

voltage range.

DD

3.6 V

0.3

Figure 27. USB OTG FS timings: definition of data signal rise and fall time

VV

V

Table 46. USB OTG FS electrical characteristics

Symbol Parameter Conditions Min Max Unit

t

t

rfm

V

CRS

1. Guaranteed by design, not tested in production.

Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

2.
Specification - Chapter 7 (version 2.0).

Rise time

r

t

Fall time

f

Rise/ fall time matching tr/t

Output signal crossover voltage 1.3 2.0 V

(2)

(2)

66/90

(1)

Driver characteristics

CL = 50 pF

CL = 50 pF 4 20 ns

f

420ns

90 110 %

STM32F105xx, STM32F107xx Electrical characteristics

Ethernet dynamic characteristics

Ta bl e 4 7 gives the list of Ethernet MAC signals for the SMI (station management interface)

and Figure 28 shows the corresponding timing diagram.

Figure 28. Ethernet SMI timing diagram

t

MDC

ETH_MII_MDC/
ETH_RMII_MDC

ETH_MII_MDIO(O)/
ETH_RMII_MDIO(O)

ETH_MII_MDIO(I)
ETH_RMII_MDIO(I)

t

d(MDIO)

t

su(MDIO)

t

tahz(MDIO)

t

h(MDIO)

ai15666

Table 47. Dynamics characteristics: Ethernet MAC signals for SMI

(1)

Symbol Rating Min Typ Max Unit

t

MDC

t

d(MDIO)

t

tahz(MDIO)

t

su(MDIO)

t

h(MDIO)

1. TBD stands for to be determined.

MDC cycle time TBDTBDTBDns

MDIO write data valid time TBD TBD TBD ns

MDC clock rise time to high
impedance (turn around)

TBDTBDTBDns

Read data setup time TBD TBD TBD ns

Read data hold time TBD TBD TBD ns

Ta bl e 4 8 gives the list of Ethernet MAC signals for the RMII and Figure 29 shows the

corresponding timing diagram.

Figure 29. Ethernet RMII timing diagram

RMII_REF_CLK

t

d(TXEN)

t

d(TXD)

RMII_TX_EN
RMII_TXD[1:0]

RMII_RXD[1:0]
RMII_CRS_DV

t

su(RXD)

t

su(CRS)

t

ih(RXD)

t

ih(CRS)

ai15667

67/90

Electrical characteristics STM32F105xx, STM32F107xx

Table 48. Dynamics characteristics: Ethernet MAC signals for RMII

(1)

Symbol Rating Min Typ Max Unit

t

su(RXD)

t

ih(RXD)

t

su(CRS)

t

ih(CRS)

t

d(TXEN)

t

d(TXD)

1. TBD stands for to be determined.

Receive data setup time TBD TBD TBD ns

Receive data hold time TBD TBD TBD ns

Carrier sense set-up time TBD TBD TBD ns

Carrier sense hold time TBD TBD TBD ns

Transmit enable valid delay time TBD TBD TBD ns

Transmit data valid delay time TBD TBD TBD ns

Ta bl e 4 9 gives the list of Ethernet MAC signals for MII and Figure 29 shows the

corresponding timing diagram.

Figure 30. Ethernet MII timing diagram

MII_RX_CLK

MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

t

su(RXD)

t

su(ER)

t

su(DV)

t

ih(RXD)

t

ih(ER)

t

ih(DV)

MII_TX_CLK

t

d(TXEN)

t

d(TXD)

MII_TX_EN
MII_TXD[3:0]

ai15668

Table 49. Dynamics characteristics: Ethernet MAC signals for MII

(1)

Symbol Rating Min Typ Max Unit

t

su(RXD)

t

ih(RXD)

t

su(DV)

t

ih(DV)

t

su(ER)

t

ih(ER)

t

d(TXEN)

t

d(TXD)

1. TBD stands for to be determined.

Receive data setup time TBD TBD TBD ns

Receive data hold time TBD TBD TBD ns

Data valid setup time TBD TBD TBD ns

Data valid hold time TBD TBD TBD ns

Error setup time TBD TBD TBD ns

Error hold time TBD TBD TBD ns

Transmit enable valid delay time TBD TBD TBD ns

Transmit data valid delay time TBD TBD TBD ns

68/90

STM32F105xx, STM32F107xx Electrical characteristics

CAN (controller area network) interface

Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (CANTX and CANRX).

5.3.16 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Ta bl e 5 0 are derived from tests
performed under the ambient temperature, f
conditions summarized in Ta bl e 9 .

Note: It is recommended to perform a calibration after each power-up.

Table 50. ADC characteristics

Symbol Parameter Conditions Min Typ

frequency and V

PCLK2

supply voltage

DDA

Max Unit

V

DDA

V

REF+

I

VREF

f

ADC

f

S

f

TRIG

V

AIN

R

AIN

R

ADC

C

ADC

t

CAL

t

lat

t

latr

t

S

t

STAB

t

CONV

1. Based on characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. V

REF+

4. For external triggers, a delay of 1/f

Power supply 2.4 3.6 V

Positive reference voltage 2.4 V

Current on the V

input pin 160

REF

ADC clock frequency 0.6 14 MHz

(2)

Sampling rate 0.05 1 MHz

(2)

External trigger frequency

Conversion voltage range

(2)

External input impedance See Equation 1 and Ta b le 5 1 kΩ

(2)

Sampling switch resistance 1 kΩ

(2)

Internal sample and hold capacitor 12 pF

(2)

Calibration time

(2)

Injection trigger conversion latency

(2)

Regular trigger conversion latency

(2)

Sampling time

(2)

Power-up tim e 0 0 1 µs

Total conversion time (including

(2)

(3)

sampling time)

is internally connected to V

DDA

PCLK2

and V

is internally connected to V

REF-

must be added to the latency specified in Table 50.

DDA

(1)

f

= 14 MHz 823 kHz

ADC

220

(1)

17 1/f

0 (V

f

= 14 MHz 5.9 µs

ADC

or V

SSA

REF-

tied to ground)

V

REF+

83 1/f

f

= 14 MHz 0.214 µs

ADC

(4)

3

f

= 14 MHz 0.143 µs

ADC

(4)

2

= 14 MHz 0.107 17.1 µs

f

ADC

1.5 239.5 1/f

= 14 MHz 1 18 µs

f

ADC

14 to 252 (t

for sampling +12.5 for

S

successive approximation)

.

SSA

1/f

1/f

1/f

V

µA

ADC

V

ADC

ADC

ADC

ADC

ADC

69/90

Electrical characteristics STM32F105xx, STM32F107xx

R

AIN

T

S

f

ADCCADC

2

N2+

()ln××

--------------------------------------------------------------- - R

ADC

–<

Equation 1: R

max formula:

AIN

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 51. R

Ts (cycles) tS (µs) R

max for f

AIN

= 14 MHz

ADC

(1)

max (kΩ)

AIN

1.5 0.11 1.2

7.5 0.54 10

13.5 0.96 19

28.5 2.04 41

41.5 2.96 60

55.5 3.96 80

71.5 5.11 104

239.5 17.1 350

1. Based on characterization, not tested in production.

Table 52. ADC accuracy - limited test conditions

Symbol Parameter Test conditions Typ Max

(1) (2)

(3)

Unit

ET Total unadjusted error

EO Offset error ±1 ±1.5

EG Gain error ±0.5 ±1.5

ED Differential linearity error ±0.7 ±1

EL Integral linearity error ±0.8 ±1.5

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non­robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
affect the ADC accuracy.

3. Based on characterization, not tested in production.

f

= 56 MHz,

PCLK2

= 14 MHz, R

f

ADC

V

= 3 V to 3.6 V

DDA

= 25 °C

T

A

< 10 kΩ,

AIN

Measurements made after
ADC calibration

and ΣI

INJ(PIN)

±1.3 ±2

in Section 5.3.12 does not

INJ(PIN)

LSB

70/90

STM32F105xx, STM32F107xx Electrical characteristics

E

O

E

G

1LSB

IDEAL

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line

E

T

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

E

O

=Offset Error: deviation between the first actual

transition and the first ideal one.

E

G

=Gain Error: deviation between the last ideal

transition and the last actual one.

E

D

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

E

L

=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.

4095

4094

4093

5

4

3

2

1

0

7

6

1234567

4093 4094 4095 4096

(1)

(2)

E

T

E

D

E

L

(3)

V

DDA

V

SSA

ai14395b

V

REF+

4096

(or depending on package)]

V

DDA

4096

[1LSB

IDEAL =

ai14139d

STM32F10xxx

V

DD

AINx

IL±1 µA

0.6 V

V

T

R

AIN

(1)

C

parasitic

V

AIN

0.6 V

V

T

R

ADC

(1)

C

ADC

(1)

12-bit

converter

Sample and hold ADC
converter

Table 53. ADC accuracy

Symbol Parameter Test conditions Typ Max

ET Total unadjusted error

EO Offset error ±1.5 ±2.5

EG Gain error ±1.5 ±3

ED Differential linearity error ±1 ±2

(1) (2) (3)

f

= 56 MHz,

PCLK2

= 14 MHz, R

f

ADC

V

= 2.4 V to 3.6 V

DDA

< 10 kΩ,

AIN

Measurements made after
ADC calibration

(4)

±2 ±5

EL Integral linearity error ±1.5 ±3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non­robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
affect the ADC accuracy.

, frequency and temperature ranges.

DD

INJ(PIN)

and ΣI

in Section 5.3.12 does not

INJ(PIN)

4. Based on characterization, not tested in production.

Figure 31. ADC accuracy characteristics

Unit

LSB

Figure 32. Typical connection diagram using the ADC

1. Refer to Tab l e 5 0 for the values of R

2. C

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

pad capacitance (roughly 7 pF). A high C
this, f

should be reduced.

ADC

, R

AIN

and C

ADC

parasitic

ADC

value will downgrade conversion accuracy. To remedy

71/90

.

Electrical characteristics STM32F105xx, STM32F107xx

c

c

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 33 or Figure 34,
depending on whether V
ceramic (good quality). They should be placed them as close as possible to the chip.

is connected to V

REF+

or not. The 10 nF capacitors should be

DDA

Figure 33. Power supply and reference decoupling (V

STM32F10xxx

V

REF+

(See note 1)

1. V

REF+

and V

1 µF // 10 nF

1 µF // 10 nF

inputs are available only on 100-pin packages.

REF–

V

DDA

V

SSA/VREF-

(See note 1)

Figure 34. Power supply and reference decoupling (V

not connected to V

REF+

connected to V

REF+

ai14380

DDA

DDA

)

)

1 µF // 10 nF

1. V

REF+

and V

inputs are available only on 100-pin packages.

REF–

72/90

STM32F10xxx

V

REF+/VDDA

(See note 1)

V

REF–/VSSA

(See note 1)

ai14381

STM32F105xx, STM32F107xx Electrical characteristics

5.3.17 DAC electrical specifications

Table 54. DAC characteristics

Symbol Parameter Min Typ Max

V

DD33A

V

DD18D

V

REF+

V

SSA

R

L

C

L

DAC_OUT
min

DAC_OUT
max

(1)

Analog supply voltage 2.4 3.6 V

Digital supply voltage 1.6 1.8 2 V

Reference supply voltage 2.4 3.6 V

Ground 0 0 V

Resistive load with buffer ON 5 kΩ

Capacitive load 50 pF

Lower DAC_OUT voltage with buffer
ON

Higher DAC_OUT voltage with buffer
ON

0.2 V

V

–

REF+

0.2 V

425 600 µA

DAC DC current consumption in

I

DD

quiescent mode (Standby mode) (in
V

DD18D+VDD33A

+ V

REF+

)

500 700 µA

DAC DC current consumption in

5350

5200

±0.5 LSB

I

DDQ

DNL

Power Down mode (in
V

DD18D+VDD33A+VREF+

)

DAC DC current consumption in
Power Down mode (in V

DD33A+VREF+

Differential non linearity (Difference
between two consecutive code-1LSB)

)

Integral non linearity (difference
between measured value at Code i

INL

and the value at Code i on a line

±1 LSB

drawn between Code 0 and last Code

1023)

Offset

Offset error
(difference between measured value

at Code (800)H and the ideal value =

/2

V

REF+

±10 mV

±3 LSB

Gain error Gain error ±0.5 %

Amplifier
gain

Gain of the amplifier in open loop 80 85 dB with a 5 kΩ load (worst case)

Unit Comments

must always be below

V

REF+

V

DD33A

Minimum resistive load between
DAC_OUT and V

SSA

Maximum capacitive load at
DAC_OUT pin.

It gives the maximum output
excursion of the DAC

it corresponds to 12-bit input
code (0E0)h to (F1C)h @ V

V

= 3.6 V and (155)h and (EAB)h

REF+

= 2.4 V

@ V

With no load, middle code
(800)H on the inputs

With no load, worst code (F1C)H
@ V

= 3.6 V in terms of DC

REF+

consumption on the inputs

nA With no load.

Given for the DAC in 10-bit
configuration (B1=B0=0 always)

Given for the DAC in 10-bit
configuration (B1=B0=0 always)

Given for the DAC in 10-bit
configuration (B1=B0=0 always)

Given for the DAC in 10-bit @
V

= 3.6 V

REF+

Given for the DAC in 10-bit
configuration (B1=B0=0 always)

REF+

73/90

Electrical characteristics STM32F105xx, STM32F107xx

Table 54. DAC characteristics (continued)

Symbol Parameter Min Typ Max

Settling time (full scale: for an 10-bit
input code transition between the

t

SETTLING

lowest and the highest input codes

34µs
when DAC_OUT reaches final value
±1LSB

Max frequency for a correct

Update
rate

DAC_OUT change when small
variation in the input code (from code i
to i+1LSB)

t

WAKEUP

PSRR+

1. Guaranteed by characterization, not tested in production.

Wakeup time from off state (PDV18
from 1 to 0)

Power supply rejection ratio (to

) (static DC measurement

V

DD33A

6.5 10 µs

–67 –40 dB No R

(1)

Unit Comments

≤ 50 pF,

C

LOAD

≥ 5 kΩ

R

LOAD

≤ 50 pF,

C

1MS/s

R

C
R

LOAD

LOAD

LOAD

LOAD

≥ 5 kΩ

≤ 50 pF,
≥ 5 kΩ

input code between lowest and
highest possible ones.

LOAD

, C

LOAD

= 50 pF

5.3.18 Temperature sensor characteristics

Table 55. TS characteristics

Symbol Parameter Min Typ Max Unit

(1)

T

L

Avg_Slope

(1)

V

25

(2)

t

START

S_temp

(3)(2)

T

1. Based on characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

V

(1)

Average slope 4.0 4.3 4.6 mV/°C

linearity with temperature

SENSE

±1 ±2

Voltage at 25 °C 1.34 1.43 1.52 V

Startup time 4 10 µs

ADC sampling time when reading the temperature 17.1 µs

°C

74/90

STM32F105xx, STM32F107xx Package characteristics

6 Package characteristics

6.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

75/90

Package characteristics STM32F105xx, STM32F107xx

ai14396

A2 A4 A3 A1 A

Seating plane

B

A1 corner index area

(see note 5)

(100 balls)

Bottom view

12345678910

F

E1

E

e

A

D

D1

e

F

K

J
H
G
F
E
D
C
B
A

ddd

C

C

eee

fff

CA

B

CM

M

∅

∅

b

∅

Figure 35. LFBGA100 - low profile fine pitch ball grid array package outline

Table 56. LFBGA100 - low profile fine pitch ball grid array package mechanical data

A 1.700 0.0026

A1 0.270 0.0004

A2 1.085 0.0017

A3 0.30 0.0005

A4 0.80 0.0012

b 0.45 0.50 0.55 0.0007 0.0008 0.0009

D 9.85 10.00 10.15 0.0153 0.0155 0.0157

D1 7.20 0.0111

E 9.85 10.00 10.15 0.0153 0.0155 0.0157

E1 7.20 0.0111

e 0.80 0.0012

F 1.40 0.0022

ddd 0.12 0.0002

76/90

eee 0.15 0.0002

fff 0.08 0.0001

N (number of balls) 100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Dim.

mm inches

(1)

Min Typ Max Min Typ Max

STM32F105xx, STM32F107xx Package characteristics

Dpad

Dsm

Dpad 0.37 mm

Dsm

0.52 mm typ. (depends on solder

mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended

– 4 to 6 mils screen print

Figure 36. Recommended PCB design rules (0.80/0.75 mm pitch BGA)

77/90

Package characteristics STM32F105xx, STM32F107xx

D

D1

D3

75

51

50

76

100 26

125

E3 E1 E

e

b

Pin 1
identification

SEATING PLANE

GAGE PLANE

C

A

A2

A1

Cccc

0.25 mm

0.10 inch

L

L1

k

C

1L_ME

75 51

5076

0.5

0.3

.3

100 26

12.3

25

1.2

16.7

1

ai14906

Figure 37. LQFP100, 100-pin low-profile quad flat

package outline

(1)

Figure 38. Recommended footprint

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 57. LQPF100 – 100-pin low-profile quad flat package mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

(1)(2)

(1)

A 1.60 0.063

A1 0.05 0.15 0.002 0.0059

A2 1.40 1.35 1.45 0.0551 0.0531 0.0571

b 0.22 0.17 0.27 0.0087 0.0067 0.0106

c 0.09 0.20 0.0035 0.0079

D 16.00 15.80 16.20 0.6299 0.622 0.6378

D1 14.00 13.80 14.20 0.5512 0.5433 0.5591

D3 12.00 0.4724

E 16.00 15.80 16.20 0.6299 0.622 0.6378

E1 14.00 13.80 14.20 0.5512 0.5433 0.5591

E3 12.00 0.4724

e0.50 0.0197

L 0.60 0.45 0.75 0.0236 0.0177 0.0295

L1 1.00 0.0394

k3.5°0° 7°3.5°0° 7°

ccc 0.08 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

78/90

STM32F105xx, STM32F107xx Package characteristics

A

A2

A1

c

L1

L

E

E1

D

D1

e

b

ai14398b

48

3249

64 17

116

1.2

0.3

33

10.3

12.7

10.3

0.5

7.8

12.7

ai14909

Figure 39. LQFP64 – 64 pin low-profile quad flat

package outline

(1)

Figure 40. Recommended footprint

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 58. LQFP64 – 64 pin low-profile quad flat package mechanical data

mm inches

Dim.

Min Typ Max Min Typ Max

(1)(2)

(1)

A 1.60 0.0630

A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 0.20 0.0035 0.0079

D 12.00 0.4724

D1 10.00 0.3937

E 12.00 0.4724

E1 10.00 0.3937

e 0.50 0.0197

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.0177 0.0236 0.0295

L1 1.00 0.0394

Number of pins

N

1. Values in inches are converted from mm and rounded to 4 decimal digits.

64

79/90

Part numbering STM32F105xx, STM32F107xx

7 Part numbering

Table 59. Ordering information scheme

Example: STM32 F 105 R C T 6 xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

105 = connectivity, USB OTG FS
107= connectivity, USB OTG FS & Ethernet

Pin count

R = 64 pins
V = 100 pins

Flash memory size

8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
C = 256 Kbytes of Flash memory

Package

H = BGA
T = LQFP

Temperature range

6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.

Options

xxx = programmed parts
TR = tape and real

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

80/90

STM32F105xx, STM32F107xx Applicative block diagrams

USB
OTG

Full-speed

core

STM32F105xx/STM32F107xx

USB

Full-speed

transceiver

D+

USB Micro-B connector

D–

V

BUS

V

SS

HNPHNP

SRPSRP

V

DD

(1)

IDID

Cortex-M3

OTG PHY

ai15653

D+
D–

V

BUS

V

SS

To host

5 V to V

DD

Regulator

(2)

Appendix A Applicative block diagrams

A.1 USB OTG FS interface solutions

Figure 41. USB OTG FS device mode

1. VDD ranges between 2 V and 3.6 V.

2. Use a regulator if you want to build a bus-powered device.

81/90

Applicative block diagrams STM32F105xx, STM32F107xx

Figure 42. Host connection

STM32F105xx/STM32F107xx

OTG PHY

D+

D–

V

BUS

V

USB Std-A connector

SS

USB
OTG

Full-speed

core

USB
full-speed/
low-speed
transceiver

HNPHNP

IDID

SRPSRP

(2)

V

DD

Cortex-M3

GPIO

GPIO + IRQ

1. ST20x2 needed only if the application has to support bus-powered devices.

ranges between 2 V and 3.6 V.

2. V

DD

EN

OVRCR
flag

Current-limited

power distribution

ST20x2

switch

5 V

(1)

ai15654

82/90

STM32F105xx, STM32F107xx Applicative block diagrams

MCU

Ethernet
MAC 10/100

Ethernet
PHY 10/100

PLL

HCLK

XT1

PHY_CLK 25 MHz

MII_RX_CLK
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER

MII_TX_CLK
MII_TX_EN

MII_TXD[3:0]
MII_CRS
MII_COL

MDIO
MDC

HCLK

(1)

PPS_OUT

(2)

XTAL

25 MHz

STM32F107xx

OSC

TIM2

Timestamp

comparator

Timer
input
trigger

IEEE1588 PTP

MII

= 15 pins

MII + MDC
= 17 pins

ai15656

Figure 43. OTG connection (any protocol)

STM32F105xx/STM32F107xx

OTG PHY

D+

D–

ID

V

BUS

V

SS

USB Micro-AB connector

USB
OTG

Full-speed

core

USB
full-speed/
low-speed
transceiver

HNPHNP

IDID

SRPSRP

(2)

V

DD

Cortex-M3

GPIO

GPIO + IRQ

1. ST20x2 needed only if the application has to support bus-powered devices.

ranges between 2 V and 3.6 V.

2. V

DD

A.2 Ethernet interface solutions

Figure 44. MII mode using a 25 MHz crystal

EN

OVRCR
flag

Current-limited

power distribution

switch

ST20x2

(1)

5 V

ai15655

1. HCLK must be greater than 25 MHz.

2. Pulse per second when using IEEE1588 PTP, optional signal.

83/90

Applicative block diagrams STM32F105xx, STM32F107xx

Figure 45. RMII with a 50 MHz oscillator

STM32F107xx

MCU

Ethernet
MAC 10/100

(1)

HCLK

IEEE1588 PTP
Timer
input
trigger

TIM2

2.5 or 25 MHz 50 MHz

OSC

50 MHz

1. HCLK must be greater than 25 MHz.

Timestamp

comparator

synchronous

PLL

/2 or /20

HCLK

RMII_TX_EN

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

MDIO

MDC

PHY_CLK 50 MHz

Figure 46. RMII with a 25 MHz crystal and PHY with PLL

PHY 10/100

RMII

= 7 pins

XT1

Ethernet

RMII + MDC
= 9 pins

50 MHz

ai15657

STM32F107xx

MCU

Ethernet
MAC 10/100

(1)

HCLK

IEEE1588 PTP
Timer
input
trigger

TIM2

2.5 or 25 MHz 50 MHz

XTAL

25 MHz

OSC

1. HCLK must be greater than 25 MHz.

Timestamp

comparator

/2 or /20

synchronous

PLL

HCLK

RMII_TX_EN

RMII_TXD[1:0]

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

MDIO

MDC

PHY_CLK 25 MHz

PHY 10/100

RMII

= 7 pins

REF_CLK

XT1

Ethernet

RMII + MDC
= 9 pins

PLL

ai15658

84/90

STM32F105xx, STM32F107xx Applicative block diagrams

MCU

Ethernet
MAC 10/100

Ethernet

PHY 10/100

PLL

HCLK

XT1/XT2

RMII_RXD[1:0]

RMII_CRX_DV

RMII_REF_CLK

RMII_TX_EN

RMII_TXD[1:0]

MDIO

MDC

HCLK

STM32F107xx

TIM2

Time stamp

comparator

Timer
input
trigger

IEEE1588 PTP

RMII

= 7 pins

RMII + MDC
= 9 pins

ai15659

50 MHz

XTAL

25 MHz

OSC

NS DP83848

(1)

50 MHz

50 MHz

Figure 47. RMII with a 25 MHz crystal

1. The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output
jitter specification of the MCU.

85/90

Applicative block diagrams STM32F105xx, STM32F107xx

Cortex-M3 core

72 MHz

OTG

+

PHY

SPI

SPI

GPIO

I2S

XTAL

14.7456 MHz

USB

Mass-storage

device

MMC/

SDCard

LCD

touch

screen

Control

buttons

Audio
ampli

File

System

Program memory

Audio

CODEC

User

application

STM32F105/STM32F107

ai15661

SOF

SOF synchronization of input/output

audio streaming

A.3 Complete audio player solutions

Two solutions are offered, illustrated in Figure 48 and Figure 49.

Figure 48 shows storage media to audio DAC/amplifier streaming using a software Codec.

This solution implements an audio crystal to provide audio class I

2

S accuracy on the master
clock (0.5% error maximum, see the Serial peripheral interface section in the reference
manual for details).

Figure 48. Complete audio player solution 1

STM32F105/STM32F107

XTAL

14.7456 MHz

USB

Mass-storage

device

MMC/

SDCard

OTG

(host

mode) +

PHY

SPI

Cortex-M3 core

72 MHz

Program memory

File

System

Audio

CODEC

User

application

SPI

GPIO

I2S

touch

screen

Control

buttons

DAC +

Audio
ampli

LCD

ai15660

Figure 49 shows storage media to audio Codec/amplifier streaming with SOF

synchronization of input/output audio streaming using a hardware Codec.

Figure 49. Complete audio player solution 2

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STM32F105xx, STM32F107xx Applicative block diagrams

14.7456 MHz

XTAL

OTG

47.9232 MHz

MCO

PLL2

x12

OSCOSC

MCU

MCO

Div

by 4

sel

Div by 3

PLL1

x6.5
VCO

Out
x13

Div

by 4

PHY

STM32F105/STM32F107

Cortex-M3 core

Up to

147.456 MHz

I2S

PLL3

VCO

Out

x40

SCLK

MCLK
Less than 0.5% accuracy
error on MCLK and SCLK

Up to

71.88 MHz

ai15662

0.16% accuracy error

A.4 USB OTG FS interface + Ethernet/I2S interface solutions

With the clock tree implemented on the STM32F107xx, only one crystal is required to work
with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. Figure 50
illustrate the solution.

Figure 50. USB OTG FS + Ethernet solution

STM32F107

MCU

Div

XTAL

25 MHz

Ethernet

PHY

MCO

OSCOSC

MCO

by 5

sel

sel

PLL2

by 5

PLL3

x10

x8

Div

PLL1

VCO

Up to
50 MHz

x9

Out
x18

up to
72 MHz

Div by 3

Cortex-M3 core

OTG

48 MHz

I2S

PHY

2% accuracy
error

MCLK

SCLK

With the clock tree implemented on the STM32F107xx, only one crystal is required to work
with both the USB (host/device/OTG) and the I

2

S (Audio) interfaces. Figure 51 illustrate the

solution.

Figure 51. USB OTG FS + I

2

S (Audio) solution

87/90

ai15662

Applicative block diagrams STM32F105xx, STM32F107xx

Table 60. PLL configurations

USB

prescaler

(PLL2

VCO

output)

PLL3MUL

I2Sn
clock
input

MCO (main

clock

output)

Application

Crystal

value in

MHz

(XT1)

PREDIV2 PLL2MUL PLL1SRC PREDIV1 PLL1MUL

Ethernet only 25 /5

Ethernet + OTG 25 /5

Ethernet + OTG
+ basic audio

25 /5

Ethernet + OTG
+ Audio class

2S(1)

I

14.7456 /4

PLL2ON

x8

PLL2ON

x8

PLL2ON

x8

PLL2ON

x12

PLL2 /5 PLL1ON x9 NA

PLL2 /5 PLL1ON x9 /3

PLL2 /5 PLL1ON x9 /3

PLL2 /4

PLL1ON

x6.5

/3

PLL3ON

x10

PLL3ON

x10

PLL3ON

x10

PLL3ON

x20

PLL1

PLL3
VCO

NA

NA

Out

XT1 (MII)

PLL3 (RMII)

XT1 (MII)

PLL3 (RMII)

XT1 (MII)

PLL3 (RMII)

NA

ETH PHY

must use its

own crystal

OTG only 8 NA PLL2OFF XT1 /1 PLL1ON x9 /3 PLL3OFF NA NA

OTG + basic
audio

OTG + Audio

2S(1)

class I

Audio class I

(1)

only

8 NA PLL2OFF XT1 /1 PLL1ON x9 /3 PLL3OFF PLL1 NA

14.7456 /4

2

S

14.7456 /4

PLL2ON

x12

PLL2ON

x12

PLL2 /4

PLL2 /4

PLL1ON

x6.5

PLL1ON

x6.5

NA

PLL3ON

/3

x20

PLL3ON

x20

PLL3
VCO

Out

PLL3
VCO

out

NA

NA

1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz.

88/90

STM32F105xx, STM32F107xx Revision history

Revision history

Table 61. Document revision history

Date Revision Changes

18-Dec-2008 1 Initial release.

I/O information clarified on page 1. Figure 4: STM32F105xxx and

STM32F107xxx connectivity line BGA100 ballout corrected.
Section 2.3.8: Boot modes updated.

PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column, plus small additional changes in Ta b le 5 :

Pin definitions.

Consumption values modified in Section 5.3.5: Supply current

20-Feb-2009 2

characteristics.

Note modified in Table 13: Maximum current consumption in Run

mode, code with data processing
Maximum current consumption in Sleep mode, code running from
Flash or RAM.

Table 20: High-speed external user clock characteristics and
Table 21: Low-speed external user clock characteristics modified.

Table 27: PLL1 characteristics modified and Table 28: PLL2 and
PLL3 characteristics added.

running from Flash and Table 15:

89/90

STM32F105xx, STM32F107xx

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