ST STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD User Manual

STM32F103xC STM32F103xD

FBGA

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LQFP144 20 × 20 mm

LFBGA100 10 × 10 mm
LFBGA144 10 × 10 mm

WLCSP64

STM32F103xE

High-density performance line ARM-based 32-bit MCU with 256 to

512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access

– Single-cycle multiplication and hardware

division

■ Memories

– 256 to 512 Kbytes of Flash memory
– up to 64 Kbytes of SRAM
– Flexible static memory controller with 4

Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND

– LCD parallel interface, 8080/6800 modes

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage

detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC with calibration
– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes
–V

■ 3 × 12-bit, 1 µs A/D converters (up to 21

supply for RTC and backup registers

BAT

channels)
– Conversion range: 0 to 3.6 V
– Triple-sample and hold capability
– Temperature sensor

■ 2 × 12-bit D/A converters

■ DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

SDIO, I

■ Debug mode

2

Ss, SPIs, I2Cs and USARTs

– Serial wire debug (SWD) & JTAG interfaces
– Cortex-M3 Embedded Trace Macrocell™

memories

■ Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all
5 V-tolerant

■ Up to 11 timers

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input

– 2 × 16-bit motor control PWM timers with

dead-time generation and emergency stop

– 2 × watchdog timers (Independent and

Window)
– SysTick timer: a 24-bit downcounter
– 2 × 16-bit basic timers to drive the DAC

■ Up to 13 communication interfaces

– Up to 2 × I

2

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)
– Up to 3 SPIs (18 Mbit/s), 2 with I

interface multiplexed
– CAN interface (2.0B Active)
– USB 2.0 full speed interface
– SDIO interface

■ CRC calculation unit, 96-bit unique ID

■ ECOPACK

Table 1. Device summary

Reference Part number

STM32F103xC

STM32F103xD

STM32F103xE

®

packages

STM32F103RC STM32F103VC
STM32F103ZC

STM32F103RD STM32F103VD
STM32F103ZD

STM32F103RE STM32F103ZE
STM32F103VE

2

S

April 2011 Doc ID 14611 Rev 8 1/130

www.st.com

1

Contents STM32F103xC, STM32F103xD, STM32F103xE

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15

2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16

2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 21

2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.21 Inter-integrated sound (I

2

S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 43

5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 84

5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.3.18 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . 102

5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 121

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11

Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 13. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 14. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 15. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47

Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48

Table 18. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 19. Typical current consumption in Sleep mode, code running from Flash or

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 22. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 24. LSE oscillator characteristics (f

Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 28. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 64

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 65

Table 33. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 34. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 35. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 36. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 38. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 39. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 79

Table 40. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 82

Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

LSE

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List of tables STM32F103xC, STM32F103xD, STM32F103xE

Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 50. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 51. I
Table 52. SCL frequency (f

Table 53. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 54. I

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

PCLK1

2

S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 55. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 56. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 57. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 58. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 59. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 60. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

ADC

Table 61. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 62. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 63. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 64. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 65. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 112

Table 66. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 69. Recommended PCB design rules (0.5mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 70. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 117

Table 71. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 118

Table 72. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 119

Table 73. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 74. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE List of figures

List of figures

Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24

Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25

Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26

Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27

Figure 7. STM32F103xC and STM32F103xE performance line

LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 8. STM32F103xC and STM32F103xE performance line

WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 9. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled . . . . . . . . . . . . . . . . . 46

Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V)-

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . 46

Figure 16. Typical current consumption on V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 17. Typical current consumption in Stop mode with regulator in run mode

versus temperature at different V
Figure 18. Typical current consumption in Stop mode with regulator in low-power

mode versus temperature at different V
Figure 19. Typical current consumption in Standby mode versus temperature at

different V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

DD

Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 21. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 64

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 65

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 29. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 75

Figure 33. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 76

Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write

access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 78

Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 79

Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

with RTC on vs. temperature at different V

BAT

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DD

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DD

BAT

Doc ID 14611 Rev 8 7/130

List of figures STM32F103xC, STM32F103xD, STM32F103xE

Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 81

Figure 41. NAND controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . 82

Figure 42. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 43. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 44. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 45. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 46. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 48. I

Figure 49. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 50. SPI timing diagram - slave mode and CPHA = 1
Figure 51. SPI timing diagram - master mode
Figure 52. I
Figure 53. I

2

C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

(1)

(1)

2

S slave timing diagram (Philips protocol)

2

S master timing diagram (Philips protocol)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 54. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 55. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 56. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 57. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 58. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 59. Power supply and reference decoupling (V
Figure 60. Power supply and reference decoupling (V

not connected to V

REF+

connected to V

REF+

). . . . . . . . . . . . . 106

DDA

). . . . . . . . . . . . . . . . 107

DDA

Figure 61. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 62. BGA pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 63. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 64. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package

outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 65. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 66. BGA pad footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad

flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 68. Recommended footprint

Figure 69. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 118

Figure 70. Recommended footprint

Figure 71. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 119

Figure 72. Recommended footprint
Figure 73. LQFP100 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

D

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

8/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line

microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family,

please refer to Section 2.2: Full compatibility throughout the family.

The high-density STM32F103xx datasheet should be read in conjunction with the

STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 14611 Rev 8 9/130

Description STM32F103xC, STM32F103xD, STM32F103xE

2 Description

The STM32F103xC, STM32F103xD and STM32F103xE performance line family

incorporates the high-performance ARM

®

Cortex™-M3 32-bit RISC core operating at a
72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and
SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16­bit timers plus two PWM timers, as well as standard and advanced communication
interfaces: up to two I

2

Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a

CAN.

The STM32F103xx high-density performance line family operates in the –40 to +105 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.

These features make the STM32F103xx high-density performance line microcontroller
family suitable for a wide range of applications such as motor drives, application control,
medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems video intercom, and HVAC.

10/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Description

2.1 Device overview

The STM32F103xx high-density performance line family offers devices in six different
package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.

Figure 1 shows the general block diagram of the device family.

Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral

counts

Peripherals STM32F103Rx STM32F103Vx STM32F103Zx

Flash memory in Kbytes 256 384 512 256 384 512 256 384 512

SRAM in Kbytes 48 64

FSMC No Yes

General-purpose 4

Timers

Advanced-control 2

Basic 2

SPI(I2S)

2

I

(3)

C2

(1)

48 64 48 64

(2)

Ye s

3(2)

Comm

USART 5

USB 1

CAN 1

SDIO 1

GPIOs 51 80 112

12-bit ADC
Number of channels

12-bit DAC
Number of channels

16

3

16

3

3

21

2
2

CPU frequency 72 MHz

Operating voltage 2.0 to 3.6 V

Operating temperatures

Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Ta b le 1 0 )

Junction temperature: –40 to + 125 °C (see Ta b le 1 0)

Package LQFP64, WLCSP64 LQFP100, BGA100 LQFP144, BGA144

1. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.

2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only

support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or
8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is
not available in this package.

3. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the

I2S audio mode.

Doc ID 14611 Rev 8 11/130

Description STM32F103xC, STM32F103xD, STM32F103xE

Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram

TRACECLK
TRACED[0:3]
as AS

NJTRST

JTDI
JTCK/SWCLK
JTMS/SWDIO

JTDO
as AF

A[25:0]
D[15:0]

CLK

NOE

NWE

NE[4:1]

NBL[1:0]

NWAIT

NL (or NADV)

as AF

D[7:0]

CMD

CK as AF

112AF

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

4 channels
3 compl. channels
BKIN, ETR as AF

4 channels
3 compl. channels
BKIN, ETR as AF

MOSI, MISO,
SCK, NSS as AF

RX, TX, CTS,
RTS, CK as AF

8 ADC123_INs
common to the 3 ADCs

8 ADC12_INs common
to ADC1 & ADC2

5 ADC3_INs on ADC3

V

REF–

V

REF+

TPIU

Trace/trig

SW/JTAG

Cortex-M3 CPU

F

: 48/72 MHz

max

NVIC

GP DMA1

7 channels

GP DMA2

5 channels

EXT.IT
WKUP

GPIO port A

GPIO port B

GPIO port C

GPIO port D

GPIO port E

GPIO port F

GPIO port G

TIM1

TIM8

SPI1

USART1

Temp. sensor

12-bit ADC1

12-bit ADC2

12-bit ADC3

@ V

DDA

FSMC

SDIO

IF

IF

IF

Pbus

Dbus

System

Ibus

Bus Matrix

APB2: Fmax = 48/72 MHz

Trace
controller

AHB2
APB2

obl

Flash 512 Kbytes

Flash

interface

SRAM

64 KB

Reset &
Clock
control

AHB: Fmax = 48/72 MHz

AHB2

APB1

64 bit

SRAM 512 B

WWDG

TIM6

TIM7

RC 8 MHz

RC 40 kHz

PCLK1
PCLK2
HCLK
FCLK

@V

PLL

DDA

POR

Reset

= 24/36 MHz

max

APB1: F

V

DD

Supply
supervision

POR / PDR

Int

Standby

interface

RTC

AWU

Backup interface

SPI2 / I2 S2

2x(8x16bit)

SPI3 / I2S3

2x(8x16bit)

bxCAN device

USB 2.0 FS
device

IFIF
IF

@V

@V

DD

Power

Volt. reg.

3.3 V to 1.8 V

@V

DDA

PVD

@V

DD
XTAL OSC
4-16 MHz

IWDG

V

@

BAT

XTAL 32kHz

Backup

reg

TIM2

TIM3

TIM4

TIM5

USART 2

USART 3

UART4

UART5

I2C1

I2C2

12bit DAC1

12bit DAC 2

DDA

V

SS

NRST
V

DDA

V

SSA

OSC_IN
OSC_OUT

V

=1.8 V to 3.6 V

BAT

OSC32_IN
OSC32_OUT

TAMPER-RTC/
ALARM/SECOND OUT

4 channels, ETR as AF

4 channels, ETR as AF

4 channels, ETR as AF

4 channels as AF

RX, TX, CTS, RTS,
CK as AF

RX, TX, CTS, RT S,
CK as AF

RX,TX as AF

RX,TX as AF

MOSI/SD, MISO
SCK/CK, MCK, NSS/WS as AF

MOSI/SD, MISO

SCK/CK, MCK, NSS/WS as AF

SCL, SDA, SMBA as AF

SCL, SDA, SMBA as AF

USBDP/CAN_TX
USBDM/CAN_RX

DAC_OUT1 as AF

DAC_OUT2 as AF

ai14666f

1. TA = –40 °C to +85 °C (suffix 6, see Table 74) or –40 °C to +105 °C (suffix 7, see Table 74), junction temperature up to
105 °C or 125 °C, respectively.

2. AF = alternate function on I/O port pin.

12/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Description

HSE OSC

4-16 MHz

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

LSE OSC

32.768 kHz

HSI RC

8 MHz

LSI RC
40 kHz

to Independent Watchdog (IWDG)

PLL

x2, x3, x4

PLLMUL

HSE = High Speed External clock signal

LSE = Low Speed External clock signal

LSI = Low Speed Internal clock signal

HSI = High Speed Internal clock signal

Legend:

MCO

Clock Output

Main

PLLXTPRE

/2

..., x16

AHB
Prescaler
/1, 2..512

/2

PLLCLK

HSI

HSE

APB1

Prescaler

/1, 2, 4, 8, 16

ADC
Prescaler
/2, 4, 6, 8

ADCCLK

PCLK1

HCLK

PLLCLK

to AHB bus, core,
memory and DMA

USBCLK

to USB interface

USB

Prescaler

/1, 1.5

to ADC1, 2 or 3

LSE

LSI

HSI

/128

/2

HSI

HSE

peripherals

to APB1

Peripheral Clock

Enable (20 bits)

Enable (6 bits)

Peripheral Clock

APB2

Prescaler

/1, 2, 4, 8, 16

PCLK2

TIM1 & 8 timers

to TIM1 and TIM8

peripherals to APB2

Peripheral Clock

Enable (15 bits)

Enable (2 bit)

Peripheral Clock

48 MHz

72 MHz max

72 MHz

72 MHz max

36 MHz max

to RTC

PLLSRC

SW

MCO

CSS

to Cortex System timer

/8

Clock

Enable (4 bits)

SYSCLK

max

RTCCLK

RTCSEL[1:0]

TIMxCLK

TIMXCLK

IWDGCLK

SYSCLK

FCLK Cortex
free running clock

/2

TIM2,3,4,5,6,7

to TIM2,3,4,5,6 and 7

To SDIO AHB interface
Peripheral clock
enable

HCLK/2

to FSMC

FSMCCLK

to SDIO

Peripheral clock
enable

Peripheral clock
enable

to I2S3

to I2S2

Peripheral clock
enable

Peripheral clock
enable

I2S3CLK

I2S2CLK

SDIOCLK

ai14752b

If (APB1 prescaler =1) x1

else x2

If (APB2 prescaler =1) x1

else x2

FLITFCLK
to Flash programming interface

Figure 2. Clock tree

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.

2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.

3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

Doc ID 14611 Rev 8 13/130

Description STM32F103xC, STM32F103xD, STM32F103xE

2.2 Full compatibility throughout the family

The STM32F103xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are
identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as
medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are
referred to as high-density devices.

Low-density and high-density devices are an extension of the STM32F103x8/B medium­density devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E
datasheets, respectively. Low-density devices feature lower Flash memory and RAM
capacities, less timers and peripherals. High-density devices have higher Flash memory
and RAM capacities, and additional peripherals like SDIO, FSMC, I
remaining fully compatible with the other members of the family.

The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE
are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different
memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F103xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.

Table 3. STM32F103xx family

2

S and DAC while

Low-density devices Medium-density devices High-density devices

Pinout

16 KB

Flash

32 KB

Flash

(1)

64 KB

Flash

128 KB

Flash

256 KB

Flash

384 KB

Flash

512 KB

Flash

6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 RAM 64 KB RAM 64 KB RAM

144 5 × USARTs

100

2 × USARTs

64

2 × 16-bit timers
1 × SPI, 1 × I

48

CAN, 1 × PWM timer
2 × ADCs

36

1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),
the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density
devices.

2. Ports F and G are not available in devices delivered in 100-pin packages.

2

C, USB,

3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I

2

Cs, USB,
CAN, 1 × PWM timer
2 × ADCs

4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I

2

Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 2 × DACs, 1 × SDIO
FSMC (100- and 144-pin packages

(2)

)

14/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Description

2.3 Overview

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE
performance line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2 Embedded Flash memory

Up to 512 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

2.3.4 Embedded SRAM

Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.

2.3.5 FSMC (flexible static memory controller)

The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE
performance line family. It has four Chip Select outputs supporting the following modes: PC
Card/Compact Flash, SRAM, PSRAM, NOR and NAND.

Functionality overview:

● The three FSMC interrupt lines are ORed in order to be connected to the NVIC

● Write FIFO

● Code execution from external memory except for NAND Flash and PC Card

● The targeted frequency, f

is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz

, is HCLK/2, so external access is at 36 MHz when HCLK

CLK

Doc ID 14611 Rev 8 15/130

Description STM32F103xC, STM32F103xD, STM32F103xE

2.3.6 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost­effective graphic applications using LCD modules with embedded controllers or high­performance solutions using external controllers with dedicated acceleration.

2.3.7 Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested
vectored interrupt controller able to handle up to 60 maskable interrupt channels (not
including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

2.3.8 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.

2.3.9 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and
the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed
APB domain is 36 MHz. See Figure 2 for details on the clock tree.

16/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Description

2.3.10 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash
memory bank 2 by setting a bit in the option bytes.

● Boot from system memory

● Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1.

2.3.11 Power supply schemes

● V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

DD

Provided externally through V

● V

SSA

, V

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

DDA

RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC

● V

is used). V

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

BAT

DDA

and V

must be connected to VDD and VSS, respectively.

SSA

registers (through power switch) when V

For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

2.3.12 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

generated when V
than the V

power supply and compares it to the V

DD/VDDA

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

V

POR/PDR

and V

PVD

is below a specified threshold, V

DD

drops below the V

.

DD

pins.

is not present.

DD

POR/PDR

threshold. An interrupt can be

PVD

threshold and/or when VDD/V

PVD

, without the need for an

is higher

DDA

2.3.13 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop modes.

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

Doc ID 14611 Rev 8 17/130

Description STM32F103xC, STM32F103xD, STM32F103xE

2.3.14 Low-power modes

The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three
low-power modes to achieve the best compromise between low power consumption, short
startup time and available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.15 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to­peripheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I
and advanced-control timers TIMx, DAC, I

2

S, SDIO and ADC.

2

C, USART, general-purpose, basic

2.3.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
V

supply when present or through the V

DD

registers used to store 84 bytes of user application data when V
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.

pin. The backup registers are forty-two 16-bit

BAT

power is not present.

DD

The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a

18/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Description

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.17 Timers and watchdogs

The high-density STM32F103xx performance line devices include up to two advanced­control timers, up to four general-purpose timers, two basic timers, two watchdog timers and
a SysTick timer.

Ta bl e 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4. High-density timer feature comparison

Timer

TIM1,
TIM8

TIM2,
TIM3,
TIM4,
TIM5

TIM6,
TIM7

Counter

resolution

16-bit

16-bit

16-bit Up

Counter

type

Up,

down,

up/down

Up,

down,

up/down

Prescaler

factor

Any integer

between 1
and 65536

Any integer

between 1
and 65536

Any integer

between 1
and 65536

DMA request

generation

Capture/compare

channels

Ye s 4 Ye s

Ye s 4 N o

Ye s 0 N o

Complementary

outputs

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase
PWM multiplexed on 6 channels. They have complementary PWM outputs with
programmable inserted dead-times. They can also be seen as a complete general-purpose
timer. The 4 independent channels can be used for:

● Input capture

● Output compare

● PWM generation (edge or center-aligned modes)

● One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the
same architecture. The advanced-control timer can therefore work together with the TIM
timers via the Timer Link feature for synchronization or event chaining.

Doc ID 14611 Rev 8 19/130

Description STM32F103xC, STM32F103xD, STM32F103xE

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)
embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line
devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler
and feature 4 independent channels each for input capture/output compare, PWM or one­pulse mode output. This gives up to 16 input captures / output compares / PWMs on the
largest packages.
The general-purpose timers can work together with the advanced-control timer via the Timer
Link feature for synchronization or event chaining. Their counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs. They all
have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.

2.3.18 I²C bus

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

20/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Description

2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three
universal synchronous/asynchronous receiver transmitters (USART1, USART2 and
USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other
available interfaces communicate at up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.

2.3.20 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.3.21 Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
48 kHz are supported. When either or both of the I
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.

2.3.22 SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD
Memory Card Specifications Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital
protocol Rev1.1.

2

S interfaces is/are configured in master

2.3.23 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.

Doc ID 14611 Rev 8 21/130

Description STM32F103xC, STM32F103xD, STM32F103xE

2.3.24 Universal serial bus (USB)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB
device peripheral compatible with the USB full-speed 12 Mbs. The USB interface
implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint
setting and suspend/resume support. The dedicated 48 MHz clock is generated from the
internal main PLL (the clock source must use a HSE crystal oscillator).

2.3.25 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current­capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

2.3.26 ADC (analog to digital converter)

Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD
and STM32F103xE performance line devices and each ADC shares up to 21 external
channels, performing conversions in single-shot or scan modes. In scan mode, automatic
conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

● Simultaneous sample and hold

● Interleaved sample and hold

● Single shunt

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) and the advanced-control
timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection
trigger, respectively, to allow the application to synchronize A/D conversion and timers.

2.3.27 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.

22/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Description

This dual digital Interface supports the following features:

● two DAC converters: one for each output channel

● 8-bit or 12-bit monotonic output

● left or right data alignment in 12-bit mode

● synchronized update capability

● noise-wave generation

● triangular-wave generation

● dual DAC channel independent or simultaneous conversions

● DMA capability for each channel

● external triggers for conversion

● input voltage reference V

REF+

Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and
STM32F103xE performance line family. The DAC channels are triggered through the timer
update outputs that are also connected to different DMA channels.

2.3.28 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.

< 3.6 V. The temperature sensor is internally

DDA

2.3.29 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

2.3.30 Embedded Trace Macrocell™

The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F10xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer running debugger software. TPA
hardware is commercially available from common development tool vendors. It operates
with third party debugger software tools.

Doc ID 14611 Rev 8 23/130

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

AI14798b

V

DD_7

PC3PC2

PF6

V

DD_6

V

SS_4

PF8

H

V

DD_1

D PG13

PG14

PE6PE5

C

PG10

PG11

V

DD_5

PB8

NRST

B PG12PG15

PC15-

OSC32_OUT

PB9

A

87654321

V

BAT

OSC_IN

OSC_OUT

V

SS_5

G

F

E

PF7

PC0

PF0 PF1

PF2

V

SS_10

PG9PF4

PF3

V

SS_3

PF5

V

DD_8

V

DD_3

V

DD_4

V

SS_8

PE4

PB5

PB6

BOOT0 PB7

V

SS_11

PF10

PC1

V

DD_11VDD_10

PF9

109

K

J

V

SS_2

PD3

PD4

PD1

PC12

PC11

PD5

PD2 PD0

V

DD_9

V

SS_9

V

DD_2

PG1

PC5PA5 PE9

PB2/

BOOT1

PC4PA4

PE10

PG0PF13V

REF–

PE12V

SSA

PA1 PE13

PA0-WKUP

PD9

PD10

PG4

PD13

1211

PG8

PA10

NC

PA9

PA11

PA12

PC10

PC9 PA8

PC7

PC6

PC8

PD14

PG3

PG2

PD15

M

L

PF15

PB1PA7 PE7

PF12

PB0PA6

PE8

PF14PF11V

DDA

PE14V

REF+

PA3 PE15

PA2

PB10

PD8

PD12

PB11

PB12

PB14

PB15

PB13

PC13-

TAMPER-RTC

PE3 PE2 PE1 PE0

PB4

JTRST

PB3

JTDO

PD6 PD7

PA15
JTDI

PA14
JTCK

PA13

JTMS

PE11V

SS_6

V

SS_7VSS_1

PG7

PD11

PG5

PG6

PC14-

OSC32_IN

3 Pinouts and pin descriptions

Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout

24/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

AI14601c

PE10

PC14-

OSC32_IN

PC5PA5

PC3

PB4

PE15

PB2

PC4PA4

H

PE14

PE11PE7

D PD4

PD3

PB8PE3

C

PD0

PC12

PE5

PB5

PC0

PE2

B PC11PD2

PC15-

OSC32_OUT

PB7

PB6

A

87654321

V

SS_5

OSC_IN

OSC_OUT V

DD_5

G

F

E

PC1

V

REF–

PC13-

TAMPER-RTC

PB9

PA15

PB3

PE4

PE1

PE0

V

SS_1

PD1PE6NRST

PC2

V

SS_3

V

SS_4

NCV

DD_3

V

DD_4

PB15

V

BAT

PD5

PD6

BOOT0 PD7

V

SS_2

V

SSA

PA1

V

DD_2

V

DD_1

PB14

PA0-WKUP

109

K

J

PD10

PD11

PA8

PA9

PA10

PA11

PA12

PC10

PA13

PA14

PC9

PC7

PC6

PD15

PC8

PD14

PE12

PB1PA7

PB11

PE8

PB0PA6

PB10

PE13PE9V

DDA

PB13

V

REF+

PA3

PB12

PA2

PD8

PD9

PD13

PD12

Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout

Doc ID 14611 Rev 8 25/130

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

V

DD_3VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PG15

V

DD_11VSS_11

PG14

PG13

PG12

PG11

PG10

PG9

PD7

PD6

V

DD_10VSS_10

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

PE2

V

DD_2

PE3

V

SS_2

PE4

NC

PE5

PA13

PE6

PA12

VBAT

PA11

PC13-TAMPER-RTC

PA10

PC14-OSC32_IN

PA9

PC15-OSC32_OUT

PA8

PF0

PC9

PF1

PC8

PF2

PC7

PF3

PC6

PF4

V

DD_9

PF5

V

SS_9

V

SS_5

PG8

V

DD_5

PG7

PF6

PG6

PF7

PG5

PF8

PG4

PF9

PG3

PF10

PG2

OSC_IN

PD15

OSC_OUT

PD14

NRST

V

DD_8

PC0

V

SS_8

PC1

PD13

PC2

PD12

PC3

PD11

V

SSA

PD10

V

REF-

PD9

V

REF+

PD8

V

DDA

PB15

PA0-WKUP

PB14

PA1

PB13

PA2

PB12

PA3

V

SS_4

V

DD_4

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PF11

PF12

VSS_6

V

DD_6

PF13

PF14

PF15

PG0

PG1

PE7

PE8

PE9

V

SS_7

V

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V

SS_1

V

DD_1

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

109

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84

3738394041424344454647484950515253545556575859

60

72

LQFP144

120

119

118

117

116

115

114

113

112

111

110

6162636465666768697071

26
27
28
29
30
31
32
33
34
35
36

83
82
81
80
79
78
77
76
75
74
73

ai14667

Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout

26/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

100999897969594939291908988878685848382818079787776

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

VDD_2
VSS_2
NC
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

VDD_1

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

26272829303132333435363738394041424344454647484950

PE2
PE3
PE4
PE5
PE6

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

OSC_IN

OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VREF-

VREF+

VDDA

PA 0- W K UP

PA 1
PA 2

ai14391

LQFP100

Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout

Doc ID 14611 Rev 8 27/130

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47
46

45
44
43

42

41

40

39

38

37

36

35

34

33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1

2
3

4

5
6

7

8

9

10
11
12

13

14
15

16

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

PC0
PC1
PC2

PC3
VSSA
VDDA

PA 0- W K UP

PA 1
PA 2

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA1 5

PA 14

VDD_2
VSS_2
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

LQFP64

ai14392

Figure 7. STM32F103xC and STM32F103xE performance line

LQFP64 pinout

28/130 Doc ID 14611 Rev 8

STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions

Figure 8. STM32F103xC and STM32F103xE performance line

WLCSP64 ballout, ball side

87654321

A

V

DD_3

V

SS_3

B

C

D

E

F

G

H

PC13 NRST V

BAT

OSC_IN OSC_OUT PC2 PB8 PA13 PA10 PA9 PC9

PC0 V

PC1

V

DDA

V

PA3

SSA

REF+

PA1 PA5 PA8 PC8 PC7 PC6

PA0­WKUP

V

DD_4

PA2 PA4 PC4 PC5 PB0 PB2

PB7 PC12 PA15 PA12 PA11

V

SS_4

PB1 PB11 PB14 PB15

PA6 PA7 PB10 PB12 PB13

PC10PD2PB5 PB3BOOT0

BYPASS/

PA14PC11PB4PB6PB9PC15PC14

V

V

SS_1VDD_1

V

DD_2

SS_2

ai15460b

Doc ID 14611 Rev 8 29/130

Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE

LFBGA100

Pins

WLCSP64

LQFP64

(2)

Pin name

(1)

Typ e

LQFP100

LQFP144

Main

function

(after reset)

I / O Level

(3)

Default Remap

Table 5. High-density STM32F103xx pin definitions

LFBGA144

A3 A3 - - 1 1 PE2 I/O FT PE2 TRACECK/ FSMC_A23

A2 B3 - - 2 2 PE3 I/O FT PE3 TRACED0/FSMC_A19

B2 C3 - - 3 3 PE4 I/O FT PE4 TRACED1/FSMC_A20

B3 D3 - - 4 4 PE5 I/O FT PE5 TRACED2/FSMC_A21

B4 E3 - - 5 5 PE6 I/O FT PE6 TRACED3/FSMC_A22

C2 B2 C6 1 6 6 V

A1 A2 C8 2 7 7

B1 A1 B8 3 8 8

C1 B1 B7 4 9 9

PC13-TAMPER-

RTC

PC14-

OSC32_IN

PC15-

OSC32_OUT

BAT

(5)

SV

I/O PC13

I/O PC14

(5)

I/O PC15

(5)

BAT

(6)

(6)

(6)

TAMPER-RTC

OSC32_IN

OSC32_OUT

C3 - - - - 10 PF0 I/O FT PF0 FSMC_A0

C4 - - - - 11 PF1 I/O FT PF1 FSMC_A1

D4 - - - - 12 PF2 I/O FT PF2 FSMC_A2

E2 - - - - 13 PF3 I/O FT PF3 FSMC_A3

E3 - - - - 14 PF4 I/O FT PF4 FSMC_A4

E4 - - - - 15 PF5 I/O FT PF5 FSMC_A5

D2 C2 - - 10 16 V

D3 D2 - - 11 17 V

SS_5

DD_5

SV

SV

SS_5

DD_5

F3 - - - - 18 PF6 I/O PF6 ADC3_IN4/FSMC_NIORD

F2 - - - - 19 PF7 I/O PF7 ADC3_IN5/FSMC_NREG

G3 - - - - 20 PF8 I/O PF8 ADC3_IN6/FSMC_NIOWR

G2 - - - - 21 PF9 I/O PF9 ADC3_IN7/FSMC_CD

G1 - - - - 22 PF10 I/O PF10 ADC3_IN8/FSMC_INTR

D1 C1 D8 5 12 23 OSC_IN I OSC_IN

E1 D1 D7 6 13 24 OSC_OUT O OSC_OUT

F1 E1 C7 7 14 25 NRST I/O NRST

H1 F1 E8 8 15 26 PC0 I/O PC0 ADC123_IN10

H2 F2 F8 9 16 27 PC1 I/O PC1 ADC123_IN11

H3 E2 D6 10 17 28 PC2 I/O PC2 ADC123_IN12

H4 F3 - 11 18 29 PC3 I/O PC3 ADC123_IN13

J1 G1 E7 12 19 30 V

SSA

SV

SSA

Alternate functions

(4)

30/130 Doc ID 14611 Rev 8