STM32F103x8
STM32F103xB
Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
Features
■ARM 32-bit Cortex™-M3 CPU Core
–72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
–Single-cycle multiplication and hardware division
■Memories
–64 or 128 Kbytes of Flash memory
–20 Kbytes of SRAM
■Clock, reset and supply management
–2.0 to 3.6 V application supply and I/Os
–POR, PDR, and programmable voltage detector (PVD)
–4-to-16 MHz crystal oscillator
–Internal 8 MHz factory-trimmed RC
–Internal 40 kHz RC
–PLL for CPU clock
–32 kHz oscillator for RTC with calibration
■Low power
–Sleep, Stop and Standby modes
–VBAT supply for RTC and backup registers
■2 x 12-bit, 1 µs A/D converters (up to 16 channels)
–Conversion range: 0 to 3.6 V
–Dual-sample and hold capability
–Temperature sensor
■DMA
–7-channel DMA controller
–Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs
■Up to 80 fast I/O ports
–26/37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
VFQFPN48 7 × 7 mm |
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LQFP100 14 × 14 m |
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VFQFPN36 6 × 6 mm |
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LQFP64 10 |
× 10 m |
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LQFP48 7 |
× 7 m |
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BGA100 10 × 10 mm
BGA64 5 × 5 mm
■Debug mode
–Serial wire debug (SWD) & JTAG interfaces
■7 timers
–Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
–16-bit, motor control PWM timer with deadtime generation and emergency stop
–2 watchdog timers (Independent and Window)
–SysTick timer 24-bit downcounter
■Up to 9 communication interfaces
–Up to 2 x I2C interfaces (SMBus/PMBus)
–Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
–Up to 2 SPIs (18 Mbit/s)
–CAN interface (2.0B Active)
–USB 2.0 full-speed interface
■CRC calculation unit, 96-bit unique ID
■Packages are ECOPACK®
Reference |
Part number |
STM32F103x8 STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103RB STM32F103VB,
STM32F103xB STM32F103CB, STM32F103TB
April 2011 |
Doc ID 13587 Rev 13 |
1/99 |
www.st.com
Contents |
STM32F103x8, STM32F103xB |
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Contents
1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 9 |
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2 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 9 |
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2.1 |
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
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2.2 |
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . |
13 |
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2.3 |
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 14 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.17Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 |
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
4 |
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
2/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB Contents
5 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.1 |
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 |
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3 |
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.1 |
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.2 |
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . |
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5.3.3 |
Embedded reset and power control block characteristics . . . . . . . . . . . |
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5.3.4 |
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.5 |
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.6 |
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.7 |
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.8 |
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.9 |
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.10 |
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.11 |
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . |
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5.3.12 |
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.13 |
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.14 |
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.15 |
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.16 |
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.17 |
CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . |
72 |
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5.3.18 |
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.19 |
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
6 |
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6.1 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6.2 |
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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6.2.1 |
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
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6.2.2 |
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
Doc ID 13587 Rev 13 |
3/99 |
Contents |
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STM32F103x8, STM32F103xB |
7 |
Ordering information scheme . . . . . . . . . . . . . |
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . |
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4/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
List of tables |
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10 Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 12. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 13. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 42 Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43 Table 17. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 22. HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 24. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 27. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 28. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 29. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 30. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 31. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 32. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 33. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 34. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 35. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 36. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 37. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 38. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 39. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 40. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 41. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 43. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 44. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Doc ID 13587 Rev 13 |
5/99 |
List of tables |
STM32F103x8, STM32F103xB |
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Table 45. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 46. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 47. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 48. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 49. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 50. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 51. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 79 Table 52. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 80 Table 53. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 54. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . . 83 Table 55. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 84 Table 56. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 85 Table 57. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 87 Table 58. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 59. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
List of figures |
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List of figures
Figure 1. |
STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
Figure 2. |
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
12 |
Figure 3. |
STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
21 |
Figure 4. |
STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
Figure 5. |
STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
23 |
Figure 6. |
STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
24 |
Figure 7. |
STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
Figure 8. |
STM32F103xx performance line VFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
Figure 9. |
STM32F103xx performance line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
Figure 10. |
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
Figure 11. |
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
Figure 12. |
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
Figure 13. |
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
Figure 14. |
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
35 |
Figure 15. |
Typical current consumption in Run mode versus frequency (at 3.6 V) - |
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code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . |
41 |
Figure 16. |
Typical current consumption in Run mode versus frequency (at 3.6 V) - |
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code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . |
41 |
Figure 17. |
Typical current consumption on VBAT with RTC on versus temperature at different |
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VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
Figure 18. |
Typical current consumption in Stop mode with regulator in Run mode versus |
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temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
Figure 19. |
Typical current consumption in Stop mode with regulator in Low-power mode versus |
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temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
Figure 20. |
Typical current consumption in Standby mode versus temperature at |
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VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
Figure 21. |
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
Figure 22. |
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
Figure 23. |
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
Figure 24. |
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
Figure 25. |
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
Figure 26. |
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
61 |
Figure 27. |
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
62 |
Figure 28. |
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
62 |
Figure 29. |
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
65 |
Figure 30. |
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
66 |
Figure 31. |
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
68 |
Figure 32. |
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
70 |
Figure 33. |
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
70 |
Figure 34. |
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
71 |
Figure 35. |
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . |
72 |
Figure 36. |
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
75 |
Figure 37. |
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
76 |
Figure 38. |
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . |
76 |
Figure 39. |
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . |
77 |
Figure 40. |
VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 79 |
Figure 41. |
Recommended footprint (dimensions in mm)(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 79 |
Figure 42. |
VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
Doc ID 13587 Rev 13 |
7/99 |
List of figures |
STM32F103x8, STM32F103xB |
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Figure 43. Recommended footprint (dimensions in mm)(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 44. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package
outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 45. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 82
Figure 46. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 83 Figure 47. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 48. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 84 Figure 49. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 50. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 85 Figure 51. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 86
Figure 52. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 87 Figure 53. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 54. LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
8/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
Introduction |
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This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F103xx datasheet should be read in conjunction with the low-, mediumand high-density STM32F10xxx reference manual.
The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
The STM32F103xx medium-density performance line family incorporates the highperformance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN.
The devices operate from a 2.0 to 3.6 V power supply. They are available in both the –40 to +85 °C temperature range and the –40 to +105 °C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F103xx medium-density performance line family includes devices in six different package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.
These features make the STM32F103xx medium-density performance line microcontroller family suitable for a wide range of applications such as motor drives, application control, medical and handheld equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Doc ID 13587 Rev 13 |
9/99 |
Description |
STM32F103x8, STM32F103xB |
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Table 2. |
STM32F103xx medium-density device features and peripheral counts |
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Peripheral |
STM32F103Tx |
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STM32F103Cx |
STM32F103Rx |
STM32F103Vx |
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Flash - Kbytes |
64 |
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128 |
64 |
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128 |
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64 |
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128 |
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64 |
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128 |
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SRAM - Kbytes |
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20 |
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20 |
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20 |
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20 |
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Timers |
Advanced-control |
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1 |
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1 |
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1 |
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1 |
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General-purpose |
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3 |
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3 |
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3 |
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3 |
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Communication |
SPI |
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1 |
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2 |
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2 |
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2 |
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I2C |
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1 |
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2 |
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2 |
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2 |
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USART |
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2 |
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3 |
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3 |
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3 |
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USB |
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1 |
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1 |
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1 |
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1 |
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CAN |
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1 |
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1 |
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1 |
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1 |
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GPIOs |
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26 |
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37 |
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51 |
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80 |
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12-bit synchronized ADC |
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2 |
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2 |
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2 |
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Number of channels |
10 channels |
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10 channels |
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16 channels |
16 channels |
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CPU frequency |
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72 MHz |
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Operating voltage |
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2.0 to 3.6 V |
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Operating temperatures |
Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9) |
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Junction temperature: –40 to + 125 °C (see Table 9) |
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Packages |
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VFQFPN36 |
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LQFP48, |
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LQFP64, |
LQFP100, |
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VFQFPN48 |
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TFBGA64 |
LFBGA100 |
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10/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
Description |
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TRACECLK |
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TRACED[0:3] |
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TPIU |
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as AS |
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Trace/trig |
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SW/JTAG |
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NJTRST |
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JTDI |
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Cortex-M3 CPU |
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JTCK/SWCLK |
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JTMS/SWDIO |
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JTDO |
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Fmax : 7 2M Hz |
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as AF |
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Trace |
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pbu s |
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Controlle r |
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obl |
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Ibu s |
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e |
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Interfac |
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flash |
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Dbus |
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POWER |
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VDD = 2 to 3.6V |
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VOLT. REG. |
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Flash 128 KB |
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3.3V TO 1.8V |
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VSS |
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64 bit |
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@VDD |
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NRST
VDDA
VSSA
80AF
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
4 Channels
3 compl. Channels ETR and BKIN
MOSI,MISO,
SCK,NSS as AF
RX,TX, CTS, RTS,
Smart Card as AF
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S |
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NVIC |
yst em |
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GP DMA
7 channels
@VDDA
SUPPLY
SUPERVISION
POR / PDR Rst
PVD |
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Int |
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EXTI
WAKEUP
GPIOA |
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GPIOB |
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GPIOC |
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GPIOD |
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MHz |
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GPIOE |
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=48 / 72 |
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max |
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TIM1 |
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F |
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APB2 : |
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SPI1 |
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USART1 |
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@VDDA |
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16AF |
12bit ADC1 |
IF |
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VREF+ |
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VREF- |
12bit ADC2 |
IF |
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Temp sens or |
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AHB:F max=48/72 MHz
AHB2
APB2
SRAM 20 KB
PCLK1 PCLK2
HCLK
FCLK
RC 8 MHz
RC 40 kHz
@VDDA
AHB2
APB1
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@VDD |
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PLL |
& |
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OSC_IN |
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XTAL OSC |
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OSC_OUT |
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CLOCK |
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4-16 MHz |
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MANAGT |
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IWDG |
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Stand by |
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interface |
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VBAT |
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@VBAT |
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OSC32_IN |
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XTAL 32 kHz |
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OSC32_OUT |
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RTC |
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Back up |
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TAMPER-RTC |
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AWU |
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reg |
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Backu p interf ace |
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4 Channels |
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TIM2 |
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4 Channels |
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TIM3 |
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4 Channels |
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TIM 4 |
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RX,TX, CTS, RTS, |
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USART2 |
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CK, SmartCard as AF |
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RX,TX, CTS, RTS, |
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USART3 |
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CK, SmartCard as AF |
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MOSI,MISO,SCK,NSS |
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SPI2 |
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2x(8x16bit) |
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as AF |
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I2C1 |
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SCL,SDA,SMBA |
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as AF |
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I2C2 |
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SCL,SDA |
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as AF |
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bxCAN |
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USBDP/CAN_TX |
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USB 2.0 FS |
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USBDM/CAN_RX |
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SRAM 512B |
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W W D G |
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ai14390d
1.TA = –40 °C to +105 °C (junction temperature up to 125 °C).
2.AF = alternate function on I/O port pin.
Doc ID 13587 Rev 13 |
11/99 |
Description |
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STM32F103x8, STM32F103xB |
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Figure 2. |
Clock tree |
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FLITFCLK |
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to Flash programming interface |
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8 MHz |
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HSI RC |
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HSI |
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USB |
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48 MHz |
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USBCLK |
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to USB interface |
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Prescaler |
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/2 |
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/1, 1.5 |
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HCLK |
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72 MHz max |
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to AHB bus, core, |
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Clock |
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memory and DMA |
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Enable (3 |
bits) |
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PLLSRC PLLMUL |
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SW |
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/8 |
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to Cortex System timer |
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FCLK Cortex |
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free running clock |
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..., x16 |
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HSI |
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SYSCLK |
AHB |
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x2, x3, x4 |
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Prescaler |
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36 MHz max |
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PCLK1 |
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PLLCLK |
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72 MHz |
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to APB1 |
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PLL |
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max |
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peripherals |
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HSE |
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TIM2,3, 4 |
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and 4 |
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CSS |
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TIMXCLK |
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Enable (3 bits) |
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PLLXTPRE |
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APB2 |
72 MHz max |
PCLK2 |
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OSC_OUT |
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peripherals |
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TIM1CLK |
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x2 Peripheral Clock |
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ADC |
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Enable (1 bit) |
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OSC32_IN |
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to RTC |
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to ADC |
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LSE |
Prescaler |
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32.768 kHz |
RTCCLK |
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OSC32_OUT |
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RTCSEL[1:0] |
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LSI RC |
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LSI |
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to Independent Watchdog (IWDG) |
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40 kHz |
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IWDGCLK |
Legend: |
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HSE = high-speed external clock signal |
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Main |
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HSI = high-speed internal clock signal |
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/2 |
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PLLCLK |
LSI = low-speed internal clock signal |
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MCO |
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Clock Output |
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HSI |
LSE = low-speed external clock signal |
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HSE |
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SYSCLK |
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MCO |
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ai14903 |
1.When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.
2.For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48 MHz.
3.To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
12/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
Description |
|
|
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.
Lowand high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family.
The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.
Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.
Table 3. |
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STM32F103xx family |
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Low-density devices |
Medium-density devices |
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High-density devices |
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Pinout |
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16 KB |
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32 KB |
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64 KB |
128 KB |
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256 KB |
384 KB |
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512 KB |
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Flash |
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Flash(1) |
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Flash |
Flash |
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Flash |
Flash |
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Flash |
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6 KB RAM |
10 KB RAM |
20 KB RAM |
20 KB RAM |
48 KB RAM |
64 KB RAM |
64 KB RAM |
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144 |
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5 |
× USARTs |
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4 |
× 16-bit timers, 2 × basic timers |
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100 |
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3 |
× USARTs |
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3 |
× SPIs, 2 × I2Ss, 2 × I2Cs |
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2 |
× USARTs |
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USB, CAN, 2 × PWM timers |
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64 |
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× 16-bit timers |
3 |
× ADCs, 2 × DACs, 1 × SDIO |
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2 |
× 16-bit timers |
2 |
× SPIs, 2 × I2Cs, USB, |
FSMC (100 and 144 pins) |
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1 |
× SPI, 1 × I2C, USB, |
CAN, 1 × PWM timer |
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48 |
CAN, 1 × PWM timer |
2 |
× ADCs |
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× ADCs |
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36 |
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1.For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices.
Doc ID 13587 Rev 13 |
13/99 |
Description |
STM32F103x8, STM32F103xB |
|
|
2.3.1ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.
●Closely coupled NVIC gives low-latency interrupt processing
●Interrupt entry vector table address passed directly to the core
●Closely coupled NVIC core interface
●Allows early processing of interrupts
●Processing of late arriving higher priority interrupts
●Support for tail-chaining
●Processor state automatically saved
●Interrupt entry restored on interrupt exit with no instruction overhead
14/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
Description |
|
|
This hardware block provides flexible interrupt management features with minimal interrupt latency.
The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree.
At startup, boot pins are used to select one of three boot options:
●Boot from User Flash
●Boot from System Memory
●Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.
●VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins.
●VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively.
●VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 13: Power supply scheme.
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains
Doc ID 13587 Rev 13 |
15/99 |
Description |
STM32F103x8, STM32F103xB |
|
|
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●MR is used in the nominal regulation mode (Run)
●LPR is used in the Stop mode
●Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.
2.3.12Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
●Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
●Stop mode
The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.
●Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note: |
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop |
|
or Standby mode. |
16/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
Description |
|
|
2.3.13DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC.
2.3.14RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
The medium-density STM32F103xx performance line devices include an advanced-control timer, three general-purpose timers, two watchdog timers and a SysTick timer.
Table 4 compares the features of the advanced-control and general-purpose timers.
Table 4. |
Timer feature comparison |
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Timer |
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Counter |
Counter |
Prescaler |
DMA request |
Capture/compare |
Complementary |
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resolution |
type |
factor |
generation |
channels |
outputs |
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Up, |
Any integer |
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TIM1 |
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16-bit |
down, |
between 1 |
Yes |
4 |
Yes |
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up/down |
and 65536 |
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TIM2, |
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Up, |
Any integer |
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TIM3, |
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16-bit |
down, |
between 1 |
Yes |
4 |
No |
TIM4 |
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up/down |
and 65536 |
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|
Doc ID 13587 Rev 13 |
17/99 |
Description |
STM32F103x8, STM32F103xB |
|
|
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for
●Input capture
●Output compare
●PWM generation (edgeor center-aligned modes)
●One-pulse mode output
If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are up to three synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.
The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardwareor software-configurable through the option bytes. The counter can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
18/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
Description |
|
|
SysTick timer
This timer is dedicated for OS, but could also be used as a standard downcounter. It features:
●A 24-bit downcounter
●Autoreload capability
●Maskable system interrupt generation when the counter reaches 0
●Programmable clock source
2.3.16I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.
The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator).
Doc ID 13587 Rev 13 |
19/99 |
Description |
STM32F103x8, STM32F103xB |
|
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2.3.21GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current- capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
2.3.22ADC (analog-to-digital converter)
Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
●Simultaneous sample and hold
●Interleaved sample and hold
●Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers.
The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value.
2.3.24Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
20/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
Pinouts and pin description |
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A |
PC14- |
PC13- |
PE2 |
PB9 |
PB7 |
PB4 |
PB3 |
PA15 |
PA14 |
PA13 |
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PC15- |
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PE3 |
PB8 |
PB6 |
PD5 |
PD2 |
PC11 |
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OSC32_OUT VBAT |
PC10 |
PA12 |
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C |
OSC_IN |
VSS_5 |
PE4 |
PE1 |
PB5 |
PD6 |
PD3 |
PC12 |
PA9 |
PA11 |
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D |
OSC_OUT VDD_5 |
PE5 |
PE0 |
BOOT0 |
PD7 |
PD4 |
PD0 |
PA8 |
PA10 |
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E |
NRST |
PC2 |
PE6 |
VSS_4 |
VSS_3 |
VSS_2 |
VSS_1 |
PD1 |
PC9 |
PC7 |
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F |
PC0 |
PC1 |
PC3 |
VDD_4 |
VDD_3 |
VDD_2 |
VDD_1 |
NC |
PC8 |
PC6 |
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G |
VSSA |
PA0-WKUP |
PA4 |
PC4 |
PB2 |
PE10 |
PE14 |
PB15 |
PD11 |
PD15 |
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H |
VREF– |
PA1 |
PA5 |
PC5 |
PE7 |
PE11 |
PE15 |
PB14 |
PD10 |
PD14 |
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J |
VREF+ |
PA2 |
PA6 |
PB0 |
PE8 |
PE12 |
PB10 |
PB13 |
PD9 |
PD13 |
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K |
VDDA |
PA3 |
PA7 |
PB1 |
PE9 |
PE13 |
PB11 |
PB12 |
PD8 |
PD12 |
AI16001c
Doc ID 13587 Rev 13 |
21/99 |
Pinouts and pin description |
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STM32F103x8, STM32F103xB |
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Figure 4. STM32F103xx performance line LQFP100 pinout |
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VDD 3 |
VSS 3 |
PE1 |
PE0 |
PB9 |
PB8 |
BOOT0 |
PB7 |
PB6 |
PB5 |
PB4 |
PB3 |
PD7 |
PD6 |
PD5 |
PD4 |
PD3 |
PD2 |
PD1 |
PD0 |
PC12 |
PC11 |
PC10 |
PA15 |
PA14 |
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PE2 |
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99 |
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97 |
96 |
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VDD_2 |
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PE3 |
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VSS_2 |
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PE4 |
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NC |
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PE5 |
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72 |
PA 13 |
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PE6 |
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PA 12 |
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VBAT |
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PA 11 |
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PC13-TAMPER-RTC 7 |
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PA 10 |
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PC14-OSC32_IN |
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PA 9 |
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PC15-OSC32_OUT |
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PA 8 |
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VSS_5 |
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PC9 |
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VDD_5 |
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PC8 |
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OSC_IN |
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LQFP100 |
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PC7 |
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OSC_OUT |
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PC6 |
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NRST |
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62 |
PD15 |
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PC0 |
15 |
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61 |
PD14 |
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PC1 |
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60 |
PD13 |
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PC2 |
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PD12 |
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PC3 |
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PD11 |
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VSSA |
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PD10 |
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VREF- |
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56 |
PD9 |
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VREF+ |
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55 |
PD8 |
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VDDA |
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54 |
PB15 |
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PA0-WKUP |
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53 |
PB14 |
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PA1 |
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52 |
PB13 |
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PA2 |
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51 |
PB12 |
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27 |
28 |
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30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
39 |
40 |
41 |
42 |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
50 |
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PA3 |
VSS 4 |
VDD 4 |
PA4 |
PA5 |
PA6 |
PA7 |
PC4 |
PC5 |
PB0 |
PB1 |
PB2 |
PE7 |
PE8 |
PE9 |
PE10 |
PE11 |
PE12 |
PE13 |
PE14 |
PE15 |
PB10 |
PB11 |
VSS 1 |
VDD 1 |
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ai14391 |
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22/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
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Pinouts and pin description |
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Figure 5. STM32F103xx performance line LQFP64 pinout |
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VDD 3 |
VSS 3 |
PB9 |
PB8 |
BOOT0 |
PB7 |
PB6 PB5 PB4 PB3 |
PD2 |
PC12 |
PC11 |
PC10 |
PA15 |
PA14 |
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VBAT |
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VDD_2 |
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PC13-TAMPER-RTC |
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VSS_2 |
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PC14-OSC32_IN |
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PA13 |
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PC15-OSC32_OUT |
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PA12 |
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PD0 OSC_IN |
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PA11 |
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PA10 |
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NRST |
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PA9 |
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PC0 |
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LQFP64 |
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PA8 |
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PC1 |
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PC9 |
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PC2 |
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PC8 |
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PC3 |
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PC7 |
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VSSA |
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PC6 |
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VDDA |
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PB15 |
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PA0-WKUP |
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PB14 |
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PA1 |
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PB13 |
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PA2 |
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PB12 |
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PA3 |
VSS 4 |
VDD 4 |
PA4 |
PA5 |
PA6 |
PA7 PC4 PC5 PB0 |
PB1 |
PB2 |
PB10 |
PB11 |
VSS 1 |
VDD 1 |
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ai14392 |
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Doc ID 13587 Rev 13 |
23/99 |
Pinouts and pin description |
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STM32F103x8, STM32F103xB |
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Figure 6. STM32F103xx performance line TFBGA64 ballout |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
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A |
PC14- |
PC13- |
PB9 |
PB4 |
PB3 |
PA15 |
PA14 |
PA13 |
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OSC32_INTAMPER-RTC |
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B |
PC15- |
VBAT |
PB8 |
BOOT0 |
PD2 |
PC11 |
PC10 |
PA12 |
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OSC32_OUT |
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C |
OSC_IN |
VSS_4 |
PB7 |
PB5 |
PC12 |
PA10 |
PA9 |
PA11 |
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D |
OSC_OUT VDD_4 |
PB6 |
VSS_3 |
VSS_2 |
VSS_1 |
PA8 |
PC9 |
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E |
NRST |
PC1 |
PC0 |
VDD_3 |
VDD_2 |
VDD_1 |
PC7 |
PC8 |
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F |
VSSA |
PC2 |
PA2 |
PA5 |
PB0 |
PC6 |
PB15 |
PB14 |
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G |
VREF+ PA0-WKUP |
PA3 |
PA6 |
PB1 |
PB2 |
PB10 |
PB13 |
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H |
VDDA |
PA1 |
PA4 |
PA7 |
PC4 |
PC5 |
PB11 |
PB12 |
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AI15494 |
24/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
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Pinouts and pin description |
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Figure 7. STM32F103xx performance line LQFP48 pinout |
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VDD 3 |
VSS 3 |
PB9 PB8 |
BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 |
PA14 |
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VBAT |
48 47 46 45 |
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VDD_2 |
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PC13-TAMPER-RTC |
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VSS_2 |
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PC14-OSC32_IN |
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34 |
PA13 |
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PC15-OSC32_OUT |
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33 |
PA12 |
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PD0-OSC_IN |
5 |
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32 |
PA11 |
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PD1-OSC_OUT |
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LQFP48 |
31 |
PA10 |
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NRST |
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30 |
PA9 |
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VSSA |
8 |
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29 |
PA8 |
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VDDA |
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28 |
PB15 |
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PA0-WKUP |
10 |
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27 |
PB14 |
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PA1 |
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26 |
PB13 |
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PA2 |
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PB12 |
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PA3 |
PA4 |
PA5 PA6 |
PA7 PB0 PB1 PB2 PB10 PB11 VSS 1 |
VDD 1 |
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ai14393b |
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VDD_3 |
VSS_3 |
PB9 |
PB8 BOOT0 PB7 PB6 PB5 |
PB4 |
PB3 PA15 |
PA14 |
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VBAT |
48 47 46 45 44 43 42 41 40 39 38 37 |
VDD_2 |
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PC13-TAMPER-RTC |
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35 |
VSS_2 |
PC14-OSC32_IN |
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34 |
PA13 |
PC15-OSC32_OUT |
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33 |
PA12 |
PD0-OSC_IN |
5 |
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32 |
PA11 |
PD1-OSC_OUT |
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VFQFPN48 |
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31 |
PA10 |
7 |
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30 |
PA9 |
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NRST |
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VSSA |
8 |
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29 |
PA8 |
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VDDA |
9 |
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28 |
PB15 |
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27 |
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PA0-WKUP |
10 |
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PB14 |
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26 |
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PA1 |
11 |
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PB13 |
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12 |
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25 |
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PA2 |
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PB12 |
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13 14 15 16 17 18 19 20 21 22 23 24 |
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PA3 |
PA4 |
PA5 |
PA6 PA7 PB0 PB1 PB2 |
PB10 |
PB11 VSS_1 |
VDD_1 |
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ai18300 |
Doc ID 13587 Rev 13 |
25/99 |
Pinouts and pin description |
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STM32F103x8, STM32F103xB |
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Figure 9. STM32F103xx performance line VFQFPN36 pinout |
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V |
BOOT0 |
PB7 |
PB6 |
PB5 |
PB4 |
PB3 |
PA15 |
PA14 |
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SS3 |
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36 |
35 |
34 |
33 |
32 |
31 |
30 |
29 |
28 |
|
VDD_3 |
1 |
|
|
|
|
|
|
|
27 |
VDD_2 |
OSC_IN/PD0 |
2 |
|
|
|
|
|
|
|
26 |
VSS_2 |
OSC_OUT/PD1 |
3 |
|
|
|
|
|
|
|
25 |
PA13 |
NRST |
4 |
|
|
|
|
|
|
|
24 |
PA12 |
VSSA |
5 |
|
|
|
QFN36 |
|
|
|
23 |
PA11 |
|
|
|
|
|
|
|
||||
VDDA |
6 |
|
|
|
|
|
|
|
22 |
PA10 |
PA0-WKUP |
7 |
|
|
|
|
|
|
|
21 |
PA9 |
PA1 |
8 |
|
|
|
|
|
|
|
20 |
PA8 |
PA2 |
9 |
|
|
|
|
|
|
|
19 |
VDD_1 |
|
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
|
|
PA3 |
PA4 |
PA5 |
PA6 |
PA7 |
PB0 |
PB1 |
PB2 |
SS 1 |
|
|
|
|
|
|
|
|
|
|
V |
|
|
|
|
|
|
|
|
|
|
|
ai14654 |
26/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
|
|
|
Pinouts and pin description |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
Table 5. |
Medium-density STM32F103xx pin definitions |
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pins |
|
|
|
|
|
|
Alternate functions(4) |
||
|
|
|
|
|
|
|
Type |
O/I Level |
|
|
|
LFBGA100 |
LQFP48/VFQFPN48 |
TFBGA64 |
LQFP64 |
LQFP100 |
VFQFPN36 |
|
|
|
|
||
|
|
|
|
|
|
|
(1) |
(2) |
Main |
|
|
|
|
|
|
|
|
Pin name |
|
|
function(3) |
Default |
Remap |
|
|
|
|
|
|
|
|
|
(after reset) |
||
|
|
|
|
|
|
|
|
|
|
|
|
A3 |
- |
|
- |
1 |
- |
PE2 |
I/O |
FT |
PE2 |
TRACECK |
|
|
|
|
|
|
|
|
|
|
|
|
|
B3 |
- |
|
- |
2 |
- |
PE3 |
I/O |
FT |
PE3 |
TRACED0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
C3 |
- |
|
- |
3 |
- |
PE4 |
I/O |
FT |
PE4 |
TRACED1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
D3 |
- |
|
- |
4 |
- |
PE5 |
I/O |
FT |
PE5 |
TRACED2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
E3 |
- |
|
- |
5 |
- |
PE6 |
I/O |
FT |
PE6 |
TRACED3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
B2 |
1 |
B2 |
1 |
6 |
- |
VBAT |
S |
|
VBAT |
|
|
A2 |
2 |
A2 |
2 |
7 |
- |
PC13-TAMPER- |
I/O |
|
PC13(6) |
TAMPER-RTC |
|
RTC(5) |
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
A1 |
3 |
A1 |
3 |
8 |
- |
PC14-OSC32_IN(5) |
I/O |
|
PC14(6) |
OSC32_IN |
|
B1 |
4 |
B1 |
4 |
9 |
- |
PC15- |
I/O |
|
PC15(6) |
OSC32_OUT |
|
OSC32_OUT(5) |
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
C2 |
- |
- |
- |
10 |
- |
VSS_5 |
S |
|
VSS_5 |
|
|
D2 |
- |
- |
- |
11 |
- |
VDD_5 |
S |
|
VDD_5 |
|
|
C1 |
5 |
C1 |
5 |
12 |
2 |
OSC_IN |
I |
|
OSC_IN |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D1 |
6 |
D1 |
6 |
13 |
3 |
OSC_OUT |
O |
|
OSC_OUT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
E1 |
7 |
E1 |
7 |
14 |
4 |
NRST |
I/O |
|
NRST |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
F1 |
- |
E3 |
8 |
15 |
- |
PC0 |
I/O |
|
PC0 |
ADC12_IN10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
F2 |
- |
E2 |
9 |
16 |
- |
PC1 |
I/O |
|
PC1 |
ADC12_IN11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
E2 |
- |
F2 |
10 |
17 |
- |
PC2 |
I/O |
|
PC2 |
ADC12_IN12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
F3 |
- |
-(7) |
11 |
18 |
- |
PC3 |
I/O |
|
PC3 |
ADC12_IN13 |
|
G1 |
8 |
F1 |
12 |
19 |
5 |
VSSA |
S |
|
VSSA |
|
|
H1 |
- |
- |
- |
20 |
- |
VREF- |
S |
|
VREF- |
|
|
J1 |
- |
G1(7) |
- |
21 |
- |
VREF+ |
S |
|
VREF+ |
|
|
K1 |
9 |
H1 |
13 |
22 |
6 |
VDDA |
S |
|
VDDA |
|
|
|
|
|
|
|
|
|
|
|
|
WKUP/ |
|
G2 |
10 |
G2 |
14 |
23 |
7 |
PA0-WKUP |
I/O |
|
PA0 |
USART2_CTS(8)/ |
|
|
ADC12_IN0/ |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TIM2_CH1_ETR(8) |
|
|
|
|
|
|
|
|
|
|
|
USART2_RTS(8)/ |
|
H2 |
11 |
H2 |
15 |
24 |
8 |
PA1 |
I/O |
|
PA1 |
ADC12_IN1/ |
|
|
|
|
|
|
|
|
|
|
|
TIM2_CH2(8) |
|
Doc ID 13587 Rev 13 |
27/99 |
Pinouts and pin description |
|
|
|
|
STM32F103x8, STM32F103xB |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 5. |
Medium-density STM32F103xx pin definitions (continued) |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pins |
|
|
|
|
|
|
|
Alternate functions(4) |
||
|
|
|
|
|
|
|
|
Type |
O/I Level |
|
|
|
LFBGA100 |
LQFP48/VFQFPN48 |
TFBGA64 |
LQFP64 |
LQFP100 |
VFQFPN36 |
|
|
|
|
|
||
|
|
|
|
|
|
|
|
(1) |
(2) |
Main |
|
|
|
|
|
|
|
|
|
Pin name |
|
|
function(3) |
Default |
Remap |
|
|
|
|
|
|
|
|
|
|
(after reset) |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
USART2_TX(8)/ |
|
J2 |
12 |
F3 |
16 |
25 |
9 |
|
PA2 |
I/O |
|
PA2 |
ADC12_IN2/ |
|
|
|
|
|
|
|
|
|
|
|
|
TIM2_CH3(8) |
|
|
|
|
|
|
|
|
|
|
|
|
USART2_RX(8)/ |
|
K2 |
13 |
G3 |
17 |
26 |
10 |
|
PA3 |
I/O |
|
PA3 |
ADC12_IN3/ |
|
|
|
|
|
|
|
|
|
|
|
|
TIM2_CH4(8) |
|
E4 |
- |
C2 |
18 |
27 |
- |
|
VSS_4 |
S |
|
VSS_4 |
|
|
F4 |
- |
D2 |
19 |
28 |
- |
|
VDD_4 |
S |
|
VDD_4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI1_NSS(8)/ |
|
G3 |
14 |
H3 |
20 |
29 |
11 |
|
PA4 |
I/O |
|
PA4 |
USART2_CK(8)/ |
|
|
|
|
|
|
|
|
|
|
|
|
ADC12_IN4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H3 |
15 |
F4 |
21 |
30 |
12 |
|
PA5 |
I/O |
|
PA5 |
SPI1_SCK(8)/ |
|
|
|
ADC12_IN5 |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI1_MISO(8)/ |
|
J3 |
16 |
G4 |
22 |
31 |
13 |
|
PA6 |
I/O |
|
PA6 |
ADC12_IN6/ |
TIM1_BKIN |
|
|
|
|
|
|
|
|
|
|
|
TIM3_CH1(8) |
|
|
|
|
|
|
|
|
|
|
|
|
SPI1_MOSI(8)/ |
|
K3 |
17 |
H4 |
23 |
32 |
14 |
|
PA7 |
I/O |
|
PA7 |
ADC12_IN7/ |
TIM1_CH1N |
|
|
|
|
|
|
|
|
|
|
|
TIM3_CH2(8) |
|
G4 |
- |
H5 |
24 |
33 |
|
|
PC4 |
I/O |
|
PC4 |
ADC12_IN14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H4 |
- |
H6 |
25 |
34 |
|
|
PC5 |
I/O |
|
PC5 |
ADC12_IN15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
J4 |
18 |
F5 |
26 |
35 |
15 |
|
PB0 |
I/O |
|
PB0 |
ADC12_IN8/ |
TIM1_CH2N |
|
|
TIM3_CH3(8) |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
K4 |
19 |
G5 |
27 |
36 |
16 |
|
PB1 |
I/O |
|
PB1 |
ADC12_IN9/ |
TIM1_CH3N |
|
|
TIM3_CH4(8) |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
G5 |
20 |
G6 |
28 |
37 |
17 |
|
PB2 |
I/O |
FT |
PB2/BOOT1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H5 |
- |
- |
- |
38 |
- |
|
PE7 |
I/O |
FT |
PE7 |
|
TIM1_ETR |
|
|
|
|
|
|
|
|
|
|
|
|
|
J5 |
- |
- |
- |
39 |
- |
|
PE8 |
I/O |
FT |
PE8 |
|
TIM1_CH1N |
|
|
|
|
|
|
|
|
|
|
|
|
|
K5 |
- |
- |
- |
40 |
- |
|
PE9 |
I/O |
FT |
PE9 |
|
TIM1_CH1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
G6 |
- |
- |
- |
41 |
- |
|
PE10 |
I/O |
FT |
PE10 |
|
TIM1_CH2N |
|
|
|
|
|
|
|
|
|
|
|
|
|
H6 |
- |
- |
- |
42 |
- |
|
PE11 |
I/O |
FT |
PE11 |
|
TIM1_CH2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
J6 |
- |
- |
- |
43 |
- |
|
PE12 |
I/O |
FT |
PE12 |
|
TIM1_CH3N |
|
|
|
|
|
|
|
|
|
|
|
|
|
K6 |
- |
- |
- |
44 |
- |
|
PE13 |
I/O |
FT |
PE13 |
|
TIM1_CH3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
G7 |
- |
- |
- |
45 |
- |
|
PE14 |
I/O |
FT |
PE14 |
|
TIM1_CH4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
28/99 |
Doc ID 13587 Rev 13 |
STM32F103x8, STM32F103xB |
|
|
|
|
Pinouts and pin description |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 5. |
Medium-density STM32F103xx pin definitions (continued) |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pins |
|
|
|
|
|
|
|
Alternate functions(4) |
||
|
|
|
|
|
|
|
|
Type |
O/I Level |
|
|
|
LFBGA100 |
LQFP48/VFQFPN48 |
TFBGA64 |
LQFP64 |
LQFP100 |
VFQFPN36 |
|
|
|
|
|
||
|
|
|
|
|
|
|
|
(1) |
(2) |
Main |
|
|
|
|
|
|
|
|
|
Pin name |
|
|
function(3) |
Default |
Remap |
|
|
|
|
|
|
|
|
|
|
(after reset) |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
H7 |
- |
- |
- |
46 |
- |
|
PE15 |
I/O |
FT |
PE15 |
|
TIM1_BKIN |
|
|
|
|
|
|
|
|
|
|
|
|
|
J7 |
21 |
G7 |
29 |
47 |
- |
|
PB10 |
I/O |
FT |
PB10 |
I2C2_SCL/ |
TIM2_CH3 |
|
USART3_TX(8) |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
K7 |
22 |
H7 |
30 |
48 |
- |
|
PB11 |
I/O |
FT |
PB11 |
I2C2_SDA/ |
TIM2_CH4 |
|
USART3_RX(8) |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
E7 |
23 |
D6 |
31 |
49 |
18 |
|
VSS_1 |
S |
|
VSS_1 |
|
|
F7 |
24 |
E6 |
32 |
50 |
19 |
|
VDD_1 |
S |
|
VDD_1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI2_NSS/ |
|
K8 |
25 |
H8 |
33 |
51 |
- |
|
PB12 |
I/O |
FT |
PB12 |
I2C2_SMBAl/ |
|
|
USART3_CK(8)/ |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TIM1_BKIN(8) |
|
|
|
|
|
|
|
|
|
|
|
|
SPI2_SCK/ |
|
J8 |
26 |
G8 |
34 |
52 |
- |
|
PB13 |
I/O |
FT |
PB13 |
USART3_CTS(8)/ |
|
|
|
|
|
|
|
|
|
|
|
|
TIM1_CH1N (8) |
|
|
|
|
|
|
|
|
|
|
|
|
SPI2_MISO/ |
|
H8 |
27 |
F8 |
35 |
53 |
- |
|
PB14 |
I/O |
FT |
PB14 |
USART3_RTS(8) |
|
|
|
|
|
|
|
|
|
|
|
|
TIM1_CH2N (8) |
|
G8 |
28 |
F7 |
36 |
54 |
- |
|
PB15 |
I/O |
FT |
PB15 |
SPI2_MOSI/ |
|
|
TIM1_CH3N(8) |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
K9 |
- |
- |
- |
55 |
- |
|
PD8 |
I/O |
FT |
PD8 |
|
USART3_TX |
|
|
|
|
|
|
|
|
|
|
|
|
|
J9 |
- |
- |
- |
56 |
- |
|
PD9 |
I/O |
FT |
PD9 |
|
USART3_RX |
|
|
|
|
|
|
|
|
|
|
|
|
|
H9 |
- |
- |
- |
57 |
- |
|
PD10 |
I/O |
FT |
PD10 |
|
USART3_CK |
|
|
|
|
|
|
|
|
|
|
|
|
|
G9 |
- |
- |
- |
58 |
- |
|
PD11 |
I/O |
FT |
PD11 |
|
USART3_CTS |
|
|
|
|
|
|
|
|
|
|
|
|
|
K10 |
- |
- |
- |
59 |
- |
|
PD12 |
I/O |
FT |
PD12 |
|
TIM4_CH1 / |
|
|
USART3_RTS |
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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J10 |
- |
- |
- |
60 |
- |
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PD13 |
I/O |
FT |
PD13 |
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TIM4_CH2 |
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H10 |
- |
- |
- |
61 |
- |
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PD14 |
I/O |
FT |
PD14 |
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TIM4_CH3 |
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G10 |
- |
- |
- |
62 |
- |
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PD15 |
I/O |
FT |
PD15 |
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TIM4_CH4 |
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F10 |
- |
F6 |
37 |
63 |
- |
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PC6 |
I/O |
FT |
PC6 |
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TIM3_CH1 |
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E10 |
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E7 |
38 |
64 |
- |
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PC7 |
I/O |
FT |
PC7 |
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TIM3_CH2 |
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F9 |
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E8 |
39 |
65 |
- |
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PC8 |
I/O |
FT |
PC8 |
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TIM3_CH3 |
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E9 |
- |
D8 |
40 |
66 |
- |
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PC9 |
I/O |
FT |
PC9 |
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TIM3_CH4 |
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D9 |
29 |
D7 |
41 |
67 |
20 |
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PA8 |
I/O |
FT |
PA8 |
USART1_CK/ |
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TIM1_CH1(8)/MCO |
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Doc ID 13587 Rev 13 |
29/99 |
Pinouts and pin description |
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STM32F103x8, STM32F103xB |
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Table 5. |
Medium-density STM32F103xx pin definitions (continued) |
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Pins |
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Alternate functions(4) |
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Type |
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O/I Level |
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LFBGA100 |
LQFP48/VFQFPN48 |
TFBGA64 |
LQFP64 |
LQFP100 |
VFQFPN36 |
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(1) |
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(2) |
Main |
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Pin name |
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function(3) |
Default |
Remap |
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(after reset) |
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C9 |
30 |
C7 |
42 |
68 |
21 |
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PA9 |
I/O |
FT |
PA9 |
USART1_TX(8)/ |
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TIM1_CH2(8) |
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D10 |
31 |
C6 |
43 |
69 |
22 |
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PA10 |
I/O |
FT |
PA10 |
USART1_RX(8)/ |
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TIM1_CH3(8) |
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USART1_CTS/ |
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C10 |
32 |
C8 |
44 |
70 |
23 |
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PA11 |
I/O |
FT |
PA11 |
CANRX(8)/ USBDM |
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TIM1_CH4(8) |
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USART1_RTS/ |
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B10 |
33 |
B8 |
45 |
71 |
24 |
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PA12 |
I/O |
FT |
PA12 |
CANTX(8) //USBDP |
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TIM1_ETR(8) |
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A10 |
34 |
A8 |
46 |
72 |
25 |
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PA13 |
I/O |
FT |
JTMS/SWDIO |
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PA13 |
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F8 |
- |
- |
- |
73 |
- |
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Not connected |
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E6 |
35 |
D5 |
47 |
74 |
26 |
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VSS_2 |
S |
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VSS_2 |
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F6 |
36 |
E5 |
48 |
75 |
27 |
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VDD_2 |
S |
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VDD_2 |
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A9 |
37 |
A7 |
49 |
76 |
28 |
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PA14 |
I/O |
FT |
JTCK/SWCLK |
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PA14 |
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A8 |
38 |
A6 |
50 |
77 |
29 |
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PA15 |
I/O |
FT |
JTDI |
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TIM2_CH1_ETR/ |
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PA15 /SPI1_NSS |
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B9 |
- |
B7 |
51 |
78 |
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PC10 |
I/O |
FT |
PC10 |
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USART3_TX |
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B8 |
- |
B6 |
52 |
79 |
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PC11 |
I/O |
FT |
PC11 |
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USART3_RX |
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C8 |
- |
C5 |
53 |
80 |
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PC12 |
I/O |
FT |
PC12 |
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USART3_CK |
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D8 |
5 |
C1 |
5 |
81 |
2 |
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PD0 |
I/O |
FT |
OSC_IN(9) |
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CANRX |
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E8 |
6 |
D1 |
6 |
82 |
3 |
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PD1 |
I/O |
FT |
OSC_OUT(9) |
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CANTX |
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B7 |
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B5 |
54 |
83 |
- |
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PD2 |
I/O |
FT |
PD2 |
TIM3_ETR |
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C7 |
- |
- |
- |
84 |
- |
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PD3 |
I/O |
FT |
PD3 |
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USART2_CTS |
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D7 |
- |
- |
- |
85 |
- |
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PD4 |
I/O |
FT |
PD4 |
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USART2_RTS |
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B6 |
- |
- |
- |
86 |
- |
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PD5 |
I/O |
FT |
PD5 |
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USART2_TX |
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C6 |
- |
- |
- |
87 |
- |
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PD6 |
I/O |
FT |
PD6 |
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USART2_RX |
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D6 |
- |
- |
- |
88 |
- |
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PD7 |
I/O |
FT |
PD7 |
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USART2_CK |
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TIM2_CH2 / PB3 |
A7 |
39 |
A5 |
55 |
89 |
30 |
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PB3 |
I/O |
FT |
JTDO |
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TRACESWO |
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SPI1_SCK |
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A6 |
40 |
A4 |
56 |
90 |
31 |
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PB4 |
I/O |
FT |
JNTRST |
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TIM3_CH1/ PB4/ |
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SPI1_MISO |
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30/99 |
Doc ID 13587 Rev 13 |