ST STLC2410B User Manual
1 FEATURES
■ Bluetooth
■ Point-to-point, point-to-multi-point (up to 7
®
V1.1 specification compliant
slaves) and scatternet capability
■ Asynchronous Connection-Less (ACL) link
support giving data rates up to 721kbps
■ Synchronous Connection-Oriented (SCO) link
■ Standard BlueRF bus interface
■ ARM7TDMI CPU
– 32-bit Core
– Run from 13MHz external clock
– Support of 32 kHz crystal for low power mode
■ Memory organization
– 64KByte on-chip RAM
– 4KByte on-chip boot ROM
– Programmable external memory interface (EMI)
– 8-bit or 16-bit external data bus
– Up to 3 programmable chip-select signals
– Hold-acknowledge bus arbitration support
■ HW support for all packet types
– ACL: DM1, 3, 5 and DH1, 3, 5
– SCO: HV1, 2, 3 and DV1
■ Communication interfaces
– Serial Synchronous Interface
– Two enhanced 16550 UART's with 128 byte
fifo depth
– 12Mbps USB interface
– Fast master I2C bus interface
– Multi slot PCM interface
– 16 programmable GPIO
– 2 external interrupts and various interrupt
possibilities through other interfaces
■ Ciphering support for up to 128-bit key
■ Receiver Signal Strenght Indication (RSSI)
support for power-controlled links
■ Separate control for external power amplifier
(PA) for power class1 support.
■ Software support
– Low level (up to HCI) stack or embedded
stack with profiles
– Support of UART and USB HCI transport layers
■ Idle and power down modes
– Ultra low power in idle mode
– Low standby current
STLC2410B
BLUETOOTH® BASEBAND
TFBGA132 (8x8x1.2mm)
ORDERING NUMBER: STLC2410B
Temperature range: -40 to +85 °C
■ Extended temperature range
■
Compliant to automotive specification AEC-Q100
1.1 Applications Features
Typical applications in which the STLC2410B can
be used are:
■ Portable computers, PDA
■ Modems
■ Handheld data transfer devices
■ Cameras
■ Computer peripherals
■ Other type of devices that require the wireless
communication provided by Bluetooth
■ Cable replacement
2 DESCRIPTION
The STLC2410B offers a compact and complete
solution for short-range wireless connectivity. It incorporates all the lower layer functions of the Blue-
®
tooth
protocol.
The microcontroller allows the support of all data
packets of Bluetooth
bedded controller can be used to run the Blue-
®
tooth
protocol and application layers if required.
®
in addition to voice. The em-
The software is located in an external memory accessed through the external memory interface.
®
January 2004
Rev. 2.0
1/20
STLC2410B
3 QUICK REFERENCE DATA
3.1 Absolute Maximum Ratings
Operation of the device beyond these conditions is not guaranteed.
Sustained exposure to these limits will adversely affect device reliability
Table 1. Absolute Maximum Ratings
Symbol Conditions Min Max Unit
V
DD
V
DDIO
V
IN
T
amb
T
stg
T
lead
3.2 Operating Ranges
Operating ranges define the limits for functional operation and parametric characteristics of the device.
Functionality outside these limits is not implied.
Supply voltage core VSS - 0.5 2.5 V
Supply voltage I/O 4 V
input voltage on any digital pin VSS - 0.5 V
+ 0.3 V
DDIO
Operating ambient temperature -40 +85 °C
Storage temperature -65 +150 °C
Lead temperature < 10s +240 °C
Table 2. Operating Ranges
Symbol Conditions Min Typ Max Unit
V
T
V
DD
DDIO
amb
Supply voltage digital core and emi pads 1.55 1.8 1.95 V
Supply voltage digital IO 2.7 3.3 3.6 V
Operating ambient temperature -40 +85 °C
3.3 I/O specifications
Depending on the interface, the I/O voltage is typical 1.8V (interface to the flash memory) or typical 3.3V
(all the other interfaces). These I/Os comply to the EIA/JEDEC standard JESD8-B.
3.3.1 Specifications for 3.3V I/Os
Table 3. LVTTL DC Input Specification (3V<V
Symbol Parameter Conditions Min Typ Max Unit
V
V
V
hyst
Low level input voltage 0.8 V
il
High level input voltage 2 V
ih
Schmitt trigger hysteresis 0.4 V
Table 4. LVTTL DC Output Specification (3V<V
Symbol Parameter Conditions Min Typ Max Unit Note
V
V
Note 1 : X is the source/sink current under worst case conditions according to the drive capability. (See table 8, pad information for value of X).
Low level output voltage I
ol
High level output voltage Ioh =-X mA V
oh
ol
= X mA 0.15 V 1
<3.6V)
DDIO
<3.6V)
DDIO
-0.15 V 1
DDIO
2/20
3.3.2 Specifications for 1.8V I/Os
STLC2410B
Table 5. DC Input Specification (1.55V<V
<1.95V)
DD
Symbol Parameter Conditions Min Typ Max Unit
V
Low level input voltage 0.35*V
il
High level input voltage 0.65*V
V
ih
t Schmitt trigger hysteresis 0.2 0.3 0.5 V
V
hys
Table 6. DC Output Specification (1.55V<V
<1.95V)
DD
DD
DD
V
V
Symbol Parameter Conditions Min Typ Max Unit Note
V
V
Note 1 : X is the source/sink current under worst case conditions according to the drive capability. (See table 8, pad information for value of X).
Low level output voltage Iol = X mA 0.15 V 1
ol
High level output voltage Ioh =-X mA VDD-0.15 V 1
oh
3.4 Current Consumption
Table 7. Typical power consumption of the STLC2410B and External Flash using UART (VDD =
VDD Flash = PLLVDD = 1.8V, VDDIO = 3.3V)
STLC2410B State
Slave Master
Standby (no low power mode) 5.10 5.10 0.13 mA
Core
IO Unit
Standby (low power mode enabled) 0.94 0.94 0.13 mA
ACL connection (no transmission) 7.60 6.99 0.13 mA
ACL connection (data transmission) 7.90 7.20 0.13 mA
SCO connection (no codec connected) 8.70 7.90 0.14 mA
Inquiry and Page scan (low power mode enabled) 127 n.a. 5 µA
Low Power mode (32 kHz crystal) 20 20 0 µA
3/20
STLC2410B
Figure 1. Block Diagram and Electrical Schematic
JTAG
V
DD
5
100nF
V
DDIO
100nF
V
DDIO
100nF
RF BUS
13
RADIO
I/F
BLUETOOTH
®
CORE
ARM7
TDMI
D
RAM
M
A
(*)
22pF
22pF
LPOCLKP
Y2
32KHz
LPO
BOOT
ROM
LPOCLKN
V
DD
100nF
VDDPLL
XIN
4
BOOT WAIT
RD/WR
EMI
3 20 16
CSN(0..2) ADDR(0..19) DATA(0..15)
(*) If a low-power clock is available, it can be connected to the LPOCLKP pin in stead of using a crystal
APB
BRIDGE
TIMER
START
DETECT
UART
FIFO
INTERRUPT
CONTROLLER
SYSTEM
CONTROL
PCM
USB
I2C
SPI
GPIO
UART
UART
4
2
2
2
4
16
8
2
2
D02TL550
PCM
EXT._INT1/2
USB
2
I
C
SPI
GPIO(O..15)
UART2
UART1
RESET
SYS_CLK_REQ
V
DD
100nF
4/20
4PINOUT
Figure 2. Pinout (Bottom view)
12
13
14
gpio9 gpio11 gpio14 vddio brxd bmosi bdclk bpaen brxen ant_sw tdi ntrst test xin
n.c. gpio10 gpio13 n.c. brclk bnden btxd vdd btxen vddio tdo tck nreset
gpio8 vddpll gpio12
vsspll gpio6 gpio7
gpio3 gpio4 gpio5
gpio0 gpio1 gpio2
lpo_
boot
clk_p
data
data
14
15
data13data12data
data10data
9
vss
vdd vdd vssiospi_frm vddio
data8 data7 data6 data0 addr17 vss
data5 data4 data2
data3 n.c. data1
gpio15 vssio bmiso bsen vss bpktctl vssio tms
lpo_
clk_n
wait
11
vss vss
8
9
10
11
addr13 addr10
addr19 addr16
addr18 addr15 addr14 addr11
vdd addr12 addr9 addr6 addr3 vss csn2 wrn
1
2
3
4
5
6
7
sys_
clk_req
uart1_
uart1_
rxd
i2c_clk int1 int2
vddio vssio
pcm_
clk
uart2_
rxd
uart2_
i2
uart2_
io1
addr5 addr2 vdd csn1
addr8 addr7 addr4 addr1 addr0 csn0 rdn
i2c_
txd
dat
pcm_
sync
pcm_a pcm_b
usb_
usb_
dn
dp
uart2_
uart2_
txd
i1
uart2_
uart2_
o1
o2
uart2_
vdd
io2
spi_
spi_
txd
clk
spi_
rxd
D02TL551
STLC2410B
A
B
C
D
E
F
G
H
J
K
L
M
N
P
4.1 Pin Description and Assignment
Table4 : STLC2410B pinlist shows the pinout of STLC2410B; there are 107 digital functional pins and 22
supply pins. The column "PU/PD" shows the pads implementing an internal weak pull-up/down, to fix value
if the pin is left open. This can not replace an external pull-up/down.
The pads are grouped according to two different power supply values, as shown in column "VDD":
– V1 for 3.3 V typical 2.7 - 3.6 V range
– V2 for 1.8 V typical 1.55 - 1.95 V range
Finally the column "DIR" describes the pin directions:
– I for inputs
– O for outputs
– I/O for input/outputs
– O/t for tristate outputs
5/20
STLC2410B
Table 8. Pin List
Name Pin # Description DIR PU/PD VDD PAD
Interface to external memory
int1 D2 External Interrupt used also as external wakeup I
int2 D1
boot G14
Second external interrupt
Select external boot from EMI or internal from ROM
I
I
wait H12 EMI external wait signal (left open) I PD
rdn P1 External read O
wrn N2 External write O
csn0 P2 External chip select bank 0 O
csn1 M3 External chip select bank 1 O
csn2 N3 External chip select bank 2 O
addr0 P3 External address bit 0 O
addr1 P4 External address bit 1 O
addr2 M5 External address bit 2 O
addr3 N5 External address bit 3 O
addr4 P5 External address bit 4 O
addr5 M6 External address bit 5 O
addr6 N6 External address bit 6 O
addr7 P6 External address bit 7 O
addr8 P7 External address bit 8 O
addr9 N7 External address bit 9 O
addr10 M7 External address bit 10 O
addr11 P8 External address bit 11 O
addr12 N8 External address bit 12 O
addr13 M8 External address bit 13 O
addr14 P9 External address bit 14 O
addr15 P10 External address bit 15 O
addr16 N10 External address bit 16 O
addr17 M10 External address bit 17 O
addr18 P11 External address bit 18 O
addr19 N11 External address bit 19 O
data0 M11 External data bit 0 I/O PD
data1 P12 External data bit 1 I/O PD
data2 N12 External data bit 2 I/O PD
data3 P14 External data bit 3 I/O PD
data4 N13 External data bit 4 I/O PD
data5 N14 External data bit 5 I/O PD
(1)
(1)
(1)
CMOS, 3.3V TTL
V1
schmitt trigger
V2 CMOS 1.8V
V2
slew rate control
CMOS 1.8V 4mA
V2
slew rate control
compatible
CMOS 1.8V
4mA
6/20
Loading...