ST STLC2150 User Manual
STLC2150
BLUETOOTH® RADIO TRANSCEIVER
■ Bluetooth
■ Fully integrated single chip:
®
v.1.2 specification compliant
– transceiver with minimum of external RF
components
– PLL completely integrated
– Integrated antenna switch
■ Supports Power Class 2 and 3 operation with
power control
■ Supports Power Class 1 operation with an
external Power Amplifie
■ Outstanding maximum usable input signal
■ Interface with base-band:
– BlueRF compatible
– unidirectional
– received data: RxMode2 and RxMode2+ are
supported
– serial interface: JTAG
■ CMOS technology
■ Standard VFQFPN-48 package
■ Low standby power consumption
■ Extended temperature range
■
Compliant to automotive specification AEC-Q100
APPLICATIONS
■
Wireless data transmission applications to 432
Kbps symmetrical or 721 Kbps asymmetrical.
■
Typical applications in which the STLC2150 is
used are:
■
Computer peripherals
■
Modems
■
Cameras
■
Portable computers, PDA
■
Handheld data transfer devices
■
Mobile phone
■
Other types of devices that require the wireless
communication provided by Bluetooth
®
.
VFQFPN-48 (7x7x1.0mm)
ORDERING NUMBER: STLC2150
Temperature range: -40 to 85 °C
DESCRIPTION
The STLC2150 is a fully integrated
Bluetooth® single
chip radio transceiver. Together with a BB processor,
like STLC2410, it offers a compact and complete solution for short-range wireless connectivity for a variety of applications.
The STLC2150 implements a low-IF receiver for
Bluetooth® modulated input signals and no external
IF filtering is required. The GFSK demodulator is fully
integrated and supplies digital output data and RSSI.
The transmit section features a fully integrated GFSK
modulator, followed by a direct up-conversion stage,
giving an output signal of 0 dBm. Optional power control is available.
On-chip VCO covers full
Bluetooth® band and contains all of the tank resonator circuitry. Unidirectional
BlueRF compatible interface and 4 wires serial JTAG
interface are used to control all functions of radio
transceiver, enabling operation with wide range of BB
processors.
January 2004
Rev. 2.0
1/10
STLC2150
BLOCK DIAGRAM
LNA
MIX
IQ-
BPF
A/D
VGA
A/D
RX
DIGITAL
PA RT
BRXD
POWER & CLOCK
ANTENNA
PLL
& VCO
FILTER
CALIBRATION
CONTROL
SERIAL PROGRAM
INTERFACE
BLUE RF
LPF
PA
MIX
DAC
SYSTEM
MODULATOR
BTXD
LPF
QUICK REFERENCE DATA
Table 1. Absolute Maximum Ratings
Operation of the device beyond these conditions is not guaranteed.
Sustained exposure to these limits will adversely effect device reliability.
Symbol Conditions Min Max Unit
D02TL547
V
DD
Power supply Analogue and
VSS - 0.3 3.5 V
Digital Core
V
SSDIF
V
IN
Input voltage on any pin VSS - 0.3
Maximum voltage difference
-0.3 0.3 V
+ 0.3 AND < 3.5
V
DD
V
+ 0.3 AND < 4.6
DDIO
(*)
V
between different VSS* pins
V
DDIO
(*) Analogue test and RF pins only.
Power supply for digital I/O V
- 0.3 4.6 V
SS
Table 2. Operating Ranges
Operating ranges define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied.
Symbol Conditions Min Typ Max Unit
V
V
T
DD
DDIO
amb
Power supply Analogue and Digital
2.62 2.70 2.78 V
Core
Power supply for I/O 2.50 3.60 V
Ambient temperature -40 85 °C
2/10
STLC2150
Pin Description and Assignment
Pin# Pin Name Description Pin# Pin Name Description
1 VSS3 Analogue Ground 25 XTAL130
2 AOUTIP Analogue test output 26 XTAL13I 13 MHz Crystal oscillator input pin
3 AOUTIN Analogue test output 27 VDDXTAL 13 MHz oscillator supply
4 AOUTQP Analogue test output 28 VSS1 Analogue Ground
5 AOUTQN Analogue test output 29 VDD1 Analogue Supply
6 LPCLK 3.2 or 32 KHz clock output 30 VDD2 Analogue Supply
7 BDCLK JTAG TCK 31 VSS2 Analogue Ground
8 DVDD1 Digital Core Supply pin 32 VSS6 Analogue Ground
9 DVSS1 Digital Core Ground pin 33 VDD6 Analogue Supply
10 BNDEN JTAG TMS 34 VDD5 Analogue Supply
11 BMOSI JTAG TDI 35 VSS5 Analogue Ground
12 BMISO JTAG TDO 36 VDD7 Analogue Supply
13 RESETN Reset 37 VSS7 Analogue Ground
14 BXTLEN Oscillator enable 38 AINQN Analogue test input
15 BTXEN Tx path enable 39 AINQP Analogue test input
16 BRXEN Rx path enable 40 VDD4 Analogue Supply
17 IOVDD1 Digital IO Supply pin 41 VSS4 Analogue Ground
18 CLK13MHZ 13 MHz output 42 RF_N RF antenna connection
19 BTXD Tx data 43 RF_P RF antenna connection
20 BRCLK 1 MHz-clock associated with data 44 VSS4 Analogue Ground
21 OTP_ZAP OTP ZAP 45 VDD4 Analogue Supply
22 BPKTCTL
Access code successfully decoded
46 AININ Analogue test input
23 BRXD Rx data 47 AINIP Analogue test input
24 BSEN Synthesizer enable 48 VDD3 Analogue Supply
13 MHz Crystal oscillator output pin
PIN CONNECTION
(bottom view)
VDD7
VSS5
VDD5
VDD6
VSS6
VSS2
VDD2
VDD1
VSS1
VDDXTAL
XTAL13I
XTAL13O
VSS7
AINQN
AINQP
VDD4
VSS4
RF_N
RF_P
VSS4
VDD4
AININ
37 38 39 40 41 42 43 44 45 46 47 48
36
35
34
33
32
31
30
29
28
27
26
25
24 23 22 21 20 19 18 17 16 15 14 13
BSEN
BRXD
BPKTCTL
BRCLK
OTP_ZAP
BTXD
CLK13MHZ
IOVDD1
BTXEN
BRXEN
AINIP
VDD3
1 VSS3
2
3
4
5
6
7
8
9
10
11
12
BXTLEN
RESETN
AOUTIP
AOUTIN
AOUTQP
AOUTQN
LPCLK
BDCLK
DVDD1
DVSS1
BNDEN
BMOSI
BMISO
3/10
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