Datasheet ST1S32 Datasheet (ST)

4 A DC step-down switching regulator

VFDFPN 8 4x4x1.0

VINSW

SW

VFB

PG

GND

EN

ST1S32

Cin_sw

Cout

L

R1

R2

VINA

Cin_a R3

VOUT

VIN

AM12608V1

Features

■ 4 A DC output current

■ 2.8 V to 5.5 V input voltage

■ Output voltage adjustable from 0.8 V

■ 1.5 MHz switching frequency

■ Internal soft-start and enable

■ Integrated 60 mΩ and 45 mΩ Power MOSFETs

■ All ceramic capacitor

■ Power Good (POR)

■ Cycle-by-cycle current limiting

■ Current foldback short-circuit protection

■ VFDFPN 8 4x4x1.0 package

Applications

■ µP/ASIC/DSP/FPGA core and I/O supplies

■ Point of Load for: STB, TV, DVD

■ Optical storage, hard disk drives, printers,

audio/graphic cards

ST1S32

Datasheet — production data

Description

The ST1S32 is an internally compensated 1.5
MHz fixed-frequency PWM synchronous step­down regulator. The ST1S32 operates from 2.8 V
to 5.5 V input, while it regulates an output voltage
as low as 0.8 V and up to V

The ST1S32 integrates a 60 mΩ high-side switch
and a 45 mΩ synchronous rectifier, allowing very
high efficiency with very low output voltages.

The peak current mode control with internal
compensation delivers a very compact solution
with a minimum component count.

IN

.

Figure 1. Application circuit

May 2012 Doc ID 023246 Rev 1 1/29

This is information on a product in full production.

The ST1S32 is available in 4 mm x 4 mm, 8-lead
VFDFPN package.

www.st.com

29

Contents ST1S32

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4.1 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.4 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.5 Light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/29 Doc ID 023246 Rev 1

ST1S32 Pin settings

1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

1.2 Pin description

Table 1. Pin description

No. Type Description

1 VINA Unregulated DC input voltage.

2EN

3FB

4 AGND Ground.

5PG

6 VINSW Power input voltage.

7 SW Regulator output switching pin.

8 PGND Power Ground.

Enable input. With EN higher than 1.5 V the device in ON and with EN
lower than 0.5 V the device is OFF.

Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.8 V. To have higher regulated voltages an
external resistor divider is required from V

Open drain Power Good (POR) pin. It is released (open drain) when the
output voltage is higher than 0.92 * V
output voltage is below 0.92 * V
immediately.

If not used, it can be left floating or to GND.

OUT

to the FB pin.

OUT

with a delay of 170 us. If the

OUT

, the POR pin goes to low impedance

Doc ID 023246 Rev 1 3/29

Maximum ratings ST1S32

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V

IN

V

EN

V

SW

V

PG

V

FB

P

TOT

T

OP

T

stg

2.1 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

R

thJA

1. Package mounted on demonstration board.

Input voltage -0.3 to 7

Enable voltage -0.3 to V

Output switching voltage -1 to V

Power-on reset voltage (Power Good) -0.3 to V

IN

IN

IN

Feedback voltage -0.3 to 1.5

Power dissipation at TA < 60 °C 2.25 W

Operating junction temperature range -40 to 150 °C

Storage temperature range -55 to 150 °C

Maximum thermal resistance junction­ambient

(1)

40 °C/W

V

4/29 Doc ID 023246 Rev 1

ST1S32 Electrical characteristics

3 Electrical characteristics

TJ=25 °C, V

=5 V, unless otherwise specified.

IN

Table 4. Electrical characteristics

Symbol Parameter Test condition

Operating input voltage

IN

range

Turn-on VCC threshold

Turn-off VCC threshold

High-side switch on-

-P
resistance

Low-side switch on-

-N
resistance

Maximum limiting current

V

R

R

V

V

INON

INOFF

DSON

DSON

I

LIM

Oscillator

Switching frequency 1.2 1.5 1.9 MHz

Maximum duty cycle

D

F

MAX

SW

Dynamic characteristics

(1)

(1)

(1)

=300 mA 60 mΩ

I

SW

=300 mA 45 mΩ

I

SW

(2)

(2)

Val ues

Min. Typ. Max.

2.8 5.5

2.4

2.0

5.0 A

95 100 %

Unit

V

Feedback voltage

/

Reference load regulation Io=10 mA to 4 A

/

Reference line regulation VIN= 2.8 V to 5.5 V

IN

%V

ΔI

%V

V

ΔV

FB

OUT

OUT

OUT

DC characteristics

I

Q

I

QST-BY

Quiescent current

Total standby quiescent
current

Enable

V

EN

I

EN

EN threshold voltage

EN current 0.1 μA

0.792 0.8 0.808

Io=10 mA to 4 A

(1)

(2)

(2)

Duty cycle=0, no load

=1.2 V

V

FB

0.776 0.8 0.824

0.2 0.6 %

0.2 0.3 %

630 1200 μA

V

OFF 10 μA

Device ON level 1.5

V

Device OFF level 0.5

Doc ID 023246 Rev 1 5/29

Electrical characteristics ST1S32

Table 4. Electrical characteristics (continued)

Val ues

Symbol Parameter Test condition

Min. Typ. Max.

Power Good

Unit

PG threshold 92 %V

PG hystereris 30 50

PG

PG output voltage low Isink= 6 mA open drain 400

PG rise delay 170 μs

Soft-start

T

SS

Soft-start duration 400 μs

Protection

Thermal shutdown 150

T

SHDN

1. Specifications referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range
are assured by design, characterization and statistical correlation.

2. Guaranteed by design.

Hystereris 20

FB

mV

°C

6/29 Doc ID 023246 Rev 1

ST1S32 Functional description

4 Functional description

The ST1S32 is based on a “peak current mode”, constant frequency control. The output
voltage V
providing an error signal that, compared to the output of the current sense amplifier, controls
the ON and OFF time of the power switch.

The main internal blocks are shown in the block diagram in Figure 3. They are:

● A fully integrated oscillator that provides the internal clock and the ramp for the slope

compensation avoiding sub-harmonic instability

● The soft-start circuitry to limit inrush current during the startup phase

● The transconductance error amplifier

● The pulse width modulator and the relative logic circuitry necessary to drive the internal

power switches

● The drivers for embedded P-channel and N-channel Power MOSFET switches

● The high-side current sensing block

● The low-side current sense to implement diode emulation

● A voltage monitor circuitry (UVLO) that checks the input and internal voltages

● A thermal shutdown block, to prevent thermal run-away.

is sensed by the Feedback pin (FB) compared to an internal reference (0.8 V)

OUT

Figure 3. Block diagram

Doc ID 023246 Rev 1 7/29

Functional description ST1S32

4.1 Soft-start

The soft-start is essential to assure the correct and safe startup of the step-down converter.
It avoids inrush current surge and makes the output voltage rise monothonically.

The soft-start is managed by ramping the reference of the error amplifier from 0 V to 0.8 V.
The internal soft-start capacitor is charged with a resistor to 0.8 V, then the FB pin follows
the reference so that the output voltage is regulated to rise to the set value monothonically.

4.2 Error amplifier and control loop stability

The error amplifier provides the error signal to be compared with the high-side switch
current through the current sense circuitry. The non-inverting input is connected with the
internal 0.8 V reference, whilst the inverting input is the FB pin. The compensation network
is internal and connected between the E/A output and GND.

The error amplifier of the ST1S32 is a transconductance operational amplifier, with high
bandwidth and high output impedance.

The characteristics of the uncompensated error amplifier are:

Table 5. Characteristics of the uncompensated error amplifier

Description Value

DC gain 94 dB

gm 238 μA/V

Ro 96 MΩ

The ST1S32 embeds the compensation network that assures the stability of the loop in the
whole operating range. Here below are all the tools needed to check the loop stability.

In Figure 4. the simple small signal model for the peak current mode control loop is shown.

8/29 Doc ID 023246 Rev 1

ST1S32 Functional description

L

Cout

Current sense

Logic

And

Driver

Slope

Com pensati on

PW M comparator

Err or Amp

Rc

Cc

R1

R2

0.8 V

High side

Swi tch

Low si de

Swi tch

GCO(s)

G

DIV

(s)

G

EA

(s)

VIN

V

C

V

OUT

V

FB

AM12609V1

GCOs()

R

LOAD

R

i

------------ ------

1

1

R

outTSW

⋅

L

------------- ------------- ----

m

C

1D–()0.5–⋅[]⋅+

------------ ------------- ------------- ------------- ------------ --------------- ------------- ----------

1

s

ω

z

-----+

⎝⎠

⎛⎞

1

s

ω

p

-----+

⎝⎠

⎛⎞

------------ ---------

F

H

s()⋅⋅⋅=

ω

Z

1

ESR C

OUT

⋅

------------ ------------- ---------=

Figure 4. Block diagram of the loop for the small signal analysis

Three main terms can be identified to obtain the loop transfer function:

1. from control (output of E/A) to output, G

2. from output (V

) to the FB pin, G

OUT

DIV

3. from the FB pin to control (output of E/A), G

The transfer function from control to output G

CO

(s);

(s);

CO

(s).

EA

(s) results:

Equation 1

where R
current sense circuitry (0.369 Ω), ω
zero given by the ESR of the output capacitor.

F

(s) accounts for the sampling effect performed by the PWM comparator on the output of

H

the error amplifier that introduces a double pole at one half of the switching frequency.

Equation 2

represents the load resistance, Ri the equivalent sensing resistor of the

LOAD

the single pole introduced by the LC filter and ωz the

p

Doc ID 023246 Rev 1 9/29

Functional description ST1S32

ω

p

1

R

LOADCOUT

⋅

------------- ------------- --------------

m

C

1D–()0.5–⋅

LC

OUTfSW

⋅⋅

------------ ------------- ------------- ----------+=

mC1

S

e

S

n

------

+=

SeVppf

SW

⋅=

S

n

VINV

OUT

–

L

------------- ------------- --- -

Ri⋅=

⎝

⎜

⎜

⎜

⎜

⎜

⎜

⎛

FHs()

1

1

s

ω

nQP

⋅

------------ -------- -

s

2

ω

n

2

-----++

----------- ------------- ------------- ------=

Q

P

1

π m

C

1D–()0.5–⋅[]⋅

------------ ------------- ------------- ------------- -------------=

ωnπ fSW⋅=

G

DIV

s()

R

2

R1R2+

------------ --------=

Equation 3

where:

Equation 4

S

represents the ON-time slope of the sensed inductor current, Se the slope of the external

n

ramp (V

peak-to-peak amplitude - 0.535 V) that implements the slope compensation to

PP

avoid sub-harmonic oscillations at duty cycle over 50%.

The sampling effect contribution F

Equation 5

where:

Equation 6

and

Equation 7

The transfer function G

(s) from V

DIV

(s) is:

H

to FB results:

OUT

The transfer function from FB to Vc (output of E/A) introduces the singularities (poles and
zeroes) to stabilize the loop. In Figure 5, the small signal model of the error amplifier with the
internal compensation network is shown.

10/29 Doc ID 023246 Rev 1

ST1S32 Functional description

CoRo

Cc

Cc

Cp

Gm*Vd

V

FB

V

REF

Vd

Rc

AM11419v1

GEAs()

G

EA0

1s+ RcC

c

⋅⋅()⋅

s

2

R0C0Cp+()RcCcsR0Cc⋅ R0C0Cp+()RcCc⋅+⋅+()1+⋅+⋅⋅ ⋅⋅

------------ ------------ ------------- ------------- ------------- -------------- ------------- ------------- ------------- --------------- ------------ ------------- ------------- ------------- ------------ -------------=

f

P LF

1

2 π R

0Cc

⋅⋅ ⋅

----------- ------------- ------------- -----=

f

P HF

1

2 π R

c

C0Cp+()⋅⋅ ⋅

----------- ------------- ------------- ------------- ----------=

f

Z

1

2 π R

cCc

⋅⋅ ⋅

------------ ------------ ------------- ---- -=

Figure 5. Small signal model for the error amplifier

R

and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect

C

system stability and can be neglected.

So, G

(s) results:

EA

Equation 8

where G

= Gm · R

EA

o

The poles of this transfer function are (if Cc >> C0+CP):

Equation 9

Equation 10

whereas the zero is defined as:

Equation 11

The embedded compensation network is R
considered as negligible. The error amplifier output resistance is 212 M
singularities are:

=80 kΩ, CC=55 pF while CP and CO can be

C

Ω, so the relevant

Doc ID 023246 Rev 1 11/29

Functional description ST1S32

fZ36 2 kHz,= f

P LF

30 Hz=

G

LOOP

s() GCOs() G

DIV

s() GEAs()⋅⋅=

0.1 1 10 100 1.10

3

1.10

4

1.10

5

1.10

6

1.10

7

60

42

24

6

12

30

48

66

84

102

120

Frequency [ Hz ]

Module [dB]

AM11420v1

Equation 12

So, closing the loop, the loop gain G

LOOP

(s) is:

Equation 13

Example:

VIN=5 V, VOUT=1.2 V, Iomax=4 A, L=1.0 uH, Cout=47 uF (MLCC), R1=10 k
k

Ω

(see Section 5.2 and Section 5.3 for inductor and output capacitor selection

guidelines).

The module and phase Bode plot are reported in Figure 6.

The bandwidth is 117 kHz and the phase margin is 63 degrees.

Figure 6. Module Bode plot

Ω

, R2=20

12/29 Doc ID 023246 Rev 1

ST1S32 Functional description

AM11421v1

0.1 1 10 100 1.10

3

1.10

4

1.10

5

1.10

6

1.10

7

210

182.5

155

127.5

100

72.5

45

17.5

10

Frequency [ H z ]

Phase

Figure 7. Phase Bode plot

4.3 Overcurrent protection

The ST1S32 implements overcurrent protection sensing the current flowing through the
high-side current switch.

If the current exceeds the overcurrent threshold, the high-side is turned off, implementing a
cycle-by-cycle current limitation. Since the regulation loop is no longer fixing the duty cycle,
the output voltage is unregulated and the FB pin falls accordingly to the new duty cycle.

If the FB pin falls below 0.2 V, the peak current limit is reduced to around 2.3 A and the
switching frequency is reduced to assure that the inductor current is properly limited below
the above mentioned value and above 1.2 A. This strategy is called “current foldback”.

The mechanism to adjust the switching undercurrent foldback condition exploits the low-side
current sense circuitry. If FB is lower than 0.2 V, the high-side Power MOSFET is turned off
when the current reaches the current foldback threshold (2.3 A), then, after a proper dead
time that avoids the cross conduction, the low-side is turned on until the low-side current is
lower than a valley threshold (1.2 A). Once the low-side is turned off, the high-side is
immediately turned on. In this way the frequency is adjusted to keep the inductor current
ripple between the current foldback value (2.3 A) and valley threshold (1.2 A), therefore
properly limiting the output current in case of overcurrent or short-circuit.

It should be noted that in some cases, mainly with very low output voltages, the hard
overcurrent can make the FB find the new equilibrium just over the current foldback
threshold (0.2 V). In this case no frequency reduction is enabled, then the inductor current
may diverge. That is, the ripple current during the minimum ON-time is higher than the ripple
current during the OFF-time (the switching period minus the minimum ON-time), so pulse­by-pulse the average current is rising, exceeding the current limit.

In order to avoid too high current, a further protection is activated when the high-side current
exceeds a further current threshold (OCP2) slightly over the current limit (OCP1). If the
current triggers the second threshold, the converter stops switching, the reference of the
error amplifier is pulled down and then it restarts with a soft-start procedure. If the
overcurrent condition is still active, the current foldback with frequency reduction properly
limits the output current to 2.3 A.

Doc ID 023246 Rev 1 13/29

Functional description ST1S32

4.4 Enable function

The enable feature allows the device to be put into standby mode. With the EN pin lower
than 0.4 V, the device is disabled and the power consumption is reduced to less than 10 uA.
With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an
internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also V

compatible.

IN

4.5 Light load operation

With peak current mode control loop the output of the error amplifier is proportional to the
load current. In the ST1S32, to increase light load efficiency, when the output of the error
amplifier falls below a certain threshold, the high-side turn-on is prevented.

This mechanism reduces the switching frequency at light load in order to save the switching
losses.

4.6 Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150
the device restarts in normal operation.

o

C. Once the junction temperature goes back to about 130 oC,

14/29 Doc ID 023246 Rev 1

ST1S32 Application information

I

RMSIO

D

2D

2

⋅

η

------------ -----–

D

2

η

2

------ -+⋅=

V

PP

I

O

CINFSW⋅

------------- ------------- --

1

D

η

----–

⎝⎠

⎛⎞

D

D

η

--- -

1D–()⋅+⋅ ESR IO⋅+⋅=

C

IN

I

O

V

PPFSW

⋅

------------- ------------- ---

1

D

η

----–

⎝⎠

⎛⎞

D

D

η

----

1D–()⋅+⋅⋅=

C

IN_MIN

I

O

2V

PP_MAXFSW

⋅⋅

------------- ------------ ------------- ------------- --=

5 Application information

5.1 Input capacitor selection

The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.

So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 14

where Io is the maximum DC output current, D is the duty cycle, and η is the efficiency.
Considering η=1, this function has a maximum at D=0.5 and is equal to Io/2.

The peak-to-peak voltage across the input capacitor can be calculated as:

Equation 15

where ESR is the equivalent series resistance of the capacitor.

Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this
case, the equation of C

as a function of the target peak-to-peak voltage ripple (VPP) can

IN

be written as follows:

Equation 16

neglecting the small ESR of ceramic capacitors.
Considering η=1, this function has its maximum in D=0.5, therefore, given the maximum

peak-to-peak input voltage (V

PP_MAX

), the minimum input capacitor (C

IN_MIN

) value is:

Equation 17

Doc ID 023246 Rev 1 15/29

Application information ST1S32

ΔI

L

VINV

OUT

–

L

------------ ------------ ----- -

T

ON

⋅

V

OUT

L

------------ --

T

OFF

⋅==

L

MIN

V

OUT

ΔI

MAX

----------------

1D

MIN

–

F

SWMIN

------------ -----------

⋅=

Ty p i c a l l y, CIN is dimensioned to keep the maximum peak-to-peak voltage ripple in the order
of 1% of V

INMAX

.

The placement of the input capacitor is very important in order to avoid noise injection and
voltage spikes on the input voltage pin. So the C

must be placed as close as possible to

IN

the VIN_SW pin.

In Ta bl e 6 some multi-layer ceramic capacitors suitable for this device are reported.

Table 6. Input MLCC capacitors

Manufacturer Series Cap value (µF) Rated voltage (V)

Murata GRM21 10 10

TDK

Taiyo Yuden LMK212 22 10

A ceramic bypass capacitor, as close as possible to the VINA pin, so that additional parasitic
ESR and ESL are minimized, is suggested in order to prevent instability on the output
voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1µF.

5.2 Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple must be selected.
The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current.

In continuous current mode (CCM), the inductance value can be calculated by the following
equation:

Equation 18

C3225 10 25

C3216 10 16

where T
the low-side switch (in CCM, F
V

OUT

calculate minimum duty). So by fixing ΔI

is the conduction time of the high-side switch and T

ON

, is obtained at maximum T

=1/(TON + T

SW

, that is at minimum duty cycle (see previous section to

OFF

OFF

=20% to 30% of the maximum output current, the

L

minimum inductance value can be calculated as:

Equation 19

where F

16/29 Doc ID 023246 Rev 1

is the minimum switching frequency, according to Ta bl e 4 .

SWMIN

is the conduction time of

OFF

)). The maximum current ripple, given the

ST1S32 Application information

LV

out

2V

pp

• fsw•()⁄>

I

LPK,

I

O

ΔI

L

2

--------+=

The slope compensation, to prevent the sub-harmonic instability in peak current control
loop, is internally managed and so fixed. This implies a further lower limit for the inductor
value. To assure the sub-harmonic stability:

Equation 20

where V

is the peak-to-peak value of the slope compensation ramp.

pp

The inductor value selected, based on Equation 19, must satisfy Equation 20.

The peak current through the inductor is given by:

Equation 21

So if the inductor value decreases, the peak current (that must be lower than the current
limit of the device) increases. The higher the inductor value, the higher the average output
current that can be delivered, without reaching the current limit.

In Ta bl e 7 some inductor part numbers are listed.

Table 7. Inductors

Manufacturer Series Inductor value (µH) Saturation current (A)

XAL50xx 1.2 to 3.3 6.3 to 9

Coilcraft

Wurth

XAL60xx 2.2 to 5.6 7.4 to 11

MSS1048 1.0 to 3.8 6.5 to 11

WE-HCI 7030 1.5 to 4.7 7 to 14

WE-PD type L 1.5 to 3.5 6.4 to 10

Coiltronics

DR73 1.0 to 2.2 5.5 to 7.9

DR74 1.5 to 3.3 5.4 to 8.35

5.3 Output capacitor selection

The current in the output capacitor has a triangular waveform which generates a voltage
ripple across it. This ripple is due to the capacitive component (charge or discharge of the
output capacitor) and the resistive component (due to the voltage drop across its ESR). So
the output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.

The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.

Doc ID 023246 Rev 1 17/29

Application information ST1S32

ΔV

OUT

ESR ΔI

MAX

⋅

ΔI

MAX

8C

OUTfSW

⋅⋅

------------ ------------- ------------- ----+=

P

COND

R

HSIOUT

2

DRLSI

OUT

2

1D–()⋅⋅+⋅⋅=

Equation 22

For the ceramic (MLCC) capacitor the capacitive component of the ripple dominates the
resistive one. While for the electrolythic capacitor the opposite is true.

As the compensation network is internal, the output capacitor should be selected in order to
have a proper phase margin and then a stable control loop.

The equations of Section 4.2 help to check loop stability, given the application conditions,
the value of the inductor and the output capacitor.

In Ta bl e 8 some capacitor series are listed.

Table 8. Output capacitors

Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ)

Murata

Panasonic

Sanyo TPA/B/C 100 to 470 4 to 16 40 to 80

TDK C3225 22 to 100 6.3 < 5

GRM32 22 to 100 6.3 to 25 < 5

GRM31 10 to 47 6.3 to 25 < 5

ECJ 10 to 22 6.3 < 5

EEFCD 10 to 68 6.3 15 to 55

5.4 Thermal dissipation

The thermal design is important to prevent the thermal shutdown of the device if junction
temperature goes above 150 °C. The three different sources of loss within the device are:

a) conduction losses due to the on-resistance of the high-side switch (R

side switch (R

Equation 23

where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between V
the regulator.

b) switching losses due to high-side Power MOSFET turn-on and off; these can be

calculated as:

); these are equal to:

LS

and VIN, but actually it is slightly higher to compensate the losses of

OUT

) and low-

HS

18/29 Doc ID 023246 Rev 1

ST1S32 Application information

P

SW

VINI

OUT

T

RISETFALL

+()

2

------------- ------------- ------------ ---- -

Fsw⋅⋅ ⋅ V

INIOUTTSWFSW

⋅⋅⋅==

PQVINIQ⋅=

TJTARthJAP

TOT

⋅+=

Equation 24

where T
switch (V

Figure 8. T

and T

RISE

) and the current flowing into it during turn-on and turn-off phases, as shown in

DS

is the equivalent switching time. For this device the typical value for the

SW

are the overlap times of the voltage across the high-side power

FALL

equivalent switching time is 20 ns.

c) Quiescent current losses, calculated as:

Equation 25

where I

The junction temperature T

is the quiescent current (IQ=1.2 mA maximum).

Q

can be calculated as:

J

Equation 26

where T

Rth

is the ambient temperature and P

A

is the equivalent thermal resistance junction-to-ambient of the device; it can be

JA

is the sum of the power losses just seen.

TOT

calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The Rth

measured on the demonstration board described in Section 5.5 is about

JA

40 °C/W for the VFDFPN package.

Doc ID 023246 Rev 1 19/29

Application information ST1S32

V

SW

I

SW,HS

V

IN

V

DS,HS

P

COND,HS

P

COND,LS

P

SW

T

FALL

T

RISE

AM11422v1

Figure 8. Switching losses

5.5 Layout considerations

The PC board layout of the switching DC/DC regulator is very important to minimize the
noise injected in high impedance nodes, to reduce interference generated by the high
switching current loops and to optimize the reliability of the device.

In order to avoid EMC problems, the high switching current loops must be as short as
possible. In the buck converter there are two high switching current loops: during the ON­time, the pulsed current flows through the input capacitor, the high-side power switch, the
inductor and the output capacitor; during the OFF-time, through the low-side power switch,
the inductor and the output capacitor.

The input capacitor connected to VINSW must be placed as close as possible to the device,
to avoid spikes on VINSW due to the stray inductance and the pulsed input current.

In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the
VINA pin to the input must be derived from VINSW.

The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so interference can be minimized by routing the feedback node with a very short trace and
as far as possible from the high current paths.

A single point connection from signal ground to power ground is suggested.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction-to-ambient; so a large ground plane, soldered to the exposed pad,
enhances the thermal performance of the converter allowing high power conversion.

20/29 Doc ID 023246 Rev 1

ST1S32 Application information

AM11423v1

Input cap as
close as possible
to VINSW pin

Star center for common ground

Short FB trace VINA derived from Cin

to avoid dynamic voltage drop
between VINA and VINSW

Short high
switching
current loop

Via to connect the thermal pad
to bottom or inner ground plane

Figure 9. PCB layout example

Doc ID 023246 Rev 1 21/29

Demonstration board ST1S32

3.3V

5V

VIN

Vout

0

0

L1

2.2uHL12.2uH

R2
20kR220k

R3

10kR310k

C2
22uC222u

C1

10uC110u

C31uC3
1u

U1

ST1S31U1ST1S32

VIN_A

1

EN

2

FB

3

AGND

4

PGND

8

SW

7

VIN_SW

6

PGOOD

5

ePAD

C4NCC4

NC

R1

62.5kR162.5k

AM12610V1

6 Demonstration board

Figure 10. Demonstration board schematic

Table 9. Component list

Reference Part number Description Manufacturer

U1 ST1S32PUR ST

L1 DR74 2R2 2.2 µH, Isat=7 A Coiltronics

C1 C3225X7RE106K 10 µF 25 V X7R TDK

C2 C3225X7R1C226M 22

C3 1

C4 NC

R1 62.5 kΩ

R2 20 kΩ

R3 10 kΩ

µF 16 V X7R TDK

µF 25 V X7R

22/29 Doc ID 023246 Rev 1

ST1S32 Demonstration board

Figure 11. Demonstration board PCB top and bottom

Doc ID 023246 Rev 1 23/29

Typical characteristics ST1S32

VIN=5V

Green: IL (100mA/div)

Yellow: SW (1V/div)

Red: V

OUT

(20mV/div)

Timescale 2us/div

VIN=5V, V

OUT

=1.2V, IO=0A

Green: IL (100mA/div)

Yellow: SW (1V/div)

Red: V

OUT

(20mV/div)

Timescale 2us/div

VIN=5V, V

OUT

=1.2V, IO=100mA

VIN=3.3V

7 Typical characteristics

Figure 12. Efficiency vs. I

@ VIN = 5 V Figure 13. Zero load operation

OUT

Figure 14. 100 mA operation Figure 15. Efficiency vs. I

@ VIN = 3.3 V

OUT

24/29 Doc ID 023246 Rev 1

ST1S32 Typical characteristics

Green: IL (1A/div)

Yellow: SW (1V/div)

Red: V

OUT

(200mV/div)

Timescale 200us/div

VIN=5V, V

OUT

=1.2V, I

LOAD

=0.5A -> 5.8A

Green: IL (1A/div)

Yellow: SW (1V/div)

Red: V

OUT

(200mV/div)

Timescale 100us/div

VIN=5.5V, V

OUT

=1.2V

Figure 16. Overcurrent protection Figure 17. Short-circuit protection

Doc ID 023246 Rev 1 25/29

Package mechanical data ST1S32

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK

26/29 Doc ID 023246 Rev 1

ST1S32 Package mechanical data

"

Table 10. VFQFPN8 (4x4x1.0 mm) mechanical data

mm inch

Dim.

Min. Typ. Max. Min. Typ. Max.

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0.02 0.05 0.0008 0.0020

A3 0.20 0.0079

b 0.23 0.30 0.38 0.009 0.0117 0.0149

D 3.90 4.00 4.10 0.153 0.157 0.161

D2 2.82 3.00 3.23 0.111 0.118 0.127

E 3.90 4.00 4.10 0.153 0.157 0.161

E2 2.05 2.20 2.30 0.081 0.087 0.091

e 0.80 0.031

L 0.40 0.50 0.60 0.016 0.020 0.024

Figure 18. Package dimensions

Doc ID 023246 Rev 1 27/29

Order codes ST1S32

AM12611V1

Figure 19. Recommended footprint

(a)

9 Order codes

Table 11. Ordering information

Order codes Package

ST1S32PUR VFDFPN 4x4 8L

10 Revision history

Table 12. Document revision history

Date Revision Changes

31-May-2012 1 First release.

a. Dimensions are in mm.

28/29 Doc ID 023246 Rev 1

ST1S32

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Doc ID 023246 Rev 1 29/29