Up to 3 A step down switching regulator
Features
■ 3 A DC output current
■ Operating input voltage from 5.5 V to 48 V
■ 850 kHz internally fixed switching frequency
■ Internal soft start
■ Power good open collector output
■ Current mode architecture
■ Embedded compensation network
■ Zero load current operation
■ Internal current limiting
■ Inhibit for zero current consumption
■ 2 mA maximum quiescent current over
temperature range
■ 250 mΩ typical R
■
Thermal shutdown
Application
Factory automation
Printers
DC-DC modules
High current LED drivers
Figure 1. Application schematic
DS(on)
ST1S14
HSOP8 - exposed pad
Description
The ST1S14 is a step down monolithic power
switching regulator able to delivers up to 3 A DC
current to the load depending on the application
conditions. The high current level is also achieved
thanks to an HSOP8 package with exposed
frame, that allows to reduce the R
approximately 40 °C/W. The output voltage can
be set from 1.22 V. The device uses an internal Nchannel DMOS transistor (with a typical R
200 mΩ) as switching element to minimize the
size of the external components. The internal
oscillator fixes the switching frequency at 850
kHz. Power good open collector output validates
the regulated output voltage as soon as it reaches
the regulation. Pulse by pulse current limit offers
an effective constant current short circuit
protection. Current foldback decreases overstress
in persistent short circuit condition.
100nFC1 100nFC1
th(JA)
PGOODPGOOD
down to
DS(on)
of
VINVIN
GNDGND
10uFC210uF
U1 ST1S14U1 ST1S14
PGOOD
8
SW
2
4
FB
D1
D1
STPS3L60U
STPS3L60U
1
BOOT
7
VIN
5
EN2
3
EN1
C3
C2
100nFC3100nF
GND
6
L1 8.5uHL1 8.5uH
R3 47KR3 47K
R1 4.7KR1 4.7K
C4C4
R2
2.7KR22.7K
small signal
power plane
VOUTVOUT
C5
100uFC5100uF
GNDGND
October 2010 Doc ID 17977 Rev 1 1/42
www.st.com
42
Contents ST1S14
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.6 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Additional features and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Maximum duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Minimum output voltage over V
range . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IN
6 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 GCO(s) Control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/42 Doc ID 17977 Rev 1
ST1S14 Contents
7.1.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1.3 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4.1 300 mV < VFB < 1.22 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4.2 V
< 300 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FB
7.5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Doc ID 17977 Rev 1 3/42
Pin settings ST1S14
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
EXPOSED
PA D
TO GND
1.2 Pin description
Table 1. Pin description
N Pin Description
1BOOT
2 PG Power good
3EN1
4 FB Feedback voltage
5 FB Enable pin active high
6 GND Ground pin
7V
8 SW Switching node
IN
E.p. Exposed pad must be connected to GND
1.3 Enable inputs
Table 2. Truth table
EN1 EN2 Device status
HL INH
HH INH
LL INH
Bootstrap capacitor for N-channel gate driver. Connect 100nF low ESR
capacitor from BOOT pin to SW
Enable pin active low
Input supply pin
LH ON
4/42 Doc ID 17977 Rev 1
ST1S14 Electrical data
2 Electrical data
2.1 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
IN
V
EN1
V
EN2
PG Power good -0.3 to (V
BOOT Bootstrap pin -0.3 to 55 V
SW Switching node -1 to (VIN+0.3) V
V
FB
T
J
T
STG
T
LEAD
Power supply input voltage -0.3 to 52 V
Enable 1 voltage -0.3 to 7 V
Enable 2 voltage -0.3 to (VIN+0.3) V
Feedback voltage -0.3 to 3 V
Operating junction temperature range -40 to 150 °C
Storage temperature range -65 to 150 °C
Lead temperature (soldering 10 sec.) 260 °C
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
th JA
Thermal resistance junction-ambient 40 °C/W
+0.3) V
IN
2.3 ESD protection
Table 5. ESD protection
Symbol Test condition Value Unit
HBM 4 kV
ESD
MM 500 V
Doc ID 17977 Rev 1 5/42
Electrical characteristics ST1S14
3 Electrical characteristics
All the population tested at TJ = 25 °C, VCC =12 V, V
EN1
= 5 V, V
=0 V unless otherwise
EN2
specified.
The specification is guaranteed from (-40 to +125) T
temperature range by design,
J
characterization and statistical correlation.
Table 6. Electrical characteristics
Symbol Parameter Test condition Min Typ Max Unit
Operating input
V
IN
R
DS(on)
I
SW
t
HICCUP
f
SW
T
ON MIN
T
OFF MIN
voltage range
MOSFET on
resistance
=1A 0.2 0.4 Ω
I
SW
Maximum limiting
current
Hiccup time 16 ms
Switching frequency 600 850 1000 kHz
Duty cycle
Minimum conduction
time of the power
element
Minimum conduction
time of the external
diode
5.5 48 V
3.7 4.5 5.2 A
(1)
(1)
(1)
75 90 120 ns
90 %
90 ns
DC characteristics
I
=0 A 1.202 1.22 1.239 V
V
I
FB
I
I
qst-by
Voltage feedback
FB
FB biasing current 50 nA
Quiescent current
q
Stand-by quiescent
current
PG output voltage
(open collector active)
LOAD
I
=10 mA to 3A 1.196 1.22 1.245 V
LOAD
V
=2V 1.3 2 mA
FB
V
=2V, VIN=48V 1.7 2.4 mA
FB
DEVICE OFF (see Ta b le 2 μ
V
falling edge
FB
I
= 6mA 0.4 V
SINK
6/42 Doc ID 17977 Rev 1
0.92*
V
OUT
0.8*
V
OUT
V
V
Table 6. Electrical characteristics (continued)
Symbol Parameter Test condition Min Typ Max Unit
Inhibit
V
I
V
I
Enable 1 levels
EN1
Enable 1 biasing
EN1
current
Enable 2 levels
EN2
Enable 2 biasing
EN2
current
Thermal shutdown
T
SHDWN
T
HYS
1. Parameter guaranteed by design
Thermal shutdown
temperature
Thermal shutdown
hysteresis
Device ON
=5.5V to 48V
V
IN
Device OFF
=5.5V to 48V
V
IN
=5V 1.6 2.5 μA
V
EN1
Device ON
VIN=5.5V to 48V
1.5 V
1.5 V
Device OFF
V
=5.5V to 48V
IN
V
=0V; V
EN1
V
=0V; V
EN1
=0V; VCC=V
V
EN1
=0V -1.0 -2.4 -3.7 μA
EN2
=12V 2.7 5.8 8.5 μA
EN2
=48V 3.0 6.0 9.0 μA
EN2
(1)
140 150 160 °C
(1)
15 °C
0.5 V
0.5 V
Doc ID 17977 Rev 1 7/42
Functional description ST1S14
4 Functional description
The ST1S14 is based on a “peak current mode”, constant frequency control. As a
consequence the intersection between the error amplifier output and the sensed inductor
current generates the control signal to drive the power switch.
The main internal blocks shown in the block diagram in Figure 3 are:
● A fully integrated sawtooth oscillator with a typical frequency of 850 kHz
● A transconductance error amplifier
● An high side current sense amplifier to track the inductor current
● A pulse width modulator (PWM) comparator and the circuitry necessary to drive the
internal power element
● The soft start circuitry to decrease the inrush current at power-up
● The current limitation circuit based on the pulse by pulse current protection with
frequency divider based on FB voltage and the HICCUP protection
● The bootstrap circuitry to drive the embedded N-MOS switch.
● A multi input inhibit block for stand-by operation.
● A circuit to implement the thermal protection function.
Figure 3. Device block diagram
Slope
compensation
EA
SOFT START
REF
VC
1.21V
T
Comp
Rc
Cc
OSC
OTP
KR*I
Reg
L
MOSFET
CONTROL
LOGIC
ShutDown
BOOT
I_SEN
VIN
Boot Reg
Driver1
SW
Driver2Cp
PG
8/42 Doc ID 17977 Rev 1
EN2
EN1 GND
ST1S14 Functional description
4.1 Power supply and voltage reference
The internal regulator circuit consists of a start-up circuit, an internal voltage pre-regulator,
the bandgap voltage reference and the bias block that provides current to all the blocks. The
starter supplies the start-up current to the entire device when the input voltage goes high
and the device is enabled (inhibit pin connected to ground). The pre-regulator block supplies
the bandgap cell with a pre-regulated voltage that has a very low supply voltage noise
sensitivity.
4.2 Voltages monitor
An internal block continuously senses the Vcc, V
good, the regulator begins operating. There is also a hysteresis on the V
Figure 4. Internal circuit
4.3 Soft Start
The startup phase minimizes the inrush current and decreases the stress of the power
components at the power up. The startup takes place when V
threshold.
As shown in Figure 5, the soft start event is composed of three main phases:
and Vbg. If the monitored voltages are
ref
crosses the selected UVLO
IN
(UVLO).
CC
Phase 1: [V
<300 mV]
FB
The output capacitor is charged with a typical peak inductor current equal to 1.45 A and
the nominal f
Phase 2: [VFB>300 mV & n
is divided by 5
SW
COUNT
<2816 clks]
A internal counter determines phase 2 time (see Figure 5).
The reference of the error amplifier is ramped in 44 steps (one step every 64 clks).
A low pass filter smooths each step to minimize output discontinuity. Considering the
typical 850 kHz switching frequency, the phase two duration is 3.3 msec
Phase 3: [VFB>300 mV & n
COUNT
=2816 clks]
The reference of the embedded error amplifier is connected to the nominal reference
voltage (1.222 typical) derived from the internal bandgap generator. The soft start
phase ends at this time.
Doc ID 17977 Rev 1 9/42
Functional description ST1S14
Figure 5. soft start phases
PHASE 1
PHASE 2 PHASE 3
VREF_OUT
VFB
SHORT
2816 clks
During normal operation a new soft start cycle takes place in case of:
● HICCUP mode current protection
● thermal shutdown event
● UVLO event
● the device is driven in INH mode
Figure 6. Soft-start block diagram
VREF
Ctrl
S2
c
Vsaw
Vsense
64clks
S1
300mV
VREF_OUT
VFB
VFB
EA
400mV
Vsense
Logic
Iclamp
SHORT
10/42 Doc ID 17977 Rev 1
ST1S14 Functional description
4.4 Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (1.222 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage.
The error amplifier is internally compensated to minimize the size of the final application.
Table 7. Uncompensated error amplifier characteristics
Description Values
Transconductance 218 µS
Low frequency gain 93 dB
C
P
C
C
R
C
The error amplifier output is compared with the inductor current sense information to
perform PWM control
24 pF
211 pF
200 kΩ
4.5 Inhibit function
The inhibit feature is used to set the device in standby mode according to Ta b l e 2 : Tr u t h
table. When the device is disabled, the power consumption is reduced to less than 40 µA.
The pin EN2 is also V
compatible.
IN
4.6 Thermal shutdown
The shutdown block generates a signal that turns OFF the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150±10 °C). The sensing element of the
chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A
hysteresis of approximately 15 °C keeps the device from turning ON and OFF continuously.
Doc ID 17977 Rev 1 11/42
Additional features and limitations ST1S14
5 Additional features and limitations
5.1 Maximum duty cycle
The bootstrap circuitry charges cycle by cycle the external bootstrap capacitor to generate a
voltage higher than V
An internal linear regulator charges the C
free wheeling diode during the switching activity. The internal logic implements a minimum
OFF time of the high side switch (90 nsec typical) to prevent the bootstrap discharge at high
duty cycle. As a consequence the ST1S14 can operate at a maximum duty cycle around
90% typical.
necessary to drive the internal N-channel power element.
IN
during the conduction time of the external
BOOT
The ST1S14 embeds the diode V
Figure 7. Bootstrap operation
REGULATOR
V
D1
V
DRIVER
V
REG-VD1+VD2
required for the bootstrap operation.
D1
V
IN
HS switch
C
BOOT
V
D2
C
OUT
12/42 Doc ID 17977 Rev 1
ST1S14 Additional features and limitations
5.2 Minimum output voltage over VIN range
The minimum regulated output voltage at a given input voltage is limited by the minimum
conduction time of the power element, that is 90nsec typical for the ST1S14:
Equation 1
V
O_MINVIN
()VIND
⋅ V
MIN
T
ON_MIN
--------------------- -
⋅ V
IN
T
SW
⋅== =
IN
90ns
------------------
1.18μs
which is plotted in Figure 14. The reference of the embedded error amplifier (1.22V) sets the
minimum V
Figure 8. V
O_SET
O_MIN
at low VIN.
over input voltage range
Figure 8 shows the minimum output voltage over input voltage range to have constant
switching activity and a predictable output voltage ripple.
The regulator can anyway regulate the minimum input voltage over the entire input voltage
range but, given the 90ns minimum conduction time of the power element, it will skip some
pulses to keep the output voltage in regulation when Equation 1 is not satisfied.
This operation is not recommended at the nominal input voltage of the application mainly
because it affects the output voltage ripple, but it is generally accepted during a line
transient event.
Doc ID 17977 Rev 1 13/42
Closing the loop ST1S14
6 Closing the loop
Figure 9. Block diagram of the loop
V
PWM contr ol
IN
Current sense
-
-
+
+
PWM comp arator
HS
switch
compensa tion network
C
P
LC fi lter
L
C
OUT
resist or div ider
R
1
FB
-
V
REF
+
R
R
C
C
C
Error amplifier
2
14/42 Doc ID 17977 Rev 1
ST1S14 Closing the loop
6.1 G
The accurate control to output transfer function for a buck peak current mode converter can
be written as:
Equation 2
where R
sense circuitry, ω
ESR of the output capacitor.
F
error amplifier that introduces a double pole at one half of the switching frequency.
Equation 3
Equation 4
(s) Control to output transfer function
CO
s
⎛⎞
1
------+
⎝⎠
R
0
----------------------------------------------------------------------------------------
GCOs()
represents the load resistance, Ri the equivalent sensing resistor of the current
0
p
(s) accounts the sampling effect performed by the PWM comparator on the output of the
H
------ -
R
i
1
⋅
R
0TSW
---------------------- -
L
the single pole introduced by the LC filter and ωz the zero given by the
ω
------------------------------------- -
n
R
LOADCOUT
1
m
1D–()0.5–⋅[]⋅+
C
1
-------------------------------=
ω
Z
1
⋅
⋅
ESR C
m
---------------------------------------------+=
OUT
1D–()0.5–⋅
C
LC
⋅⋅
OUTfSW
ω
z
--------------------- -
⎛⎞
1
⎝⎠
F
H
s
------+
ω
p
s()⋅⋅⋅=
where:
Equation 5
⎛
mC1
⎜
⎜
⎜
S
e
⎜
⎜
⎜
S
n
⎝
S
represents the on time slope of the sensed inductor current, Se the on time slope of the
n
external ramp (V
peak to peak amplitude) that implements the slope compensation to
PP
S
e
------
+=
S
n
Vppf
⋅=
SW
VINV
–
OUT
----------------------------- -
L
R
⋅=
i
avoid sub-harmonic oscillations at duty cycle over 50%
The sampling effect contribution F
(s) is:
H
Equation 6
where:
Equation 7
----------------------------------------------------------=
Q
P
π m
1
1D–()0.5–⋅[]⋅
C
Doc ID 17977 Rev 1 15/42
Closing the loop ST1S14
FHs()
------------------------------------------ -=
1
1
s
------------------ -
ω
⋅
nQP
s
------++
ω
6.2 Error amplifier compensation network
The ST1S14 embeds (see Figure 10) the error amplifier and a pre-defined compensation
network which is effective to stabilize the system in most of the application conditions
Figure 10. Transconductance embedded error amplifier
E/A
FB
+
-
COMP
2
2
n
R
C
C
C
C
P
+
V
?V
G
?V
m
R
and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect
C
system stability but it is useful to reduce the noise at the output of the error amplifier.
The transfer function of the error amplifier and its compensation network is:
Equation 8
A
1s+ RcC
A0s()
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=
V0
s2R0C0Cp+()RcCcsR0Cc⋅ R0C0Cp+()RcCc⋅+⋅+()1+⋅+⋅⋅ ⋅⋅
Where A
= Gm · R
vo
o
The poles of this transfer function are (if Cc >> C0+CP):
16/42 Doc ID 17977 Rev 1
R
R
0
C
0
⋅⋅()⋅
c
C
C
C
C
P
ST1S14 Closing the loop
Equation 9
P LF
--------------------------------- -=
⋅⋅ ⋅
2 π R
0Cc
f
1
Equation 10
whereas the zero is defined as:
Equation 11
The embedded compensation network is R
considered negligible, so the singularities are:
Equation 12
f
Z
6.3 Voltage divider
The contribution of a simple voltage divider is:
Equation 13
f
P HF
377 kHz,= f
F
Z
P LF
----------------------------------------------------=
2 π R
1
+()⋅⋅ ⋅
cC0Cp
1
---------------------------------=
⋅⋅ ⋅
2 π R
cCc
=200K, CP=24pF, CC=211pF and CO can be
C
301 Hz,= f
P HF
33 16 kHz,=
G
DIV
Figure 11. Leading network example
1
BOOT
7
VIN
5
EN2
3
EN1
Doc ID 17977 Rev 1 17/42
GND
6
s()
PGOOD
R
2
--------------------=
R1R2+
8
SW
2
4
FB
R1R1
CR1CR1
R2R2
small signal
power plane
Closing the loop ST1S14
A small signal capacitor in parallel to the upper resistor (see Figure 11.) of the voltage
divider implements a leading network (f
zero
< f
), sometimes necessary to improve the
pole
system phase margin:
Equation 14
where:
6.4 Total loop gain
In summary, the open loop gain can be expressed as:
Equation 15
Example: V
= 12V, V
IN
G
OUT
s()
DIV
Gs() G
= 3.3V, R
R
2
--------------------
R1R2+
------------------------------------- -
f
Z
⋅⋅ ⋅
2 π R
---------------------------------------------------=
f
P
2 π
<
f
ZfP
DIV
= 2Ω
OUT
1sR
⋅⋅+()
---------------------------------------------------------- -
⋅=
⎛⎞
1s
⎝⎠
1
1CR1
R
1R2
--------------------
⋅⋅+
R
1R2
=
1CR1
⋅
+
C
R1
1
⋅
R
1R2
--------------------
⋅⋅ ⋅
R
1R2
C
+
R1
s()GCOs()A0s()⋅⋅=
The resistor divider is R1=5.6K, R2=3.3K.
C
=150nF implements a leading network (fZ=190 kHz, fP=510 kHz).
R1
Selecting L = 8.2 µH, C
= 100 µF and ESR = 75 mΩ, the gain and phase bode
OUT
diagrams are plotted respectively in Figure 12 and Figure 13 over input voltage range
(V
=6V to 48V, I
IN
18/42 Doc ID 17977 Rev 1
OUT
=3A)
ST1S14 Closing the loop
Figure 12. Module plot
Figure 13. Phase plot
The cut-off frequency and the phase margin are:
Equation 16
V
6V= f
IN
12V= f
V
IN
V
48V= f
IN
Doc ID 17977 Rev 1 19/42
46 kHz= pm 49° =
C
71 kHz= pm 62°=
C
97 kHz= pm 78°=
C
Application information ST1S14
7 Application information
7.1 Component selection
7.1.1 Input capacitor
The input capacitor must be able to support the maximum input operating voltage and the
maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is
squared and the height of each pulse is equal to the output current. The input capacitor has
to absorb all this switching current, whose RMS value can be up to the load current divided
by two (worst case, with duty cycle of 50%). For this reason, the quality of these capacitors
has to be very high to minimize the power dissipation generated by the internal ESR,
thereby improving system reliability and efficiency. The critical parameter is usually the RMS
current rating, which must be higher than the RMS current flowing through the capacitor.
The maximum RMS input current (flowing through the input capacitor) is:
Equation 17
I
RMSIO
2D2⋅
D
-------------- -–
η
2
D
------ -+⋅=
2
η
Where η is the expected system efficiency, D is the duty cycle and I
is the output DC
O
current. Considering η = 1 this function reaches its maximum value at D = 0.5 and the
equivalent RMS current is equal to I
divided by 2. The maximum and minimum duty cycles
O
are:
Equation 18
V
+
OUTVF
D
MAX
------------------------------------ -=
V
–
INMINVSW
and
Equation 19
V
+
D
MIN
Where V
is the free wheeling diode forward voltage and VSW the voltage drop across the
F
internal PDMOS. Considering the range D
OUTVF
--------------------------------------=
V
INMAXVSW
to D
MIN
–
, it is possible to determine the max
MAX
IRMS going through the input capacitor. Capacitors that can be considered are:
Electrolytic capacitors:
These are widely used due to their low price and their availability in a wide range of
RMS current ratings.
The only drawback is that, considering ripple current rating requirements, they are
physically larger than other capacitors.
20/42 Doc ID 17977 Rev 1
ST1S14 Application information
Ceramic capacitors:
If available for the required value and voltage rating, these capacitors usually have a
higher RMS current rating for a given physical dimension (due to very low ESR).
The drawback is the considerably high cost.
Tantalum capacitors:
Small tantalum capacitors with very low ESR are becoming more available. However,
they can occasionally burn if subjected to very high current during charge.
Therefore, it is suggested to avoid this type of capacitor for the input filter of the device
as they could be stressed by an high surge current when connected to the power
supply.
Table 8. List of ceramic capacitors for the ST1S14
Manufacturer Series Capacitor value (µ) Rated voltage (V)
TAIYO YUDEN UMK325BJ106MM-T 10 50
MURATA GRM42-2 X7R 475K 50 4.7 50
In case the selected capacitor is ceramic (so neglecting the ESR contribution), the input
voltage ripple can be calculated as:
Equation 20
7.1.2 Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the
current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required.
Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain,
which helps to increase the phase margin of the system. If the zero goes to a very high
frequency, its effect is negligible.
Ceramic capacitors
Ceramic capacitors and very low ESR capacitors that introduce a zero outside the
designed bandwidth (f
should be avoided. A leading network across the upper resistor of the voltage divider is
useful to increase the phase margin and compensate the system (see Chapter 6.3:
Voltage divider). The effectiveness of the leading network increases at high output
voltage because the singularities becomes more split.
High ESR capacitors
The “high ESR capacitor” definition stands for a capacitor having an ESR value able to
introduce a zero into the designed system bandwidth, which can be, as a general rule,
up to f
/5 at maximum. Tantalum or electrolytic capacitors belongs to this group.
SW
V
IN PP
Z
-----------------------
CINfSW⋅
=1/(2*pi*ESR*C
I
O
D
⎛⎞
1
--- -–
⎝⎠
η
, see Chapter 6: Closing the loop) in general
OUT
D
--- -
D⋅
1D–()⋅+⋅=
η
Doc ID 17977 Rev 1 21/42
Application information ST1S14
Equation 21
--------------------------------------------------
f
Z
2 π ESR COUT⋅⋅ ⋅
1
<<=
BW
f
SW
-------- -
5
A list of some tantalum capacitor manufacturers is provided in Table 9.: Output capacitor
selection.
Table 9. Output capacitor selection
Manufacturer Series Rated voltage (V) Cap value (µF)
Nippon Chemicon KZE 6.3 to 50
Sanyo POSCAP
AVX TPS 4 to 35
1. see Chapter 6: Closing the loop for the selection of the output capacitor
2. POSCAP capacitors have some characteristics which are very similar to tantalum.
(2)
TAE 4 to 16
THB/C/E 4 to 16
--------------------------------------------------
f
Z
2 π ESR COUT⋅⋅ ⋅
(1)
ESR (mΩ)
1
(1)
BW<=
7.1.3 Inductor
The inductor value is very important as it fixes the ripple current flowing through the output
capacitor. The ripple current is usually fixed at 20 - 40% of I
I
max = 3 A. The approximate inductor value is obtained using the following formula:
O
, which is 0.6 - 1.2 A with
omax
Equation 22
VINV
–()
ΔI
OUT
T
⋅=
ON
where T
V
= 3.3 V, V
OUT
----------------------------------
L
is the ON time of the internal switch, given by D · T. For example, with
ON
= 24 V and ΔIO = 0.8 A, the inductor value is about 4.7 µH. The peak
IN
current through the inductor is given by:
Equation 23
ΔI
I
PKIO
-----+=
2
and it can be observed that if the inductor value decreases, the peak current (which must be
lower than the current limit of the device) increases. So, when the peak current is fixed, a
higher inductor value allows a higher value for the output current. In the Table 10.: Inductor
selection, some inductor manufacturers are listed.
Table 10. Inductor selection
Manufacturer Series Inductor value (µH) Saturation current (A)
Wurth Elektronik
Coilcraft XPL 7030 2.2 to 10 29 to 7.2
22/42 Doc ID 17977 Rev 1
WE-HCI 7040 1 to 4.7 20 to 7
WE-HCI 7050 4.9 to 10 20 to 4.0
ST1S14 Application information
7.2 Layout considerations
The layout of switching DC-DC converters is very important to minimize noise and
interference. Power-generating portions of the layout are the main cause of noise and so
high switching current loop areas should be kept as small as possible and lead lengths as
short as possible.
High impedance paths (in particular the feedback connections) are susceptible to
interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 14 below.
The input and output loops are minimized to avoid radiation and high frequency resonance
problems. The feedback pin connections to the external divider are very close to the device
to avoid pick-up noise. Another important issue is the ground plane of the board. Since the
package has an exposed pad, it is very important to connect it to an extended ground plane
in order to reduce the thermal resistance junction-to-ambient.
To increase the design noise immunity, different signal and power ground should be
implemented in the layout (see Chapter 7.5: Application circuit). The signal ground serves
the small signal components, the device ground pin, the exposed pad and a small filtering
capacitor connected to the VCC pin. The power ground serves external diode and the input
filter. The different grounds are connected underneath the output capacitor. Neglecting the
current ripple contribution, the current flowing through this component is constant during the
switching activity and so this is the cleanest ground point of the buck application circuit.
Figure 14. Layout example
Doc ID 17977 Rev 1 23/42
Application information ST1S14
7.3 Thermal considerations
The dissipated power of the device is tied to three different sources:
● Conduction losses due to the not insignificant R
Equation 24
, which are equal to:
DSON
P
ON
R
DSONIOUT
2
()⋅
D⋅=
Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between V
and VIN, but in practice it is substantially higher than this value to
OUT
compensate for the losses in the overall application. For this reason, the conduction losses
related to the R
● Switching losses due to turning ON and OFF. These are derived using the following
increase compared to an ideal case.
DSON
equation:
Equation 25
T
+()
RISETFALL
---------------------------------------- -
2
Where T
P
SWVINIOUT
and T
RISE
⋅⋅ ⋅ ⋅⋅ ⋅=
represent the switching times of the power element that cause the
FAL L
switching losses when driving an inductive load (see Figure 15). T
F
= I
SWVIN
OUTTSW_EQFSW
is the equivalent
SW
switching time.
Figure 15. Switching losses
● Quiescent current losses.
Equation 26
PQVINIQ⋅=
24/42 Doc ID 17977 Rev 1
ST1S14 Application information
Example:
R
DS(on)
–V
–V
–I
= 24 V
IN
=5 V
OUT
= 3 A
OUT
has a typical value of 0.2Ω @ 25 °C and increases to a maximum value of 0.4Ω @
125 °C. We can consider a value of 0.3 Ω.
T
I
Q
is approximately 12 ns.
SW_EQ
has a typical value of 2 mA @ VIN = 24 V.
The overall losses are:
Equation 27
P
TOT
0.3 3()
R
DSONIOUT
2
0.137 24 3 12 109–850 103–24210
2
()⋅
DVINI
OUTTSWFSWVINIQ
⋅⋅+⋅⋅ ⋅ ⋅ ⋅+⋅⋅ 1.15W≅=
3–
""=⋅+⋅⋅⋅+⋅=
The junction temperature of device will be:
Equation 28
Where T
TJTARth
is the ambient temperature and Rth
A
⋅+=
JA–PTOT
is the thermal resistance junction-to-
J-A
ambient. Considering that the device is mounted on board with a good ground plane, that it
has a thermal resistance junction-to-ambient (Rth
) of about 40 °C/W, and an ambient
J-A
temperature of about 40 °C:
T
40 1.15 40 86°C≅⋅+=
J
7.4 Short-circuit protection
In overcurrent protection mode, when the peak current reaches the current limit, the device
disables the power element and it is able to reduce the conduction time down to the
minimum value (approximately 90 nsec typical) to keep the inductor current limited. This is
the pulse by pulse current limitation to implement constant current protection feature.
For the ST1S14, the operation of the pulse by pulse current limitation depends on the FB
voltage:
● 300 mV <V
current limitation value
● V
< 300mV: the switching frequency is decreased five times the nominal value (170
FB
kHz = 850 kHz/5) and the peak current value is foldback to 1.45A typical. The
frequency foldback helps to prevent the current diverging at low V
voltage. The current foldback reduces the stress of the embedded power element and
the external power components in case of persistent short circuit at the output.
In overcurrent condition, the duty cycle is strongly reduced and, in most applications, this is
enough to limit the switch current to the active current threshold, nominal or foldback
depending on the FB voltage.
<1.22V: the device operates at nominal switching frequency and the
FB
Doc ID 17977 Rev 1 25/42
/ high input
OUT
Application information ST1S14
The inductor current ripple during ON and OFF phases can be written as:
● ON phase
Equation 29
VINV
● OFF phase
Δ
I
L TON
– DCRLR
OUT
--------------------------------------------------------------------------------------- -
+()I⋅–
DSON
L
T
()=
ON
Equation 30
Δ
I
L TON
V
DVOUT
----------------------------------------------------------------- -
DCRLI⋅++()–
L
()=
T
OFF
where V
is the voltage drop across the diode, DCRL is the series resistance of the inductor.
D
The pulse by pulse current limitation is effective to implement constant current protection
when:
Equation 31
The overcurrent protection is operating over the entire output voltage, which goes from the
regulated output voltage (V
O_SET
output.
From Equation 29 and Equation 30 we can gather that the implementation of the constant
current protection becomes more critical the lower is the V
In fact, the voltage applied to the inductor during the OFF time becomes equal to the voltage
drop across parasitic components (typically the DCR of the inductor and the V
wheeling diode) when VOUT is negligible, while during T
is maximized and it is approximately equal to V
heavy short-circuit at the output with maximum input voltage.
7.4.1 300 mV < VFB < 1.22 V
The nominal output voltage can be written as:
Δ I
I
L TON
Δ=
L TOFF
) down to GND during heavy short circuit applied at the
and the higher is VIN.
OUT
of the free
the voltage applied the inductor
. In general the worst case scenario is
IN
ON
FW
Equation 32
R
V
O_SET
⎛⎞
VFB1
------ -+
⋅ 1.22 1
⎝⎠
R
From Equation 32 the voltage can be expressed as:
Equation 33
R
1
⎛⎞
1
------ -+
⎝⎠
R
2
so the output voltage is:
26/42 Doc ID 17977 Rev 1
1
2
V
-------------------=
O_SET
1.22
R
1
⎛⎞
------ -+
⋅==
⎝⎠
R
2
ST1S14 Application information
Equation 34
VOV
R
⎛⎞
1
------ -+
⋅ V
FB
⎝⎠
R
1
2
V
-------------------
⋅==
FB
O_SET
1.22
The Equation 29 and Equation 30 in overcurrent conditions can be simplified to:
Equation 35
DCRLR
+()I⋅–
DSON
L
()
T
ON MIN
V
-------- -
L
IN
90ns()≅=
considering T
V
IN
Δ
I
L TON
that has been already reduced to its minimum.
ON
----------------------------------------------------------------
Equation 36
V
⎛⎞
V
–
Δ
I
L TOFF
where T
VDV
--------------------------------------------------------------------- -
=1/fSW and considering the nominal fSW.
SW
O_MIN
DCRLI⋅++()–
L
T
SW
90ns–()
DVFB
⎝⎠
--------------------------------------------------------------------------------------
The voltage divider introduces a gain factor K between the V
O_SET
-------------------
⋅ DCR
1.22
L
and VFB that affect the
O_SET
L
I⋅++
1.18μs()≅=
effectiveness of the current protection. The worst case scenario is the minimum K, that is
the minimum output voltage, over the input voltage (Chapter 5.2: Minimum output voltage
over V
range).
IN
As a consequence the minimum feedback voltage to keep the inductor current limited over
the input voltage range can be expressed making Equation 35 equal to Equation 36 and
expressing V
as given in Equation 1:
O_SET
Equation 37
()1.22
V
FBVIN
1.22 T
⎛⎞
-----------------------------------
–=
⎝⎠
V
INTON_MIN
SW
V
⋅
DIL
DCR⋅()+()⋅
⋅
Equation 37 expresses the worst case scenario as it considers the minimum K gain of the
voltage divider over the entire input voltage range. The Figure 16 plots the Equation 37
considering the minimum value of the peak current limit given in Ta b l e 6 : E l e ct r i c a l
characteristics on page 6.
Doc ID 17977 Rev 1 27/42
Application information ST1S14
Figure 16. Minimum VFB for effective pulse by pulse protection over VIN
As a consequence for VIN > 12V the pulse by pulse current protection (in the worst case
scenario which is minimum V
peak current limitation over entire FB range 300mV < V
In fact at higher input voltage
) could not be effective to limit the inductor current to the
OSET
ΔI
L TON
could be higher than ΔI
< 1.22V.
FB
and so the inductor
L TOFF
current could escalate. The system typically meets the Equation 31 at a current level higher
than the nominal value thanks to the voltage drop across stray components.
Figure 17. I
diverging triggers hiccup protection (VIN= 48V)
L
In most of the application condition the pulse by pulse current limitation is effective to limit
the inductor current.
28/42 Doc ID 17977 Rev 1
ST1S14 Application information
Whenever the current escalates, a second level current protection called “hiccup mode” is
enabled. In case the hiccup current level (6.2A typical) is triggered the switching activity is
prevented for 16ms and then a new soft start phase takes place (see Figure 17).
7.4.2 VFB < 300 mV
The device reduces the switching frequency five time than the nominal value when
V
<300mV. The frequency foldback makes the pulse by pulse current protection effective
FB
to keep the current limited when the output voltage is shorted and V
The Equation 29 and Equation 30 in overcurrent conditions can be simplified to:
Equation 38
DCRLR
Δ
I
L TON
V
IN
----------------------------------------------------------------
+()I⋅–
DSON
L
()
T
ON MIN
V
-------- -
L
IN
OUT
90ns()≅=
negligible.
considering T
that has been already reduced to its minimum.
ON
Equation 39
V
-------------------
⋅ DCR
1.22
Δ
I
L TOFF
VDV
--------------------------------------------------------------------- -
O_MIN
DCRLI⋅++()–
L
⎛⎞
–
V
T
SW
⎛⎞
----------- 90ns–
⎝⎠
5
DVFB
⎝⎠
------------------------------------------------------------------------------------- -
taking in consideration the frequency foldback feature.
Figure 18. Current and frequency foldback triggered when V
O_SET
L
L
<300mV (red trace)
FB
I⋅++
5.9μs()≅=
Doc ID 17977 Rev 1 29/42
Application information ST1S14
The content given in Chapter 7.4.1 is valid and the equivalent expression of Equation 37 is:
Equation 40
VFBVIN()
1.22
-----------
5
1.22 TSW⋅
⎛⎞
-----------------------------------
–=
⎝⎠
V
⋅
INTON_MIN
V
DIL
DCR⋅()+()⋅
The Figure 19 plots the Equation 40 considering the foldback current limitation threshold
(1.45A) given in Table 6: Electrical characteristics on page 6.
Equation 40 expresses the worst case scenario as it considers the minimum K gain of the
voltage divider over the entire input voltage range (see Figure 14).
In most of the application conditions the pulse by pulse current limitation with frequency
foldback is effective to limit the inductor current in short circuit condition. The current
foldback helps to decrease the power component stress in persistent short circuit condition.
The hiccup protection offers an additional protection against heavy short circuit condition at
very high input voltage even considering the spread of the minimum conduction time of the
power element. In case the hiccup current level (6.2A typical) is triggered the switching
activity is prevented for 15ms and then a new soft start phase takes place.
Figure 19. Minimum V
for effective pulse by pulse protection over VIN
FB
Figure 20 shows the effectiveness of the constant current protection limiting the inductor
current to the peak current of 1.45A typical during a short circuit event.
30/42 Doc ID 17977 Rev 1
ST1S14 Application information
Figure 20. Short-circuit current VIN = 24V (I
L_PK
= I
FOLD
)
Figure 21 shows the operation of the constant current protection when a short circuit is
applied at the output at the maximum input voltage. Accordingly to Figure 20 the maximum
inductor current escalates over the foldback current limitation.
Figure 21. Short-circuit current V
= 43V (I
IN
L_PK
> I
FOLD
)
Doc ID 17977 Rev 1 31/42
Application information ST1S14
7.5 Application circuit
Figure 22. Evaluation board application circuit
C6 100nFC6 100nF
744314101
L1 10uHL1 10uH
R3
47KR347K
R1 4.7KR1 4.7K
C7
D1
D1
R2
2.7KR22.7K
power plane
150pFC7150pF
small signal
C8
100uFC8100uF
KZE 100u 50V (8 x 11.5)
1210 MLCC
VIN
VIN
TP3
TP3
GND
GND
TP5
TP5
C1C1 C2
10uF
10uF
50V
50V
U1 ST1S14U1 ST1S14
PGOOD
EX-PAD
9
8
SW
2
4
FB
STPS3L60U
STPS3L60U
1
BOOT
7
JP1JP1
1 2
C5
68nF
68nF
50V
50V
C5
C4
C4
100 nF
100 nF
50V
50V
JP2JP2
C2
C3
C3
10uF
10uF
50V
50V
VIN
5
EN2
3
EN1
3
GND
6
Table 11. Component list
Reference Part number Description Manufacturer
C2, C3 UMK325BJ106MM-T
C6,C6
C7
C8 EKZE500ESS101MHB5D
C1,C9,C10,C11 NOT MOUNTED
R1
10 μF 50V
(size 1210)
100nF 50V
(size 0603)
150pF 50V
(size 0603)
100 μF 50V
(size 8 x 11.5 mm)
4.7 KΩ
(size 0603)
Taiyo Yuden
Nippon Chemicon
PGOOD
PGOOD
C9C9 C11C11
C10C10
1210 MLCC
VOUT
VOUT
TP4
TP4
GND
GND
TP7
TP7
TP6
TP6
R2
R3
D1 STPS3L60U
L1 744314850
(size 7 x 6.9 x 4.8 mm)
32/42 Doc ID 17977 Rev 1
I
SAT
=4.5A, I
2.7 KΩ
(size 0603)
47 KΩ
(size 0603)
3A 60V
(size SMB)
8.5μH
RMS
=4A
STMicroelectronics
Wurth
ST1S14 Application information
Figure 23. PCB layout (component side)
Figure 24. PCB layout (bottom side)
Doc ID 17977 Rev 1 33/42
Typical characteristics ST1S14
8 Typical characteristics
Figure 25. Line regulation Figure 26. Load regulation
Figure 27. R
Figure 29. fSW vs temperature Figure 30. Quiescent current vs temperature
vs temperature (VIN = 12 V) Figure 28. VFB vs temperature (VIN = 12 V)
DSon
34/42 Doc ID 17977 Rev 1
ST1S14 Typical characteristics
Figure 31. Shutdown current vs temperature Figure 32. Duty cycle max vs temperature
Figure 33. Efficiency vs I
Figure 35. Efficiency vs I
(VIN 12 V) Figure 34. TJ vs I
OUT
(VIN 24 V) Figure 36. TJ vs I
OUT
(VIN 12 V)
OUT
(VIN 24 V)
OUT
Doc ID 17977 Rev 1 35/42
Typical characteristics ST1S14
Figure 37. Efficiency vs I
(VIN 32 V) Figure 38. TJ vs I
OUT
(VIN 32 V)
OUT
Figure 39. 1 A to 3 A load transient (VIN 12 V) Figure 40. Zoom - 1 A to 3 A load transient (VIN
12 V)
Figure 41. Zoom - 1 A to 3 A rising edge load
transient (V
12 V)
IN
Figure 42. 1 A to 3 A falling edge load
36/42 Doc ID 17977 Rev 1
transient (VIN 24 V)
ST1S14 Typical characteristics
Figure 43. Zoom - 1 A to 3 A rising edge load
transient (V
24 V)
IN
Figure 44. Zoom - 1 A to 3 A falling edge load
transient (VIN 24 V)
Figure 45. 1 A to 3 A load transient (VIN 32 V) Figure 46. Zoom - 1 A to 3 A rising edge load
transient (V
32 V)
IN
Figure 47. Zoom - 1 A to 3 A falling edge load
transient (V
32 V)
IN
Doc ID 17977 Rev 1 37/42
Package mechanical data ST1S14
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK®
38/42 Doc ID 17977 Rev 1
ST1S14 Package mechanical data
Table 12. HSOP8 mechanical data
mm inch
Dim.
Min. Typ. Max. Min. Typ. Max.
A 1.70 0.0669
A1 0.00 0.10 0.00 0.0039
A2 1.25 0.0492
b 0.31 0.51 0.0122 0.0201
c 0.17 0.25 0.0067 0.0098
D 4.80 4.90 5.00 0.1890 0.1929 0.1969
D1 3 3.1 3.2 0.118 0.122 0.126
E 5.80 6.00 6.20 0.2283 0.2441
E1 3.80 3.90 4.00 0.1496 0.1575
E2 2.31 2.41 2.51 0.091 0.095 0.099
e1.27
h 0.25 0.50 0.0098 0.0197
L 0.40 1.27 0.0157 0.0500
k0° (min), 8° (max)
ccc 0.10 0.0039
Figure 48. Package dimensions
Doc ID 17977 Rev 1 39/42
Order code ST1S14
10 Order code
Table 13. Ordering information
Order code Package
ST1S14PHR HSOP8 - exposed pad
40/42 Doc ID 17977 Rev 1
ST1S14 Revision history
11 Revision history
Table 14. Document revision history
Date Revision Changes
27-Oct-2010 1 Initial release
Doc ID 17977 Rev 1 41/42
ST1S14
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