ST1L05B - ST1L05C - ST1L05D
Very low quiescent BiCMOS voltage regulator
Features
■ Fixed output voltage: 1.8 V, 2.5 V, 3.3 V and
ADJ
■ Output voltage tolerance: ± 2 % at 25 °C
■ Output current capability: 1.3 A
■ Very low quiescent current: max 650 µA Over
temperature range
■ Typ. dropout 0.3 V (@ I
■ Enable function for the B, C and D versions
■ Power Good function for the B and D versions
■ Stable with low ESR ceramic capacitors
■ Thermal shutdown protection with hysteresis
■ Overcurrent protection
■ Operating junction temperature range: from 0
to 125 °C
Description
The ST1L05 family is a low drop linear voltage
regulator capable of supplying up to 1.3 A output
current.
=1.3 A)
O
ST1L05 - ST1L05A
DFN8 (4 x 4 mm)DFN6 (3 x 3 mm)
range. The ST1L05 is stable with low ESR output
ceramic capacitors.
Internal protection circuitry includes thermal
protection with hysteresis and overcurrent limiting.
The ST1L05 is especially suitable for data storage
applications such as HDDs, where it can be used
to supply the 3.3 V required by read channel and
memory chips.
The regulator is available in the small and thin
DFN6 (3 x 3) and DFN8 (4 x 4) packages.
The output voltage is fixed at 1.8 V, 2.5 V, 3.3 V
and Adjustable. It is available in three different
versions with different pin outs.
Thanks to BiCMOS technology, the quiescent
current is controlled and maintained below 650 µA
over the entire allowed junction temperature
Table 1. Device summary
Order codes Packages Output voltages
ST1L05PU25R DFN6D (3 x 3 mm) 2.5 V
ST1L05APU33R DFN6D (3 x 3 mm) 3.3 V
September 2009 Doc ID 14492 Rev 2 1/24
ST1L05BPUR DFN6D (3 x 3 mm) ADJ
ST1L05CPU33R DFN6D (3 x 3 mm) 3.3 V
ST1L05DPUR DFN8 (4 x 4 mm) ADJ
www.st.com
24
Contents ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Contents
1 Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Enable function (ST1L05B, ST1L05C and ST1L05D only) . . . . . . . . . . . 16
6.3 Power Good function (ST1L05B and ST1L05D only) . . . . . . . . . . . . . . . . 16
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/24 Doc ID 14492 Rev 2
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Schematic diagrams
1 Schematic diagrams
Figure 1. Schematic diagram for ST1L05
V
V
I
I
V
V
I
I
BandGap
BandGap
reference
reference
OpAmp
OpAmp
Current
Current
limit
limit
Thermal
Thermal
protection
protection
V
V
O
O
VO_
VO_
SENSE
SENSE
R
R
1
1
R
R
2
2
Figure 2. Schematic diagram for ST1L05A
V
V
I
I
BandGap
BandGap
reference
reference
OpAmp
OpAmp
GND
GND
GND
GND
Current
Current
limit
limit
Thermal
Thermal
protection
protection
V
V
I
I
V
V
O
O
R
R
1
1
R
R
2
2
Doc ID 14492 Rev 2 3/24
Schematic diagrams ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Figure 3. Schematic diagram for ST1L05B and ST1L05D
V
V
I
EN
EN
I
BandGap
BandGap
reference
reference
Power-good
Power-good
signal
signal
Current
OpAmp
OpAmp
V
V
I
I
R
R
P
P
Internal
Internal
enable
enable
GND
GND
Current
limit
limit
Thermal
Thermal
protection
protection
PG
PG
V
V
I
I
V
V
O
O
ADJ
ADJ
Figure 4. Schematic diagram for ST1L05C
V
V
I
I
BandGap
BandGap
reference
reference
V
V
I
I
R
R
P
P
EN
EN
Internal
Internal
enable
enable
OpAmp
OpAmp
GND
GND
Current
Current
limit
limit
Thermal
Thermal
protection
protection
Power-good
Power-good
signal
signal
PG
PG
V
V
I
I
V
V
O
O
ADJ
ADJ
4/24 Doc ID 14492 Rev 2
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Pin configuration
2 Pin configuration
Figure 5. Pin connections (top through view)
ST1L05
ST1L05A
ST1L05C
Table 2. Pin description
Pin n°
Symbol
ST1L05 ST1L05A ST1L05B ST1L05C ST1L05D
V
I
V
O
6366 8
4244 6
GND 2 6 2 2 2 Ground pin
ADJ - - 5 - 7 Adjust pin
Supply voltage input pin. Bypass with a 4.7
µF capacitor to GND
Output voltage pin. Bypass with a 4.7 µF
capacitor to GND
ST1L05B
ST1L05D
Function
V
O_SENSE
5--5 -V
sense
O
PG - - 3 - 3 Power Good pin
EN - - 1 1 1 Enable pin. Internal pull-up to V
I
NC 1,3 1,4,5 - 3 4, 5 Not connected
GND EXP Exposed pad must be connected to GND
Doc ID 14492 Rev 2 5/24
Maximum ratings ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
3 Maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
I
V
O
DC supply voltage -0.3 to 7 V
DC output voltage -0.3 to 7 V
PG Power Good pin -0.3 to 7 V
EN Enable pin -0.3 to 7 V
ADJ/V
OUT_SENSE
P
D
I
O
T
OP
T
STG
T
LEAD
1. Storage temperature > 125 °C are acceptable only if the regulator is soldered to a PCBA.
Adjust pin or VO sense 4 V
Power dissipation internally limited W
Output current internally limited A
Operating junction temperature range 0 to 150 °C
Storage temperature range
(1)
-65 to 150 °C
Lead temperature (soldering) 10 Sec. 260 °C
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these condition is not implied.
Table 4. Thermal data
Symbol Parameter DFN6 DFN8 Unit
R
R
thJC
thJA
Thermal resistance junction-case 10 4 °C/W
Thermal resistance junction-ambient 55 40 °C/W
Table 5. ESD data
Symbol Parameter Value Unit
HBM Human body model 2 kV
MM Machine model 150 V
6/24 Doc ID 14492 Rev 2
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Electrical characteristics
4 Electrical characteristics
Refer to the typical application schematic, VI = 3.3 V to 4.5 V, IO = 5 mA to 1.3 A,
C
= CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Typical values are intended at
I
T
= 25 °C unless otherwise specified.
J
Table 6. Electrical characteristics for the ST1L05PU25
Symbol Parameter Test condition Min. Typ. Max. Unit
V
V
ΔV
ΔV
I
I
OMIN
V
I
SVR Supply voltage rejection
eN RMS output noise
ΔVO/ΔIOLoad transient (rising)
ΔVO/ΔIOLoad transient (falling)
ΔVO/ΔVIStart-up transient
ΔVO/ΔI
T
Output voltage VI =3.3V to 5.25V, T=25°C 2.45 2.5 2.55 V
O
Output voltage VI = 3.3V to 5.25V 2.4375 2.5 2.5625 V
O
Line regulation VI = 4.75V to 5.25V 15 mV
O
Load regulation VI = 4.75V, IO = 10mA to 1.3A 15 30 mV
O
Output current limit VI = 5.5V 1.3 A
S
Minimum output current for
regulation
Dropout voltage
d
Quiescent current
Q
(1)
(1)
(1)(2)
(1)(2)
(1)(2)
Short circuit removal response
(1)(2)
O
Thermal shutdown trip point
SH
(1)
1. Guaranteed by design. Not tested in production
=10µF, CO =10µF, all X7R ceramic capacitors.
2. C
I
0mA
I
= 0.8A 0.2 0.4 V
O
= 1A 0.25 0.45 V
I
O
= 1.3A 0.3 0.5 V
I
O
VI = 5V, IO = 2mA to 1.3A, T=25°C 350 500
µA
= 5.5V, IO = 2mA to 1.3A 350 650
V
I
VI = 5±0.5V, IO = 5mA, f=120Hz 50 68 dB
B = 10Hz to 10kHz, VI = 5V,
IO=5mA
VI =5V, any 200mA step from
100mA to 1.3A, t
≥ 1µs
R
0.003 %V
5%V
VI =5V, IO = 1.3A to 10mA, tF ≥ 1µs 2.75 V
VI =0V to 5V, IO = 10mA to 1.3A,
≥ 1µs
t
R
2.75 V
VI =5V, IO = short to 10mA 2.75 V
VI =5V 165 °C
O
O
Doc ID 14492 Rev 2 7/24
Electrical characteristics ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Refer to the typical application schematic, VI = 4.5 V to 5.5 V, IO = 5 mA to 1.3 A,
C
= CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified). Typical values are intended
I
at T
= 25 °C unless otherwise specified.
J
Table 7. Electrical characteristics for ST1L05APU33
Symbol Parameter Test condition Min. Typ. Max. Unit
V
V
ΔV
ΔV
I
I
OMIN
V
I
SVR Supply voltage rejection
eN RMS output noise
ΔVO/ΔIOLoad transient (rising)
ΔVO/ΔIOLoad transient (falling)
ΔVO/ΔVIStart-up transient
ΔV
O
T
Output voltage VI = 4.75V to 5.25V, T=25°C 3.234 3.3 3.366 V
O
Output voltage VI = 4.75V to 5.25V 3.2175 3.3 3.3825 V
O
Line regulation VI = 4.75V to 5.25V 15 mV
O
Load regulation VI = 4.75V, IO = 10mA to 1.3A 15 30 mV
O
Output current limit VI = 5.5V 1.3 A
S
Minimum output current for
regulation
Dropout voltage
d
Quiescent current
Q
(1)
(1)
(1)(2)
(1)(2)
(1)(2)
Short circuit removal response
/ΔI
(1)(2)
O
Thermal shutdown trip point
SH
( 1)
1. Guaranteed by design. Not tested in production.
=10µF, CO =10µF, all X7R ceramic capacitors.
2. C
I
0mA
I
= 0.8A 0.2 0.4 V
O
= 1A 0.25 0.45 V
I
O
I
= 1.3A 0.3 0.5 V
O
V
= 5V, IO = 2mA to 1.3A, T=25°C 350 500
I
= 5.5V, IO = 2mA to 1.3A 350 650
V
I
µA
VI = 5±0.5V, IO = 5mA, f=120Hz 50 65 dB
B = 10Hz to 10kHz, VI = 5V, IO =5mA 0.003 %V
VI =5V, any 200mA step from 100mA
to 1.3A, t
R
≥ 1µs
5%V
VI =5V, IO = 1.3A to 10mA, tF ≥ 1µs 3.6 V
VI =0V to 5V, IO = 10mA to 1.3A,
≥ 1µs
t
R
3.5 V
VI =5V, IO = short to 10mA 3.5 V
VI =5V 165 °C
O
O
8/24 Doc ID 14492 Rev 2
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Electrical characteristics
Refer to the typical application schematic, VI = 4.5 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A,
C
= CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Typical values are intended at
I
T
= 25 °C unless otherwise specified.
J
Table 8. Electrical characteristics for the ST1L05CPU33
Symbol Parameter Test condition Min. Typ. Max. Unit
Output voltage VI = 4.75V to 5.25V, T=25°C 3.234 3.3 3.366 V
O
Output voltage VI = 4.75V to 5.25V 3.2175 3.3 3.3825 V
O
Line regulation VI = 4.75V to 5.25V 15 mV
O
Load regulation VI = 4.75V, IO = 10mA to 1.3A 15 30 mV
O
I
Output current limit VI = 5.5V 1.3 A
S
Minimum output current for
regulation
V
Dropout voltage
d
I
Quiescent current
Q
Enable threshold high VI=4.5V to 5.25, IO = 50mA 2
Enable threshold low VI=4.5V to 5.25, IO= 50mA 0.8
Enable pin current VEN=VI = 5V 2 µA
EN
ΔV
ΔV
I
OMIN
V
EN_H
V
EN_L
I
V
V
SVR Supply voltage rejection
eN RMS output noise
(1)
(1)
0mA
I
= 0.8A 0.2 0.4 V
O
= 1A 0.25 0.45 V
I
O
I
= 1.3A 0.3 0.5 V
O
V
= 5V, IO = 2mA to 1.3A, T=25°C 350 500
I
= 5.5V, IO = 2mA to 1.3A 350 650
V
I
µA
V
VI = 5±0.5V, IO = 5mA, f=120Hz 50 65 dB
B = 10Hz to 10kHz, VI = 5V, IO
=5mA
0.003 %V
O
ΔVO/ΔIOLoad transient (rising)
ΔVO/ΔIOLoad transient (falling)
ΔVO/ΔVIStart-up transient
ΔVO/ΔI
T
1. Guaranteed by design. Not tested in production.
2. C
Short circuit removal response
(1)(2)
O
Thermal shutdown trip point
SH
=10µF, CO =10µF, all X7R ceramic capacitors.
I
(1)(2)
(1)(2)
(1)(2)
VI =5V, any 200mA step from
100mA to 1.3A, tR ≥ 1µs
VI =5V, IO = 1.3A to 10mA, tF ≥ 1µs 3.6 V
VI =0V to 5V, IO = 10mA to 1.3A,
t
≥ 1µs
R
VI =5V, IO = short to 10mA 3.5 V
(1)
VI =5V 165 °C
Doc ID 14492 Rev 2 9/24
5%V
O
3.5 V
Electrical characteristics ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Refer to the typical application schematic, VI = 3 V to 5.5 V, VEN = 2 V, IO = 5 mA to 1.3 A,
C
= CO = 4.7 µF, TJ = 0 to 125 °C, unless otherwise specified. Typical values are intended at
I
T
= 25 °C unless otherwise specified.
J
Table 9. Electrical characteristics for the ST1L05BPU and ST1L05DPU
Symbol Parameter Test condition Min. Typ. Max. Unit
Output voltage VI = 3V to 5.25V, T=25°C 1.195 1.22 1.245 V
O
Output voltage VI = 3V to 5.25V 1.18 1.22 1.256 V
O
Line regulation VI = 4.75V to 5.25V 15 mV
O
Load regulation VI = 4.75V, IO = 10mA to 1.3A 15 30 mV
O
Adjust pin current VI = 3V to 5.25V 1 nA
Output current limit VI = 5.5V 1.3 A
I
S
Minimum output current for
regulation
Dropout voltage
V
d
I
Quiescent current
Q
(1)
Enable threshold high VI=3V to 5.25, IO = 50mA 2
Enable threshold low VI=3V to 5.25, IO= 50mA 0.8
Enable pin current VEN=VI = 5V 2 µA
EN
ΔV
ΔV
I
I
OMIN
V
EN_H
V
EN_L
I
V
V
ADJ
Power Good output threshold
PG
Power Good output voltage
(3)
low
SVR Supply voltage rejection
eN RMS output noise
(3)
ΔVO/ΔIOLoad transient (rising)
ΔVO/ΔIOLoad transient (falling)
(3)
(3)(4)
(3)(4)
1mA
IO = 0.8A, VO=3.3V 0.2 V
I
= 1A, VO=3.3V 0.25 V
O
= 1.3A, VO=3.3V 0.3 V
I
O
= 5V, IO = 2mA to 1.3A, T=25°C 300 500
V
I
= 5.5V, IO = 2mA to 1.3A 350 650
I
Device OFF
(2)
µAV
1
V
Rising edge 0.92V
Falling edge 0.8V
I
=6mA open drain output 0.4 V
SINK
O
O
V
VI = 5±0.5V, IO = 5mA, f=120Hz 50 72 dB
B = 10Hz to 10kHz, VI = 5V,
=5mA
I
O
VI =5V, any 200mA step from
100mA to 1.3A, tR ≥ 1µs
0.003 %V
5%V
VI =5V, IO = 1.3A to 10mA, tF ≥ 1µs 1.38 V
O
O
ΔVO/ΔVIStart-up transient
ΔVO/ΔI
T
Short circuit removal response
(3)(4)
O
Thermal shutdown trip point
SH
(3)(4)
VI =0V to 5V, IO = 10mA to 1A,
tR ≥ 1µs
VI =5V, IO = short to 10mA 1.38 V
(3)
VI =5V 165 °C
1. See minimum start-up voltage, VI = 2.9V.
2. PG pin floating
3. Guaranteed by design. Not tested in production.
=10µF, CO =10µF, all X7R ceramic capacitors.
4. C
I
10/24 Doc ID 14492 Rev 2
1.38 V
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Typical characteristics
5 Typical characteristics
Figure 6. Output voltage vs. temperature Figure 7. Output voltage vs. temperature
1.30
1.30
1.30
1.28
1.28
1.26
1.26
1.24
1.24
1.22
1.22
[V]
[V]
1.20
1.20
O
O
1.18
1.18
V
V
1.16
1.16
1.14
1.14
V
= VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF
V
1.12
1.12
1.10
1.10
Figure 8. Output voltage vs. temperature Figure 9. Output voltage vs. temperature
= VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF
EN
EN
-30 -5 20 45 70 95 120 145
-30 -5 20 45 70 95 120 145
T [°C]
T [°C]
1.30
1.28
1.28
1.26
1.26
1.24
1.24
1.22
1.22
[V]
[V]
1.20
1.20
O
O
1.18
1.18
V
V
1.16
1.16
1.14
1.14
1.12
1.12
1.10
1.10
V
= VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
V
= VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
EN
EN
-30 -5 20 45 70 95 120 145
-30 -5 20 45 70 95 120 145
T [°C]
T [°C]
2.70
2.70
2.65
2.65
2.60
2.60
2.55
2.55
[V]
[V]
2.50
2.50
O
O
V
V
2.45
2.45
2.40
2.40
2.35
2.35
2.30
2.30
Figure 10. Line regulation vs. temperature Figure 11. Load regulation vs. temperature
Line [mV]
Line [mV]
-10
-10
-15
-15
-20
-20
VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF
VI = 5 V, IO = 0.01 A, CI = CO = 4.7 µF
-30-5 20457095120145
-30-5 20457095120145
T [°C]
T [°C]
20
20
V
= VI = from 4.75 to 5.25 V, IO = 0.005 A, C
V
= VI = from 4.75 to 5.25 V, IO = 0.005 A, C
EN
EN
15
15
10
10
5
5
0
0
-5
-5
-30 -5 20 45 70 95 120
-30 -5 20 45 70 95 120
T [°C]
T [°C]
= CO = 4.7 µF
= CO = 4.7 µF
IN
IN
2.70
2.70
VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
2.65
2.65
2.60
2.60
2.55
2.55
[V]
[V]
2.50
2.50
O
O
V
V
2.45
2.45
2.40
2.40
2.35
2.35
2.30
2.30
-30-5 20457095120145
-30-5 20457095120145
T [°C]
T [°C]
50
50
V
= VI = 4.75 V, IO = from 0.01 to 1.3 A, CI = CO = 4.7 µF
V
= VI = 4.75 V, IO = from 0.01 to 1.3 A, CI = CO = 4.7 µF
EN
40
40
30
30
20
20
Load [mV]
Load [mV]
10
10
EN
0
0
-30 -5 20 45 70 95 120 145
-30 -5 20 45 70 95 120 145
T [°C]
T [°C]
Doc ID 14492 Rev 2 11/24
Typical characteristics ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Figure 12. Dropout voltage vs. temperature Figure 13. ESR required for stability with
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
Dropout [V]
Dropout [V]
0.2
0.2
0.1
0.1
CI = CO = 4.7 µF, VO@ 3.3 V
CI = CO = 4.7 µF, VO@ 3.3 V
0
0
-30 -5 20 45 70 95 120 145
-30 -5 20 45 70 95 120 145
T [°C]
T [°C]
IO = 800 mA
IO = 800 mA
IO = 1 A
IO = 1 A
IO = 1.3 A
IO = 1.3 A
0.4
0.4
0.35
0.35
0.3
0.3
0.25
0.25
0.2
0.2
0.15
0.15
0.1
0.1
ESR @ 100kHz [ohm]
ESR @ 100kHz [ohm]
0.05
0.05
0
0
0246810121416182022
0246810121416182022
ceramic capacitors
CI = 4.7 µF, V
CI = 4.7 µF, V
= VI = from 3 V to 5.5 V, IO = from 5 mA to 1.3 A
= VI = from 3 V to 5.5 V, IO = from 5 mA to 1.3 A
EN
EN
Stable zone
Stable zone
CO[µF] (nominal value)
CO[µF] (nominal value)
Figure 14. Quiescent current vs. temperature Figure 15. Quiescent current vs. output
700
700
V
= VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
V
= VI = 5 V, IO = 1.3 A, CI = CO = 4.7 µF
EN
EN
600
600
500
500
400
400
[µA]
[µA]
300
300
Q
Q
I
I
200
200
100
100
0
0
-30 -5 20 45 70 95 120 145
-30 -5 20 45 70 95 120 145
T [°C]
T [°C]
400
400
350
350
300
300
250
250
200
200
[µA]
[µA]
Q
Q
I
I
150
150
100
100
50
50
0
0
current
V
= VI = 5.5 V, CI = CO = 4.7 µF
V
= VI = 5.5 V, CI = CO = 4.7 µF
EN
EN
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
IO [A]
IO [A]
Figure 16. Enable voltage vs. temperature Figure 17. Enable voltage vs. temperature
2.5
2.5
2.5
VI = 3 V, IO = 50 mA, CI = CO = 4.7 µF
VI = 3 V, IO = 50 mA, CI = CO = 4.7 µF
2
2
1.5
1.5
[V]
[V]
EN
EN
V
V
1
1
0.5
0.5
0
0
-30 -5 20 45 70 95 120 145
-30 -5 20 45 70 95 120 145
T [°C]
T [°C]
ON
ON
OFF
OFF
2.5
VI = 5.25 V, IO = 50 mA, CI = CO = 4.7 µF
VI = 5.25 V, IO = 50 mA, CI = CO = 4.7 µF
2
2
1.5
1.5
[V]
[V]
EN
EN
V
V
1
1
0.5
0.5
0
0
-30-520457095120145
-30-520457095120145
T [°C]
T [°C]
12/24 Doc ID 14492 Rev 2
ON
ON
OFF
OFF
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Typical characteristics
Figure 18. Supply voltage rejection vs.
80
80
75
75
70
70
65
65
SVR [dB]
SVR [dB]
60
60
55
55
50
50
-30-5 20457095120145
-30-5 20457095120145
Figure 20. Load transient Figure 21. Short-circuit removal transient
temperature
V
= VI = from 3 to 5.5 V, IO = 5 mA, VO = 1.22 V,
V
= VI = from 3 to 5.5 V, IO = 5 mA, VO = 1.22 V,
EN
EN
= CO = 4.7 µF, F = 120 Hz
= CO = 4.7 µF, F = 120 Hz
C
C
I
I
T[°C]
T[°C]
Figure 19. Supply voltage rejection vs.
frequency
80
80
70
70
60
60
50
50
SVR [dB]
SVR [dB]
40
40
30
30
V
= VI = 3 to 5.5 V, IO = 5 mA, VO = 1.22 V, CI = CO = 4.7 µF
V
= VI = 3 to 5.5 V, IO = 5 mA, VO = 1.22 V, CI = CO = 4.7 µF
EN
EN
20
20
10 100 1000 10000 100000 1000000
10 100 1000 10000 100000 1000000
Frequency [Hz]
Frequency [Hz]
IO=10 mA to 1.3 A, CI=CO=10 µF, VEN=VI=5 V, VO@3.3 V
Figure 22. Line transient Figure 23. Enable transient
V
I
V
O
CI=CO=4.7 µF, VI=3 to 5.5V, IO=5 mA
IO=10 mA to short, CI=CO=10 µF, VEN=VI=5.5 V
V
EN
V
O
CO=CI=4.7 µF, VEN=0 to 2 V, VI=5.5 V, IO=5 mA
Doc ID 14492 Rev 2 13/24
Application information ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
6 Application information
The ST1L05 is a low dropout linear regulator. It provides up to 1.3 A with a low 300 mV
dropout. The input voltage range is from 3 V to 5.5 V. The device is available in fixed and
adjustable output versions.
The regulator is equipped with internal protection circuitry, such as short-circuit current
limiting and thermal protection.
The regulator is designed to be stable with ceramic capacitors on the input and the output.
The expected values of the input and output ceramic capacitors are from 1 µF to 22 µF with
4.7 µF typical. The input capacitor must be connected within 0.5 inches of the V
The output capacitor must also be connected within 0.5 inches of output pin. There is no
upper limit to the value of the input capacitor.
Figure 24, Figure 25, Figure 26 and Figure 27 illustrate the typical application schematics:
Figure 24. Application schematic for the ST1L05
V
V
IN
IN
V
V
IN
IN
ST1L05
ST1L05
V
V
OUT
OUT
V
V
OUT
OUT
terminal.
I
GND
V
V
GND
IN
IN
C
C
I
I
the
Figure 25. Application schematic for the ST1L05A
V
V
IN
IN
C
C
I
I
GND
GND
ST1L05A
ST1L05A
GND
GND
V
V
O_SENSE
O_SENSE
V
V
OUT
OUT
C
C
O
O
V
V
OUT
OUT
C
C
O
O
GND
GND
14/24 Doc ID 14492 Rev 2
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Application information
Figure 26. Application schematic for the ST1L05B and ST1L05D
V
V
IN
IN
V
V
IN
IN
ST1L05B
ST1L05B
ST1L05D
GND
GND
ST1L05D
GND
GND
EN
OFF ON
OFF ON
C
C
I
I
EN
V
V
ADJ
ADJ
PG
PG
OUT
OUT
R1
R1
R2
R2
V
V
OUT
OUT
C
C
O
O
Figure 27. Application schematic for the ST1L05C
V
V
I
C
C
I
I
I
OFF ON
OFF ON
V
V
EN
EN
I
I
GND
GND
For the adjustable version, the output voltage can be adjusted from 1.22 V up to the input
voltage, minus the voltage drop across the PMOS (dropout voltage), by connecting a
resistor divider between the ADJ pin and the output, thus allowing remote voltage sensing.
The resistor divider should be selected using the following equation:
V
O
= V
(1 + R1 / R2) with V
ADJ
It is recommended to use resistors with values in the range of 10 kΩ to 100 kΩ. Lower
values can also be suitable, but will increase current consumption.
ST1L05C
ST1L05C
GND
GND
= 1.22 V (typ.)
ADJ
V
V
O_SENSE
O_SENSE
V
V
O
C
C
O
O
O
V
V
O
O
Doc ID 14492 Rev 2 15/24
Application information ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
6.1 Power dissipation
An internal thermal feedback loop disables the output voltage if the die temperature rises to
approximately 165 °C. This feature protects the device from excessive temperature and
allows the user to push the limits of the power handling capability of a given circuit board
without risk of damaging the device.
It is very important to use a good PC board layout to maximize the power dissipation. The
thermal path for the heat generated by the device is from the die to the copper lead frame
through the package leads and exposed pad to the PC board copper. The PC board copper
acts as a heat sink. The footprint copper pads should be as wide as possible to spread and
dissipate the heat to the surrounding ambient. Feed-through vias to inner or backside
copper layers are also useful in improving the overall thermal performance of the device.
The power dissipation of the device depends on the input voltage, output voltage and output
current, and is given by:
P
= (VI -VO) I
D
The junction temperature of device will be:
O
T
J_MAX
= TA + R
thJA
x P
D
where:
T
T
R
is the maximum junction of the die,125 °C;
J_MAX
is the ambient temperature;
A
is the thermal resistance junction-to-ambient.
thJA
6.2 Enable function (ST1L05B, ST1L05C and ST1L05D only)
The ST1L05B, ST1L05C and ST1L05D features an enable function. When the EN voltage is
higher than 2 V the device is ON, and if it is lower than 0.8 V the device is OFF. In shutdown
mode, consumption is lower than 1 µA.
The EN pin has an internal pull-up, which means that it can be left floating if it is not used.
6.3 Power Good function (ST1L05B and ST1L05D only)
Most applications require a flag showing that the output voltage is in the correct range.
The Power Good threshold depends on the adjust voltage. When the adjust is higher than
0.92*V
0.92*V
Good pin is at high impedance.
, the Power Good (PG) pin goes to high impedance. If the adjust is below
ADJ
the PG pin goes in low impedance. If the device is functioning well, the Power
ADJ
If the output voltage is fixed using an external or internal resistor divider, the Power Good
threshold is 0.92*V
.
O
The use of the Power Good function requires an external pull-up resistor, which must be
connected between the PG pin and V
up to 6 mA. The use of a pull-up resistor for PG in the range of 100 kΩ to 1 MΩ is
recommended. If the Power Good function is not used, the PG pin must remain floating.
16/24 Doc ID 14492 Rev 2
or VO. The typical current capability of the PG pin is
I
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Package mechanical data
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
Doc ID 14492 Rev 2 17/24
Package mechanical data ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
DFN6D (3x3 mm) mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A0.80 1.00 0.031 0.039
A1 0 0.02 0.05 0 0.001 0.002
A3 0.20 0.008
b 0.23 0.45 0.009 0.018
D2.90 3.00 3.10 0.114 0.118 0.122
D2 2.23 2.50 0.088 0.098
E2.90 3.00 3.10 0.114 0.118 0.122
E2 1.50 1.75 0.059 0.069
e0.950.037
L0.30 0.40 0.50 0.012 0.016 0.020
18/24 Doc ID 14492 Rev 2
7946637B
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Package mechanical data
DFN8 (4x4) mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A0.800.90 1.00 0.031 0.035 0.039
A1 0 0.02 0.05 0 0.001 0.002
A3 0.20 0.008
b 0.23 0.300.38 0.009 0.012 0.015
D 3.90 4.00 4.10 0.154 0.157 0.161
D2 2.82 3.00 3.23 0.111 0.118 0.127
E 3.90 4.00 4.10 0.154 0.157 0.161
E2 2.05 2.20 2.30 0.081 0.087 0.091
e0.800.031
L 0.40 0.50 0.60 0.016 0.020 0.024
7869653B
Doc ID 14492 Rev 2 19/24
Package mechanical data ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Tape & Reel QFNxx/DFNxx (3x3) Mechanical Data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N60 2.362
T18.4 0.724
Ao 3.3 0.130
Bo 3.3 0.130
Ko 1.1 0.043
Po 4 0.157
P 8 0.315
20/24 Doc ID 14492 Rev 2
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Package mechanical data
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm. inch.
Dim.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 99 101 3.898 3.976
T 14.4 0.567
Ao 4.35 0.171
Bo 4.35 0.171
Ko 1.1 0.043
Po 4 0.157
P 8 0.315
Doc ID 14492 Rev 2 21/24
Package mechanical data ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
Figure 28. DFN6 (3x3) footprint recommended data
Figure 29. DFN8 (4 x 4) footprint recommended data
22/24 Doc ID 14492 Rev 2
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D Revision history
8 Revision history
Table 10. Document revision history
Date Revision Changes
29-Feb-2008 1 First release.
08-Sep-2009 2 Modified Table 1 on page 1.
Doc ID 14492 Rev 2 23/24
ST1L05, ST1L05A, ST1L05B, ST1L05C, ST1L05D
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24/24 Doc ID 14492 Rev 2
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