– 2 x USB 2.0 Host
– USB 2.0 Device
– Giga Ethernet (GMII port)
2
–I
C and fast IrDA interfaces
– 3 x SSP Synchronous serial peripheral
(SPI, Microwire or TI protocol) ports
– 2 x UART interfaces
■ Peripherals supported:
– TFT/STN LCD controller (resolution up to
1024 x 768 and colors up to 24 bpp)
– Touchscreen support
■ Miscellaneous functions
– Integrated real-time clock, watchdog, and
system controller
– 8-channel 10-bit ADC, 1 Msps
– JPEG codec accelerator
– 10 GPIO bidirectional signals with interrupt
capability
– 10 independent 16-bit timers with
programmable prescaler
■ 32-bit width External local bus (EXPI interface).
■ 3 x I
■ Customizable logic with 600 Kgate standard
■ Software:
Applications
■ The SPEAr
Table 1.Device summary
2
S interfaces for audio features:
– One stereo input and two stereo outputs
(audio 3.1 configuration capable)
cell array
– System compliant with all operating
systems (including Linux)
®
embedded MPU family targets
networked devices used for communication,
display and control. This includes diverse
consumer, business, industrial and life science
applications such as:
– IP phones, thin client computers, printers,
programmable logic controllers, PC
docking stations,
– Medical lab/diagnostics equipment,
wireless access devices, home appliances,
residential control and security systems,
digital picture frames, and bar-code
scanners/readers.
Order code
SPEAR600-2 -40 to 85 °C
Tem p.
range
PackagePacking
PBGA420
(23 x 23 x
2.06 mm)
Tr ay
May 2012Doc ID 16259 Rev 3 1/97
This is information on a product in full production.
The SPEAr600 is a member of the SPEAr family of embedded MPUs for networked devices,
it is based on dual ARM926EJ-S processors (up to 333 MHz), widely used in applications
where high computation performance is required.
Both processors have an MMU supporting virtual memory management and making the
system compliant with the Linux operating system. They also offer 16 KBytes of data cache,
16 KBytes of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug
operations.
To expand its range of target applications, SPEAr600 can be extended by adding additional
peripherals through the external local bus (EXPI interface).
Figure 1.Functional block diagram
8/97Doc ID 16259 Rev 3
SPEAr600Description
1.1 Main features
●Dual core ARM926EJ-S 32-bit RISC CPU, up to 333 MHz, each with:
–16 Kbytes of instruction cache, 16 Kbytes of data cache
–3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code
density, byte Java mode (Jazelle™) for direct execution of Java code.
–Tightly Coupled Memory
–AMBA bus interface
●32-KByte on-chip BootROM
●8-KByte on-chip SRAM
●Dynamic memory controller managing external DDR1 memory up to 166 MHz and
●Two USB 2.0 host (high-full-low speed) with integrated PHY transceiver
●One USB 2.0 device (high-full speed) with integrated PHY transceiver
●10 GPIO bidirectional signals with interrupt capability
●JPEG codec accelerator 1clock/pixel
●ADC 10-bit, 1 Msps 8 inputs/1-bit DAC
●3 SSP master/slave (supporting Motorola, Texas instruments, National Semiconductor
protocols) up to 40 Mbps
2
●I
C master/slave interface (slow/ fast/high speed, up to 1.2 Mb/s)
●10 independent 16-bit timers with programmable prescaler
●I/O peripherals
–Two UARTs (speed rate up to 460.8 kbps)
–Fast IrDA (FIR/MIR/SIR) 9.6 Kbps to 4 Mbps speed-rate
●Audio block with 3-I2Ss interfaces to support Audio Play (Up to 3.1) and Audio Record
functionality.
●Advanced power saving features
–Normal, Slow, Doze and Sleep modes, CPU clock with software-programmable
frequency
–Enhanced dynamic power-domain management
–Clock gating functionality
–Low frequency operating mode
–Automatic power saving controlled from application activity demands
●Vectored interrupt controller
●System and peripheral controller
Doc ID 16259 Rev 3 9/97
DescriptionSPEAr600
–RTC with separate power supply allowing battery connection
–Watchdog timer
–Miscellaneous registers array for embedded MPU configuration.
●External local bus (EXPI I/f) that is an AMBA AHB like interface
●Programmable PLLs for CPU and system clocks
●JTAG IEEE 1149.1 boundary scan
●ETM functionality multiplexed on primary pins.
●Supply voltages
–1.0 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs 1.8 V RTC and 3.3 V I/Os
●Operating temperature: - 40 to 85 °C
●ESD rating: HBM class 2, CDM class II
●PBGA420 (23 x 23 x 2.06 mm, pitch 1 mm)
10/97Doc ID 16259 Rev 3
SPEAr600Architecture overview
Clock, Reset
32 kHz30 MHz
RTC
8-Channel DMA
10 Timers / WD
8 KB Embed. SRAM
32 KB Embed. ROM
ADC
TouchScreenTouchScreen
ARM 926EJ
up to 333 MHz
MMU
Interrupt/
Syst controller
DDR
memory
controller
DDR2DDR2
DDR1DDR1
FSMC
EEPROMEEPROM
SMI
FLASHFLASH
Debug, TraceDebug, Trace
JTAG
ETM9
LCD
controller
USB2.0 PHYdevice
USB2.0 PHY
device
I2C
Internet
Access
Phy
FIdDA
3xSSPUart2Uart1
USB2.0 PHYHost
USB2.0 PHY
Host
USB2.0 PHYHost
USB2.0 PHY
Host
ARM 926EJ
up to 333 MHz
MMU
Interrupt/
Syst controller
3xI2SEXPI I/f
NAND FlashNAND Flash
SPEAr600
RAS
2 Architecture overview
Figure 2. shows an example of a typical SPEAr600 based system.
Figure 2.Typical system architecture using SPEAr600
The core of the SPEAr600 is the dual ARM926EJ-S reduced instruction set computer
(RISC) processor.
It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off
between high performance and high code density and includes features for efficient
execution of Java byte codes.
Each ARM CPU:
●Is clocked at a frequency up to 333 MHz
●Embeds 16 Kbytes instruction cache + 16 Kbytes data cache
●Features a memory management unit (MMU) which makes it fully compliant with Linux
The SoC includes three major subsystems logic domains which control the following
and VxWorks operating systems.
function blocks:
Configurable Cell Array Subsystem
This block contains the Reconfigurable Array Subsystem logic (RAS) made by an array of
600Kgate equivalent standard cells freely customizable by means of a few metal and via
mask layer changes during the customization process. The programmable logic allows
reducing the SoC NRE cost, the development cycle time improving the devices time to
Doc ID 16259 Rev 3 11/97
Architecture overviewSPEAr600
market. The user custom logic can be configured using the following SoC internal
resources:
●130 Kbyte of static memory arranged in four 32 KB macro group and one 2 KB group.
●Up to 17 selectable source clocks (either internal or external)
●DMA support (up to 16 configurable dma input/output request lines)
●Power management I/F
●Interrupts line (12 outputs - 64 inputs)
●4 AHB output master ports interconnected with the multi-channel memory controller
●5 AHB input slave ports
●1 interconnection port with the Expansion Interface bus (EXPI)
●9 LVDS (8 outputs - 1 input) signals
●88/112 PL_GPIOs primary input/output signals
Caution:PL GPIO pins are not configurable by software.
Common Subsystem
This block consists of four different logic subsystems used to control the SoC basic
functions:
●I/O connectivity:
–Low speed: UARTs, SSPs, I2C and IrDA
–High speed: MII 10/100/1000, USB 2.0 host and devices
●Hardware accelerator: JPEG-codec and DMA
●Video: Color LCD interface
●Common resources: Timers, GPIOs, RTC and Watchdog
●Power management functionality
●SoC configurability: Miscellaneous control logic
CPU Subsystem
The SPEAr600 has a symmetric processor architecture with:
●2 equivalent subsystems including the ARM926 and its private subsystem logic
(GPIOs, Interrupt controller and Timer) providing the essential hardware resources to
support a generic Operating System
●The subsystem is replicated twice so both processors have the same memory map.
This structure enables a true symmetric multi-processor architecture were both
processors can simultaneously execute the same OS (all interrupt sources are handled
by both processors)
●All internal peripherals are shared, allowing flexible and efficient software partitions.
●High aggregate throughput can be sustained by splitting critical tasks either onto
additional CPUs and optional hardware accelerator engines.
●Both processors are equipped with ICE and ETM configurable debug interfaces. for
real-time CPU activity tracing and debugging.
4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode is supported,
with normal or half-rate clock.
The internal architecture is also based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix. The switch matrix structure
12/97Doc ID 16259 Rev 3
SPEAr600Architecture overview
allows different subsystem data flows to be executed in parallel improving the core platform
efficiency.
High performance master agents are directly interconnected with the memory controller
reducing the memory access latency. The overall memory bandwidth assigned to each
master port can be programmed and optimized through an internal efficient weighted roundrobin arbitration mechanism.
2.1 Embedded memory units
The SPEAr600 has two embedded memory units
●32 Kbytes of BootROM
●8 Kbytes of SRAM
2.2 DDR/DDR2 memory controller
SPEAr600 integrates a high performance multi-channel memory controller able to support
DDR1 and DDR2 double data rate memory devices. The multi-port architecture ensures that
memory is shared efficiently among different high-bandwidth client modules.
●Internal efficient port arbitration scheme to ensure high memory bandwidth utilization
●Programmable register interface to control memory device parameters and protocols
●DRAM controller supports both DDR1 and DDR2 memory devices:
–DDR1 up to 166 MHz
–DDR2 up to 333 MHz
●Memory frequency with DLL enable configurable from 100 MHz to 333 MHz
●Wide range of memory devices supported:
–128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit, 2 Gbit
–Two chip selects.
–8 or 16-bit data width
2.3Serial memory interface
SPEAr600 provides a Serial Memory Interface (SMI), acting as an AHB slave interface
(32-, 16- or 8-bit) to SPI-compatible off-chip memories.
These serial memories can be used either as data storage or for code execution.
Doc ID 16259 Rev 3 13/97
Architecture overviewSPEAr600
Main features:
●Supports the following SPI-compatible Flash and EEPROM devices:
–STMicroelectronics M25Pxxx, M45Pxxx
–STMicroelectronics M95xxx, except M95040, M95020 and M95010
–ATMEL AT25Fxx
–YMC Y25Fxx
–SST SST25LFxx
●Acts always as a SPI master and supports up to 3 SPI slave memory devices (with
separate chip select signals), with up to 16 MB address space each
●SMI clock (SMICLK) is generated by SMI (and input to all slaves) using a clock
provided by the AHB bus
●SMI_CLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can
be controlled by 7 programmable bits.
2.4 Flexible static memory controller
Root part number 1 provides Flash Nand Static Memory Controller (FSMC) which is
intended to interface an AHB bus to external NAND Flash memories.
Main purpose of FSMC is then:
●Translate AHB protocol into the appropriate external storage device protocol
●Meet the timing of the external devices, slowing down and counting an appropriate
number of HCLK (AHB clock) cycles to complete the transaction to the external device
Note:The external storage device cannot be faster than one AHB cycle.
Main features of the FSMC are listed below:
●The FSMC is an AMBA slave module connected to the AHB
●Provides an interface between AHB system bus and Nand Flash memory devices with
8 and 16 bits wide data paths
●FSMC performs only one access at a time and only one external device is accessed
●Support little-endian and big-endian memory architectures
●Handles AHB burst transfers to reduce access time to external devices
●Supplies an independent configuration for each memory bank
●Provides programmable timings to support a wide range of devices:
–Programmable wait states (up to 31)
–Programmable bus turn around cycles (up to 15)
–Programmable output enable and write enable delays (up to 15)
●Provides only one chip select for the first memory bank
●Shares the address bus and the data bus with all the external peripherals, whereas
only chips selects are unique for each peripheral
●Offers an external asynchronous wait control
●Offers configurable size at reset for boot memory bank using external control pins.
14/97Doc ID 16259 Rev 3
SPEAr600Architecture overview
2.5 Multichannel DMA controller
Within its basic subsystem, SPEAr600 provides a DMA controller (DMAC) able to service up
to 8 independent DMA channels for serial data transfers between a single source and
destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to-memory, and
peripheral-to-peripheral).
Each DMA channel can support unidirectional transfers, with one internal four-word FIFO
per channel.
2.6 LCD controller
Main features:
●Resolution programmable up to 1024 x 768
●16-bpp true-color non-palletized, for color STN and TFT
●24-bpp true-color non-palletized, for color TFT
●Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8-
bit interfaces
●Supports single and dual-panel color and monochrome STN displays
●Supports thin film transistor (TFT) color displays
●15 gray-level mono, 3375 color STN, and 32 K color TFT support
●1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN
●1, 2, 4 or 8-bpp palletized color displays for color STN and TFT
●Programmable timing for different display panels
●256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line
and pixel clock signals
●AC bias signal for STN and data enable signal for TFT panels patented gray scale
algorithm
●Supports little-endian, big-endian and WinCE data formats
2.7 GPIOs
The General Purpose Input/Outputs (GPIOs) provide programmable inputs or outputs.
Each input/output can be controlled in two distinct modes:
●Software mode, through an APB interface
●Hardware mode, through a hardware control interface.
SPEAr600 provides up to 10 GPIO lines:
●Individually programmable input/output pins (default to input at reset)
●An APB slave acting as control interface in "software mode"
●Programmable interrupt generation capability on any number of pins
●Bit masking in both read and write operations through address lines
Doc ID 16259 Rev 3 15/97
Architecture overviewSPEAr600
2.8 JPEG codec
Main features:
●Compliance with the baseline JPEG standard (ISO/IEC 10918-1)
●Single-clock per pixel encoding/decoding
●Support for up to four channels of component color
●8-bit/channel pixel depths
●Programmable quantization tables (up to four)
●Programmable Huffman tables (two AC and two DC)
●Programmable minimum coded unit (MCU)
●Configurable JPEG headers processing
●Support for restart marker insertion
●Use of two DMA channels and of two 8 x 32-bits FIFOs (local to the JPEG) for efficient
transferring and buffering of encoded/decoded data from/to the codec core.
2.9 8-channel ADC
Main features:
●Successive approximation ADC
●10-bit resolution @1 Msps
●Hardware over sampling and accumulation up to 128 samples
●Eight analog input (AIN) channels, ranging from 0 to 2.5 V
●INL ± 1 LSB, DNL ± 1 LSB
●Programmable conversion speed, (min. conversion time is 1 µs)
●Programmable averaging of results from 1 (No averaging) up to 128
2.10 Ethernet controller
Main features:
●Supports the default Gigabit Media Independent Interface (GMII)/Media Independent
Interface (MII) defined in the IEEE 802.3 specifications.
●Supports 10/100/1000 Mbps data transfer rates with any one or a combination of the
above PHY interfaces
●Supports both half-duplex and full-duplex operation. In half-duplex operation,
CSMA/CD protocol is provided for, as well as packet bursting and frame extension at
1000 Mbps
●Programmable frame length to support both Standard and Jumbo Ethernet frames with
size up to 16 Kbytes
●32-bit data transfer interface on system-side
●A variety of flexible address filtering modes are supported
●A set of control and status registers (CSRs) to control GMAC Core operation.
●Complete network statistics with RMON Counters (MMC, MAC Management
Counters).
16/97Doc ID 16259 Rev 3
SPEAr600Architecture overview
●Native DMA with single-channel Transmit and Receive engines, providing 32/64/128-bit
data transfers
●DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining
●A set of CSRs to control DMA operation
●An AHB slave acting as programming interface to access all CSRs, for both DMA and
GMAC core subsystems
●An AHB master for data transfer to system memory
●32-bit AHB master bus width, supporting 32-bit wide data transactions
●Supports both big-endian and little-endian byte ordering
●Power Management Module (PMT) with Remote Wake-up and Magic Packet frame
processing options
2.11 USB2 host controller
SPEAr600 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks:
●EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)
●OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)
●Local 2-Kbyte FIFO
●Local DMA
●Integrated USB2 transceiver (PHY)
Both hosts can manage an external power switch, providing a control line to enable or
disable the power, and an input line to sense any over-current condition detected by the
external switch.
Both host controllers can perform high speed transfer simultaneously.
2.12 USB2 device controller
Main features:
●Supports 480 Mbps high-speed mode (HS) for USB 2.0, as well as 12 Mbps full-speed
(FS) and the low-speed (LS modes) for USB 1.1
●Supports 16 physical endpoints, which can be assigned to different interfaces and
configurations to implement logical endpoints
●Integrated USB transceiver (PHY)
●Local 4 Kbyte FIFO shared by all endpoints
●DMA mode and slave-only mode are supported
●In DMA mode, the UDC supports descriptor-based memory structures in application
memory
●In both modes, an AHB slave is provided by UDC-AHB, acting as programming
interface to access to memory-mapped control and status registers (CSRs)
●An AHB master for data transfer to system memory is provided, supporting 8, 16, and
32-bit wide data transactions on the AHB bus
●A USB plug detect (UPD) which detects the connection of a cable.
Doc ID 16259 Rev 3 17/97
Architecture overviewSPEAr600
2.13Synchronous Serial Peripheral (SSP)
The SPEAR600 has three Synchronous Serial Peripherals (SSPs) (SPI, Microwire or TI
protocol).
Main features:
●Maximum speed of 40 Mbps
●Programmable choice of interface protocol:
–SPI (Motorola)
–Microwire (National Semiconductor)
–TI synchronous serial
●Programmable data frame size from 4 to 16-bit.
●Master and slave mode capability.
●DMA interface
2.14 I2C
Main features:
●Compliance to the I
2
●I
C v2.0 compatible.
●Supports three modes:
–Standard (100 kbps)
–Fast (400 kbps)
–High-speed (3.4 Mbps)
●Master and slave mode configuration possible
●Slave Bulk data transfer capability
●DMA interface
2
C bus specification (Philips)
2.15 UARTs
The SPEAr600 has two UARTs.
Main features:
●Hardware flow control
●Separate 16x8 (16 locations deep x 8 bits wide) transmit and 16 x 12 receive FIFOs to
reduce CPU interrupts
●Speed up to 3 Mbps
18/97Doc ID 16259 Rev 3
SPEAr600Architecture overview
2.16 Fast IrDA controller
The SPEAr600 has a Fast IrDA controller.
Main features:
●Supports the following standards:
–IrDA serial infrared physical layer specification (IrPHY), version 1.3
–IrDA link access protocol (IrLAP), version 1.1
●Supports the following infrared modes and baud rates:
–Serial infrared (SIR), with rates 9.6 kbps, 19.2 kbps, 38.4 kbps, 57.6 kbps and
115.2 kbps
–Medium Infrared (MIR), with rates 576 kbps and 1.152 Mbps
–Fast Infrared (FIR), with rate 4 Mbps
●Transceiver interface compliant to all IrDA transceivers with configurable TX and RX
signal polarity
●Half-duplex infrared frame transmission and reception
●16-bit CRC algorithm for SIR and MIR, and 32-bit CRC algorithm for FIR
●Generates preamble, start and stop flags
●Uses the RZI (Return-to-Zero Inverted) modulation/demodulation scheme for SIR and
MIR, and the 4PPM (4 Pulse Position Modulation) modulation/demodulation scheme
for FIR
●Provides synchronization by means of a DPLL in FIR mode
●Easily adaptable to different bus systems with 32-bit register interface and FIFO with
configurable FIFO size
2.17 I2S audio block
SPEAr600 contains three I2S interfaces providing the following features.
Main features:
●Conversion of AHB protocol to I
●Supports 2.0, 2.1 and 3.1 audio outputs (I
●32 (16L + 16R) and 64 bit (32L + 32R) of raw PCM data length supported
The System Controller provides an interface for controlling the operation of the overall
system.
Main features:
●Power saving system mode control
●Crystal oscillator and PLL control
●Configuration of system response to interrupts
2
S protocol and vice versa
2
S master mode)
Doc ID 16259 Rev 3 19/97
Architecture overviewSPEAr600
●Reset status capture and soft reset generation
●Watchdog module clock enable
2.18.1 Power saving system mode control
Using three mode control bits, the system controller switch the SPEAr600 to any one of four
different modes: DOZE, SLEEP, SLOW and NORMAL.
●SLEEP mode: In this mode the system clocks, HCLK and CLK, are disabled and the
System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz).
When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters
DOZE mode. Additionally, the operating mode setting in the system control register
automatically changes from SLEEP to DOZE.
●DOZE mode: In this mode the system clocks, HCLK and CLK, and the System
Controller clock SCLK are driven by a low speed oscillator. The System Controller
moves into SLEEP mode from DOZE mode only when none of the mode control bits
are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL
mode is required the system moves into the XTAL control transition state to initialize the
crystal oscillator.
●SLOW mode: During this mode, both the system clocks and the System Controller
clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes
into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode
control bits are set, the system goes into the "Switch from XTAL" transition state.
●NORMAL mode: In NORMAL mode, both the system clocks and the System Controller
clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the
system goes into the "Switch from PLL" transition state.
2.19 Clock and reset system
The clock system is a fully programmable block that generates all the clocks for the
SPEAr600.
The default operating clock frequencies are:
●Clock @ 333 MHz for the CPUs.
●Clock @ 166 MHz for AHB bus and AHB peripherals. (PLL1 source)
●Clock @ 83 MHz for, APB bus and APB peripherals. (PLL1 source)
●Clock @ 12 MHz, 30 MHz and 48 MHz for USBs (PLL3 source)
The above frequencies are the maximum allowed values.
All these clocks are generated by three PLLs.
PLL1 and PLL2 sources are fully programmable through dedicated registers.
The clock system consists of 2 main parts: a multi clock generator block and two internal
PLLs.
The multi clock generator block, takes a reference signal (which is usually delivered by the
PLL), generates all clocks for the IPs of SPEAr600 according to dedicated programmable
registers.
20/97Doc ID 16259 Rev 3
SPEAr600Architecture overview
Each PLL uses an oscillator input of 30 MHz to generate a clock signal at a frequency
corresponding to the highest of the group. This is the reference signal used by the multi
clock generator block to obtain all the other required clocks for the group. Its main feature is
electromagnetic interference reduction capability.
The user can set up the PLL in order to modulate the VCO with a triangular wave. The
resulting signal has a spectrum (and power) spread over a small programmable range of
frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic
emissions. This method replaces all the other traditional methods of EMI reduction, such as
filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal
shielding and so on. This gives the customer appreciable cost savings.
In sleep mode the SPEAr600 runs with the PLL disabled so the available frequency is 30
MHz or a sub-multiple (/2, /4, /16 and /32) or 32 KHz.
PLL3 is used to generate the USB controller clocks and it is not configured through
registers.
2.20 Vectored interrupt controller (VIC)
Each ARM Subsystem of SPEAr600 offers Vectored Interrupted Controller (VIC) blocks,
providing a software interface to the interrupt system.
Acting as an interrupt controller, the VIC determines the source that is requesting service
and where its interrupt service routine (ISR) is loaded, doing that in hardware.
In particular, the VIC supplies the starting address, or vector address, of the ISR
corresponding to the highest priority requesting interrupt source.
Main features of the VIC are listed below:
●Support for 32 standard interrupt sources (a total of 64 lines are available for each CPU
from its two daisy-chained VICs).
●Generation of both Fast Interrupt request (FIQ) and Interrupt Request (IRQ. IRQ is
used for general interrupts, whereas FIQ is intended for fast, low-latency interrupt
handling.
●Support for 16 vectored interrupts (IRQ only);
●Hardware interrupt priority
–FIQ interrupt has the highest priority
–followed by vectored IRQ interrupts, from vector 0 to vector 15
–then non-vectored IRQ interrupts with the lowest priority
●Interrupt masking/ interrupts request status
●Software interrupt generation
2.21 General purpose timers
SPEAr600 provides five general purpose timers (GPTs) acting as APB slaves.
Each GPT consists of 2 channels, each one made up of a programmable 16-bit counter and
a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock
division by 1 up to 256, and different input frequencies can be chosen through SPEAr600
configuration registers (frequencies up to 83 MHz can be synthesized).
Doc ID 16259 Rev 3 21/97
Architecture overviewSPEAr600
Two different modes of operation are available:
●Auto-reload mode, an interrupt source is activated, the counter is automatically cleared
and then it restarts incrementing.
●Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT
is disabled.
2.22 Watchdog timer
The ARM watchdog module consists of a 32-bit down counter with a programmable time-out
interval that has the capability to generate an interrupt and a reset signal on timing out. The
watchdog module is intended to be used to apply a reset to a system in the event of a
software failure.
2.23 RTC oscillator
The RTC provides a 1-second resolution clock. This keeps time when the system is inactive
and can be used to wake the system up when a programmed alarm time is reached. It has a
clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a
secured time update.
Main features:
●Time-of-day clock in 24 hour mode
●Calendar
●Alarm capability
●Isolation mode, allowing RTC to work even if power is not supplied to the rest of the
The Reconfigurable Logic Array consists of an embedded macro where it is possible to
implement a custom project by mapping up to 600k equivalent standard cells. The user can
design custom logic and special function using various features offered by the
Reconfigurable Logic Array and by the SPEAr600 system listed here below.
●4 AHB bus master interfaces
●5 AHB bus slave interfaces
●Dedicated interface with CPU1 to customize the Tightly Couple Memory
●Dedicated interface with CPU1 to customize the Coprocessor
●Dedicated interface with CPU2 to customize the Tightly Coupled Memory
●Interfaces towards a dedicated 130 kB Memory Array Subsystem provided of functional
BIST driven by SoC via software and divided in the following ST memory cuts:
–3 single port memory cuts (48 words x 128 bits)
–4 single port memory cuts (2048 words x 32 bits)
–8 single port memory cuts (1024 words x 32 bits)
–16 single port memory cuts (512 words x 32 bits)
–8 dual port memory cuts (512 words x 32 bits)
22/97Doc ID 16259 Rev 3
SPEAr600Architecture overview
–4 dual port memory cuts (1024 words x 32 bits)
●Clock system constituted by:
–5 clocks coming from the external balls
–4 clocks coming from the integrated frequency synthesizers
–CPU core clock frequency
–Pll2 frequency
–48 MHz clock (USB Pll)
–30 MHz clock (Main Oscillator)
–32.768 kHz clock (RTC Oscillator)
–APB clock (programmable)
–AHB clock (programmable)
–User Configurable sync/async clock towards Memory Controller port 2 (M2)
●Connection with 84/112 I/Os
●Connection with 9 LVDS lines
●12 interrupt lines towards CPU1 and CPU2
●64 interrupt input lines from the various platform IP sources
●16 peripheral DMA request lines
●64 user configurable (in the SoC) general purpose input lines
●64 user configurable (in the RAS) general purpose output lines
●SoC dynamic power management control interface;
●50 specific ATE Test interface signals dedicated to RAS
2.25 External Port Controller (EXPI I/F)
The port controller is a socket communication interface between the SPEAr600 and an
external FPGA device; it implements a simple AHB bidirectional protocol used to compress
a couple of std AHB master/slave bus onto 84 PL_GPIOs and 4 PL_CLK primary signals.
Caution:PL_GPIO pins are not configurable by software.
ST provide a symmetric port controller logic solution to be embedded inside the external
FPGA with the purpose of interfacing the EXPI bus directly and decompressing the same
pair of AHB master/slave ports on the FPGA side in order to interconnect the customer logic
as follows (more slave and master agents can be connected to the EXPI):
SPEAr600_AHB-master >> FPGA_AHB-slave
SPEAr600_AHB-slave << FPGA_AHB-master (AHB-full)
The EXPI interface is based on two main groups of signals:
●AHB bidirectional signal bus driven alternatively from the SPEAr600 and FPGA side.
●Unidirectional signals continuously driven from both the SPEAr600 and FPGA sides.
Table 36: EXPI - pad signal assignment lists the EXPI signal names. Further details in these
signals are given in the SPEAr600 user manual (UM0510)
Doc ID 16259 Rev 3 23/97
Pin descriptionSPEAr600
3 Pin description
The following tables describe the pinout of the SPEAr600 listed by functional block.
This description refers to the default configuration of SPEAr600 (full features).
More details on the configuration of each pin are given in Table 16: Multiplexing scheme.
●Ta b le 2: S y stem reset, master clock, RTC and configuration pins
●Ta b le 3: Pow e r supply pins
●Table 4: Debug pins
●Table 5: SMI, SSP, UART, FIRDA and I2C pins
●Table 6: USB pins
●Table 7: Ethernet pins
●Table 8: GPIO pins
●Ta b le 9: A D C p i n s
●Table 10: NAND Flash I/F pins
●Table 11: DDR I/F pins
●Table 12: LCD I/F pins
●Table 13: LVDS I/F pins
●Table 14: EXPI/I2S pins
●Table 15: EXPI pins
List of abbreviations:
PU = Pull Up
PD = Pull Down
3.1 Required external components
1.DDR_COMP_1V8: place an external 121 kΩ resistor between ball V7 and ball V8
2. DDR_COMP_2V5: place an external 121 k
3. USB_RREF: connect an external 1.5 k
4. DIGITAL_REXT: place an external 121 k
Ω
resistor between ball V9 and ball V8
Ω
pull-down resistor to ball U4
Ω
resistor between ball E11 and ball E126.
3.2 Pin descriptions listed by functional block
Table 2.System reset, master clock, RTC and configuration pins
GroupSignal nameBallDirectionFunctionPin type
SYSTEM
RESET
MRESETC17InputMain reset
TTL Schmitt
trigger input
buffer,
3.3 V tolerant, PU
CONFIGDIGITAL_REXTE11RefConfiguration
24/97Doc ID 16259 Rev 3
Analog,
3.3 V capable,
See Note 4
SPEAr600Pin description
Table 2.System reset, master clock, RTC and configuration pins (continued)
GroupSignal nameBallDirectionFunctionPin type
Master
clock
MCLK_XIY1Input30 MHz crystal I
MCLK_XOY2Output30 MHz crystal O
RTC_XIA9Input32 kHz crystal I
RTC
RTC_XOB9Output32 kHz crystal O
Table 3.Power supply pins
GroupSignal nameBallValue
J9, J10, J11, J12, J13, J14, K9, K10,
K11, K12, K13, K14, L9, L10, L11,
GND
L12, L13, L14, M9, M10, M11, M12,
M13, M14, N9, N10, N11, N12, N13,
N14, P9, P10, P11, P12, P13, P14,
DIGITAL
GROUND
RTC_GNDEA10
M18, N18, P18, T5, V6
DITH_VSSU5
DDR_MEM_PLL_VSS_DIGU17
DIGITAL_GNDBGCOMPE12
ADC_AGNDV16
DDR_MEM_PLL_VSS_ANAV17
USB_VSSC2V5T4
USB_HOST1_VSSBSR1
Oscillator,
2.5 V capable
Oscillator,
1.8 V capable
0 V
USB_HOST2_VSSBSN2
ANALOG
GROUND
USB_DEV_VSSBSU2
USB_PLL_VSSP2V5W2
I/OVDDE3V3
COREVDD
HOST1/HOST2
USB PHY
HOST2 USB
PHY
USB_HOST_VDD3V3R33.3V
USB_HOST2_VDDBCN12.5 V
USB_HOST2_VDDBSN31.0 V
USB_PLL_VSSPW3
MCLK_GNDY3
MCLK_GNDSUBAA3
DITH_VSS2V5V5
J6, H6, F8, F9, F16, H17, K17, L17,
N17, P17, M6, F17
G6, L6, G17, M17, R17, F10, F13,
F15, J17, T6, U13, U10, U16
Doc ID 16259 Rev 3 25/97
0 V
3.3 V
1.0 V
Pin descriptionSPEAr600
Table 3.Power supply pins (continued)
GroupSignal nameBallValue
HOST1 USB
PHY
USB_HOST1_VDDBCP32.5 V
USB_HOST1_VDDBSR21.0 V
USB_DEV_VDDBCU12.5 V
DEVICE USB
PHY
USB_DEV_VDDBSU31.0 V
USB_DEV_VDD3V3T33.3 V
USB_PLL_VDDPV31.0 V
USB PLL
USB_PLL_VDDP2V5W12.5 V
OSCI (MASTER
CLOCK)
MCLK_VDDAA11.0 V
MCLK_VDD2V5AA22.5 V
DITH_VDD2V5V42.5 V
PLL1
DITH_VDDU61.0 V
DDR I/O
(1)
SSTL_VDDE1V8U7, U8, U9, U11, U12, U14, U151.8/2.5 V
ADCADC_AVDDW162.5 V
DDR_MEM_PLL_VDD_ANAW172.5 V
PLL2
DDR_MEM_PLL_VDD_DIGT171.0 V
LVDS I/OLVDS_VDDE2V5F11, F12, F142.5 V
OSCI RTCRTC_VDDE_1V8B101.8 V
1. For DDRI the supply voltage must be 2.5 V, instead for DDRII the supply voltage must be 1.8 V.
26/97Doc ID 16259 Rev 3
SPEAr600Pin description
Table 4.Debug pins
GroupSignal nameBallDirectionFunctionPin type
BOOT_SELK18InputBoot selection
TEST_0E15
TEST_1E14
TEST_2D14
Input
TEST_3D13
Configuration
ports
TEST_4E13
TEST_5D12
DEBUG
nTRSTD17InputTest reset Input
TDOE17OutputTest data outpuT
TCKE16InputTest clock
TDID16InputTest data input
TMSD15InputTest mode select
TTL input
buffer, 3.3 V
tolerant, PD
TTL Schmitt
trigger, input
buffer, 3.3 V
tolerant, PU
TTL output
buffer, 3.3 V
capable, 4 mA
TTL Schmitt
trigger, input
buffer, 3.3 V
tolerant, PU
Table 5.SMI, SSP, UART, FIRDA and I2C pins
GroupSignal nameBallDirectionFunctionPin type
Serial Flash
input data
Serial Flash
output data
Serial Flash
clock
Serial Flash
chip selects
SMI
SMI_DATAINL21Input
SMI_DATAOUTL20
SMI_CLKL22
Output
SMI_CS_0L19
SMI_CS_1L18
TTL input
buffer, 3.3 V
TTL output
buffer, 3.3 V
capable,
4 mA
Doc ID 16259 Rev 3 27/97
Pin descriptionSPEAr600
Table 5.SMI, SSP, UART, FIRDA and I2C pins (continued)
GroupSignal nameBallDirectionFunctionPin type
SSP
UART
SSP_1_MOSIAA21
SSP_1_MISOAB21
Master out
slave in
Master in slave
out
SSP_1_SCLKAB22Serial clock
SSP_1_SSAA22Slave select
SSP_2_MOSIK20
SSP_2_MISOK21
I/O
Master out
slave in
Master in slave
out
SSP_2_SCLKK22Serial clock
SSP_2_SS_0K19Slave select
SSP_3_MOSIJ20
SSP_3_MISOJ21
Master out
slave in
Master in slave
out
SSP_3_SCLKJ22Serial clock
SSP_3_SSJ19Slave select
UART1_TXDAA19
OutputSerial data out
UART2_TXDAA20
UART1_RXDAB19
InputSerial data in
UART2_RXDAB20
TTL bidir
buffer, 3.3 V
capable,
8 mA,
3.3 V tolerant,
(1)
PU
TTL output
buffer, 3.3 V
capable, 4 mA
TTL input
buffer, 3.3 V
tolerant, PD
FIRDA_TXDAA18OutputSerial data out
FIRDA
FIRDA_RXDAB18InputSerial data in
SDAY18I/O
I2C
SCLY19I/OSerial clock
1. When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
28/97Doc ID 16259 Rev 3
Serial data
in/out
TTL output
buffer, 3.3 V
capable, 4mA
TTL input
buffer, 3.3 V
tolerant, PU
TTL bidir
buffer, 3.3V
capable, 4 mA,
3.3 V tolerant,
PU
SPEAr600Pin description
Table 6.USB pins
GroupSignal nameBallDirectionFunctionPin type
USB
USB_DEV_DPV1
USB Device D+
I/O
USB_DEV_DMV2USB Device D-
USB_DEV_VBUSR4Input
USB_HOST1_DPT1
I/O
USB Device
VBUS
USB HOST1
D+
USB_HOST1_DMT2USB HOST1 D-
USB_HOST1_VBUSP5Output
USB_HOST1_OVRCP6Input
USB_HOST2_DPP1
I/O
USB HOST1
VBUS
USB Host1
Over-current
USB HOST2
D+
USB_HOST2_DMP2USB HOST2 D-
Bidirectional
analog buffer,
5V tolerant
TTL input buffer,
3.3 V tolerant,
PD
Bidirectional
analog buffer
5V tolerant
TTL output
buffer, 3.3 V
capable, 4 mA
TTL input buffer,
3.3V tolerant,
active low
Bidirectional
analog buffer,
5V tolerant
USB_HOST2_VBUSR5Output
USB_HOST2_OVRCR6Input
USB_USB_RREFU4Output
USB HOST2
VBUS
USB Host2
Over-current
Ext.Reference
resistor
TTL output
buffer, 3.3 V
capable, 4 mA
TTL input buffer,
3.3 V tolerant,
active low
Analog, see
Note 3 on
page 24
Doc ID 16259 Rev 3 29/97
Pin descriptionSPEAr600
Table 7.Ethernet pins
GroupSignal nameBallDirectionFunctionPin type
Ethernet
GMII_TXCLKF22Output
Transmit clock
(GMII)
GMII_TXCLK125E22InputExt. Clock
MII_TXCLKD22I/O
Transmit clock
MII
TXD_0F21
TXD_1E21
Output
TXD_2F20
TXD_3E20
Transmit data
GMII_TXD_4D21
GMII_TXD_5D20
I/O
GMII_TXD_6C22
GMII_TXD_7C21
TX_ERD18
Transmit errorTTL output buffer,
Output
TX_END19Transmit enable
RX_ERC20
RX_DVC19
Receive error
Receive data
valid
TTL output buffer,
3.3 V capable,
8mA
TTL input buffer,
3.3 V tolerant, PD
TTL output buffer,
3.3 V capable,
8mA
TTL bidirectional
buffer, 3.3 V
capable, 8 mA,
3.3 V tolerant, PD
3.3 V capable,
8mA
RX_CLKA22Receive clock
RXD_0B22
Input
RXD_1B21
RXD_2A21
RXD_3B20
Receive data
GMII_RXD_4A20
GMII_RXD_5B19
I/O
GMII_RXD_6A18
GMII_RXD_7A19
COLA17
Collision detect
Input
CRSB17Carrier sense
MDIOB18I/O
MDCC18Output
Management
data I/O
Management
data clock
TTL input buffer,
3.3 V tolerant, PD
TTL bidirectional
buffer, 3.3 V
capable, 8 mA,
3.3 V tolerant, PD
TTL input buffer,
3.3 V tolerant, PD
TTL bidirectional
buffer, 3.3 V
capable, 4 mA,
3.3 V tolerant, PD
TTL output buffer,
3.3 V capable,
4mA
30/97Doc ID 16259 Rev 3
SPEAr600Pin description
Table 8.GPIO pins
GroupSignal nameBallDirectionFunctionPin type
GPIO_0W18
GPIO_1V18
GPIO_2U18
GPIO
GPIO_3T18
GPIO_4W19
GPIO_5V19
GPIO_6U19
I/O
General
purpose I/O
TTL bidirectional
buffer, 3.3 V
capable, 8mA,
3.3 V tolerant,
PU
GPIO_7T19
GPIO_8R19
GPIO_9R18
1. When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
Table 9.ADC pins
GroupSignal nameBallDirectionFunctionPin Type
AIN_0W11
AIN_1V11
AIN_2V12
ADC
AIN_3W12
AIN_4W13
AIN_5V13
Input
ADC analog
input channel
Analog buffer,
2.5 V tolerant
AIN_6V14
AIN_7W14
ADC_VREFNW15
ADC_VREPV15
ADC negative
voltage
ADC positive
voltage
(1)
Doc ID 16259 Rev 3 31/97
Pin descriptionSPEAr600
Table 10.NAND Flash I/F pins
GroupSignal nameBallDirectionFunctionPin Type
NF_IO_0H19
NF_IO_1H18
TTL bidirectional
buffer,
3.3 V capable,
4mA,
3.3 V tolerant,
(1)
PU
TTL output buffer,
3.3 V capable,
4mA, active low
NAND
FLASH
I/F
NF_IO_2G19
NF_IO_3G18
I/OData
NF_IO_4F19
NF_IO_5F18
NF_IO_6E18
NF_IO_7E19
NF_CEG20
Chip enable
NF_REG22Read enable
NF_WEH20Write enable
NF_ALEH21
NF_CLEG21
Output
Address latch
enable
Command latch
enable
TTL output buffer,
3.3 V capable,
4mA
NF_WPJ18Write protect
NF_RBH22InputRead/busy
1. When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
TTL input buffer
3.3 V tolerant, PU
32/97Doc ID 16259 Rev 3
SPEAr600Pin description
Table 11.DDR I/F pins
GroupSignal nameBallDirectionFunctionPin type
DDR_ADD_0AB3
DDR_ADD_1AB4
DDR_ADD_2AA4
DDR_ADD_3Y4
DDR_ADD_4W4
DDR_ADD_5W5
DDR_ADD_6Y5
DDR_ADD_7AA5
DDR_ADD_8AB5
DDR_ADD_9AB6
DDR_ADD_10AA6
DDR_ADD_11Y6
DDR_ADD_12W6
DDR_ADD_13W7
Output
Address
line
SSTL_2/
SSTTL_18
DDR
I/F
DDR_ADD_14Y7
DDR_BA_0Y9
DDR_BA_1W9
Output
Bank
select
DDR_BA_2W10
DDR_RASAB7
Row strobe
DDR_CASAA7Column strobe
Output
DDR_WEAA8Write enable
DDR_CLKENAB8Clock enable
DDR_CLK_PAA9
DifferentialDifferential
Output
DDR_CLK_NAB9Clock
DDR_CS_0Y8
Chip select
Output
DDR_CS_1W8Chip select
DDR_ODT_0AB2
Output
On-die
Termination
DDR_ODT_1AB1Enable lines
DDR_DATA_0AB11
DDR_DATA_1AA10
DDR_DATA_2AB10
I/O
Data lines
(lower byte)
DDR_DATA_3Y10
DDR_DATA_4Y11
SSTL_2/
SSTTL_18
SSTL_2/
SSTTL_18
Doc ID 16259 Rev 3 33/97
Pin descriptionSPEAr600
Table 11.DDR I/F pins (continued)
GroupSignal nameBallDirectionFunctionPin type
DDR_DATA_5Y12
DDR_DATA_6AB12
DDR_DATA_7AA12
DDR_DQS_0AB13
DDR_nDQS_0AA13
I/O
Data lines
(Lower byte)
Differential lower
Data Strobe
SSTL_2
/SSTTL_18
Differential
SSTL_2/
SSTTL_18
DDR
I/F
DDR_DM_0AA11Output
DDR_GATE_0Y13I/OLower gate open
DDR_DATA_8AB15
DDR_DATA_9AA16
DDR_DATA_10AB16
DDR_DATA_11Y16
I/O
DDR_DATA_12Y15
DDR_DATA_13Y14
DDR_DATA_14AB14
DDR_DATA_15AA14
DDR_DQS_1AB17I/O
DDR_nDQS_1AA17Data strobe
DDR_DM_1AA15Output
DDR_GATE_1Y17I/O
DDR_VREFV10InputRef. voltageAnalog
Lower data
mask
Data lines
(Upper byte)
Differential
upper
Upper data
mask
Upper gate
open
SSTL_2/
SSTTL_18
Differential
SSTL_2/
SSTTL_18
SSTL_2/
SSTTL_18
DDR_COMP_2V5V9RefExt. ref resistor
DDR_COMP_GN
D
DDR_COMP_1V8V7RefExt. ref. resistor
DDR2_END11InputConfiguration
34/97Doc ID 16259 Rev 3
V8-
Common return
for Ext. resistors
Analog, see
Note 2 on
page 24
Power
Analog, see
Note 1 on
page 24
TTL input buffer,
3.3 V tolerant, PU
SPEAr600Pin description
Table 12.LCD I/F pins
GroupSignal nameBallDirectionFunctionPin Type
CLD_0Y20
CLD_1Y21
CLD_2Y22
CLD_3W22
CLD_4W21
CLD_5W20
CLD_6V20
CLD_7V21
CLD_8V22
CLD_9U22
CLD_10U21
LCD I/F
CLD_11U20
LCD Data
CLD_12T20
CLD_13T21
CLD_14R21
CLD_15R20
CLD_16P19
CLD_17P20
Output
CLD_18P21
CLD_19N21
CLD_20N20
CLD_21N19
CLD_22M20
CLD_23M21
STN AC bias
CLACT22
drive TFT Data
Enable
CLCPR22
LCD Panel
STN Frame
CLFPP22
Pulse\TFT
Vertical Sync
STN Line
CLLPN22
Pulse\TFT
Horizontal Sync
CLLEM22Line End
CLPOWERM19
LCD Power
Enable
TTL output buffer,
3.3 V capable,
8mA
Clock
Doc ID 16259 Rev 3 35/97
Pin descriptionSPEAr600
Table 13.LVDS I/F pins
GroupSignal nameBallDirectionFunctionPin Type
PH0A16
PH0nB16
PH1C16
PH1nC15
PH2A15
PH2nB15
PH3A14
PH3nB14
PH4C14
LVDS I/F
PH4nC13
PH5A13
PH5nB13
PH6A12
PH6nB12
Output
General
purpose I/O
With LVDS
transceiver
LVDS Driver
PH7C12
PH7nC11
PH8A11
PH8nB11
InputLVDS Receiver
36/97Doc ID 16259 Rev 3
SPEAr600Pin description
Table 14.EXPI/I2S pins
GroupSignal nameBallDirectionFunctionPin Type
EXPI/I2S
PL_GPIO_47/
ADO_REC_DIN
PL_GPIO_48/
ADO_REC_WS
PL_GPIO_50/
ADO_WS_OUT
PL_GPIO_51/
ADO_DOUT2
PL_GPIO_52/
ADO_DOUT1
PL_GPIO_53/
ADO_CLK_in_529
PL_GPIO_54/
MCLK_out_309
PL_GPIO_55/
ADO_RECORD_CLK
PL_CLK_4/
ADO_CLK_OUT
C2
C1
A1
B2
I/OLogic I/O
A2
C3
B3
A3
A4Output
Logic External
Clock
TTL bidirectional
buffer
3.3 V capable,
3.3 V tolerant,
4mA,
(1)
PU
TTL bidirectional
buffer, 3.3 V
capable, 8 mA,
3.3 V tolerant,
(1)
PU
1. When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed.
Doc ID 16259 Rev 3 37/97
Pin descriptionSPEAr600
Table 15.EXPI pins
GroupSignal nameBallDirectionFunctionPin Type
PL_GPIO_0P4
PL_GPIO_1N4
PL_GPIO_2N5
PL_GPIO_3N6
PL_GPIO_4M5
PL_GPIO_5M4
PL_GPIO_6M3
PL_GPIO_7M2
PL_GPIO_8M1
PL_GPIO_9L1
PL_GPIO_10L2
PL_GPIO_11L3
PL_GPIO_12L4
PL_GPIO_13L5
TTL bidirectional
buffer
3.3 V capable,
3.3 V tolerant,
4mA,
(1)
PU
EXPI
PL_GPIO_14K6
PL_GPIO_15K5
I/OLogic I/O
PL_GPIO_16K4
PL_GPIO_17K3
PL_GPIO_18K2
PL_GPIO_19K1
PL_GPIO_20J1
PL_GPIO_21J2
PL_GPIO_22J3
PL_GPIO_23J4
PL_GPIO_24J5
PL_GPIO_25H5
PL_GPIO_26H4
PL_GPIO_27H3
PL_GPIO_28H2
PL_GPIO_29H1
PL_GPIO_30G1
PL_GPIO_31G2
38/97Doc ID 16259 Rev 3
SPEAr600Pin description
Table 15.EXPI pins (continued)
GroupSignal nameBallDirectionFunctionPin Type
PL_GPIO_32G3
PL_GPIO_33G4
PL_GPIO_34G5
PL_GPIO_35F5
PL_GPIO_36F4
PL_GPIO_37F3
PL_GPIO_38F2
PL_GPIO_39F1
PL_GPIO_40E4
PL_GPIO_41E3
TTL bidirectional
buffer
3.3 V capable,
4mA,
3.3 V tolerant,
(1)
PU
EXPI
PL_GPIO_42E2
PL_GPIO_43E1
I/OLogic I/O
PL_GPIO_44D3
PL_GPIO_45D2
PL_GPIO_46D1
PL_GPIO_49B1
PL_GPIO_56B4
PL_GPIO_57C4
PL_GPIO_58D4
PL_GPIO_59E5
PL_GPIO_60D5
PL_GPIO_61C5
PL_GPIO_62B5
PL_GPIO_63B6
Doc ID 16259 Rev 3 39/97
Pin descriptionSPEAr600
Table 15.EXPI pins (continued)
GroupSignal nameBallDirectionFunctionPin Type
PL_GPIO_64C6
PL_GPIO_65D6
PL_GPIO_66E6
PL_GPIO_67F6
PL_GPIO_68F7
PL_GPIO_69E7
PL_GPIO_70D7
PL_GPIO_71C7
TTL bidirectional
buffer
3.3 V capable,
3.3 V tolerant,
4mA,
(1)
PU
EXPI
PL_GPIO_72B7
PL_GPIO_73E8
PL_GPIO_74D8
PL_GPIO_75C8
PL_GPIO_76B8
PL_GPIO_77A8
PL_GPIO_78C9
Logic I/O
I/O
PL_GPIO_79D9
PL_GPIO_80E9
PL_GPIO_81E10
PL_GPIO_82D10
PL_GPIO_83C10
PL_CLK_1A7
PL_CLK_2A6
Logic External
Clock
PL_CLK_3A5
1. When the pin is not driven, the output voltage is 2.5 V, On the core side, logic ‘1’ state is guaranteed
TTL bidirectional
buffer, 3.3 V
capable, 8 mA,
3.3 V tolerant,
PU
(1)
40/97Doc ID 16259 Rev 3
SPEAr600Pin description
3.3 Configuration modes
The previous tables show the connectivity of the pins in the default configuration mode (full
features). On top of this SPEAr600 can be also configured in different modes.
This section describes the main operating modes created by disabling some IPs to enable
other ones.
The following modes can be selected by setting the TEST_0 .. TEST_5 pins at the
appropriate values. This setting is used to program the control register (SOC_CFG_CTR)
present in the Miscellaneous registers block (MISC). Please refer to the section 11.4.3 of the
SPEAr600 reference manual (RM0305)
●Mode 0: Full features
●Mode 1: Disable_nand_flash
●Mode 2: Disable_LCD_ctr
●Mode 3: Disable_GMAC_ctr
●Mode 4: self_cfg4
●Mode 5: self_cfg5
●Mode6: Full RAS
●Mode7: All_Process_disable
Table 16: Multiplexing scheme shows all the alternate functions available in each mode.
Mode 0 is the default mode for SPEAr600.
3.3.1 Full features
Default configuration, I/O standard features.
3.3.2 Disable NAND Flash
The NAND Flash interface is disabled and alternatively the following features are provided:
●UART extension for modem flow control
●One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user
manual for more details).
3.3.3 Disable LCD ctr
The Color LCD controller interface is disabled and alternatively the following features are
provided:
●UART extension for modem flow control
●One additional clock programmable trought GPT registers. Please refer to the
SPEAr600 user manual (UM0510) for more details.
●Additional 8 data lines of NAND Flash interface not otherwise available.
●One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user
manual for more details).
Doc ID 16259 Rev 3 41/97
Pin descriptionSPEAr600
3.3.4 Disable GMAC ctr
The GMAC interface is disabled and alternatively the following features are provided:
●Two UARTs : one with extension for modem flow control and one with simplified
hardware flow control
●One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user
manual for more details).
●Four additional clocks programmable trough the GPT registers. Please refer to the
SPEAr600 user manual (UM0510) for more details.
3.3.5 Self cfg_4
In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this
mode source clock and reset signals are provided from the external application logic.
3.3.6 Self cfg_5
In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this
mode source clock and reset signals are internally provided.
3.3.7 All processors disabled
This mode configures the SoC as an I/O slave target device controlled by an external master
application (the internal processors can be disabled).
This product contains devices to protect the inputs against damage due to high/low static
voltages. However it is advisable to take normal precaution to avoid application of any
voltage higher/lower than the specified maximum/minimum rated voltages.
The Absolute maximum rating is the maximum stress that can be applied to a device without
causing permanent damage. However, extended exposure to minimum/maximum ratings
may affect long-term device reliability.
Table 19.Absolute maximum ratings
SymbolParameterMinimum valueMaximum valueUnit
1.0Supply voltage at 1.0- 0.31.2V
V
DD
V
3.3Supply voltage at 3.3- 0.33.9V
DD
2.5Supply voltage at 2.5- 0.33V
V
DD
V
1.8Supply voltage at 1.8- 0.32.16V
DD
T
STG
T
J
Storage temperature-55150°C
Junction temperature-40125°C
5.2 Maximum power consumption
The following table includes the maximum current and power consumption for each power
domain.
Note:These values take into consideration the worst cases of process variation and voltage range
and must be used to design the power supply section of the board.
Table 20.Maximum current and power consumption
SymbolDescriptionMaxUnit
V
1.0Supply voltage at 1.0 V1000mA
DD
V
1.8Supply voltage at 1.8 V
DD
V
2.5Supply voltage at 2.5 V22mA
DD
V
3.3Supply voltage at 3.3 V
DD
V
RTCSupply voltage at 1.8 V10µA
DD
P
D
1. Average current with Linux memory test [50% write and 50% read] plus DMA reading memory.
2. With 30 logic channels connected to the device and simultaneously switching at 10 MHz.
Maximum power consumption1500
(1)
(2)
130mA
60mA
(3)
mW
Doc ID 16259 Rev 3 55/97
Electrical characteristicsSPEAr600
3. The maximum current and power values listed above, obtained with typical supply voltages, are not
guaranteed to be the highest obtainable. These values are dependent on many factors including the type of
applications running, clock rates, use of internal functional capabilities, external interface usage, case
temperature, and the power supply voltages. Your specific application can produce significantly different
results.
1 V current and power are primarily dependent on the applications that are running and the use of internal
chip functions (DMA, USB, Ethernet, and so on).
3.3 V current and power are primarily dependent on the capacitive loading, frequency, and utilization of the
external buses.
5.3DC electrical characteristics
The recommended operating conditions are listed in the following table:
Table 21.Recommended operating conditions
SymbolParameterMinTypMaxUnit
V
1.0Supply voltage at 1.00.9511.10V
DD
V
3.3Supply voltage at 3.333.33.6V
DD
V
2.5Supply voltage at 2.52.252.52.75V
DD
V
1.8Supply voltage at 1.81.701.81.9V
DD
V
RTCSupply voltage at 1.81.621.81.98V
DD
T
A
T
J
Ambient temperature-4085°C
Junction temperature-40125°C
5.4 Overshoot and undershoot
This product can support the following values of overshoot and undershoot.
Table 22.Overshoot and undershoot specifications
Parameter3V3 I/Os2V5 I/Os1V8 I/Os
Amplitude500 mV500 mV500 mV
Ratio of overshoot (or undershoot) duration with respect to
pulse width
If the amplitude of the overshoot/undershoot increases (decreases), the ratio of
overshoot/undershoot width to the pulse width decreases (increases). The formula relating
the two is:
1/31/31/3
Amplitude of OS/US = 0.75*(1- ratio of OS (or US) duration with respect to pulse width)
Note:The value of overshoot/undershoot should not exceed the value of 0.5 V. However, the
duration of the overshoot/undershoot can be increased by decreasing its amplitude.
56/97Doc ID 16259 Rev 3
SPEAr600Electrical characteristics
5.5 3.3V I/O characteristics
The 3.3 V I/Os are compliant with JEDEC standard JESD8b
Table 23.Low voltage TTL DC input specification (3 V< VDD <3.6 V)
SymbolParameterMinMaxUnit
V
IL
V
IH
Low level input voltage0.8V
High level input voltage2V
VhystSchmitt trigger hysteresis300800mV
Table 24.Low voltage TTL DC output specification (3 V< VDD <3.6 V)
SymbolParameterTest ConditionMinMaxUnit
V
OL
V
OH
1. For the max current value (X mA) refer to Section 3: Pin description.
Table 25.Pull-up and pull-down characteristics
Low level output voltageIOL= X mA
High level output voltageIOH= -X mA
SymbolParameterTest ConditionMin.MaxUnit
R
PU
R
PD
Equivalent pull-up resistanceVI = 0 V2967KΩ
Equivalent pull-down
resistance
5.6 DDR2 pin characteristics
(1)
(1)
V
- 0.3V
DD
V
= V
I
3V329103KΩ
DDE
0.3V
Table 26.DC characteristics
SymbolParameterTest ConditionMin.MaxUnit
V
V
V
hyst
Table 27.Driver characteristics
Low level input voltage
IL
High level input voltage
IH
Input voltage hysteresis200mV
SSTL2-0.3V
SSTL18-0.3V
SSTL2V
SSTL18V
+0.15V
REF
+0.125V
REF
-0.15V
REF
-0.125V
REF
2V5+0.3V
DDE
1V8+0.3V
DDE
SymbolParameterMinTypMaxUnit
Output impedance (strong value)18.92123.1Ω
R
O
Output impendance (weak value)32.93537.1Ω
Doc ID 16259 Rev 3 57/97
Electrical characteristicsSPEAr600
2.95 us
MRESET
resets_o
sclk
npor_o
hresetn
pll_lock
17 scl k clock
cycles ( at 30MHz)
All Vdd are
stable
OSCI 3 0MHz
synch
synch
60 clock
cycles
synch
Pll lock time (note 2)
DOZE MODE
NORMAL
MODE
arm_fetching
10 ms
Table 28.On die termination
SymbolParameterMin.Typ.MaxUnit
RT1*
RT2*
Table 29.Reference voltage
Termination value of resistance for on die
termination
Termination value of resistance for on die
termination
SymbolParameterMin.Typ.MaxUnit
V
REFIN
Voltage applied to core/pad
5.7 Power up sequence
No particular sequence is required. It is only required that the various power supplies reach
the correct range in less than 10 msec.
5.8 Power on reset (MRESET)
The MRESET must remain active for at least 10 ms after all the power supplies are in the
correct range and should become active in no more than 10 µs when one of the power
supplies goes out of the correct range.
0.49 *
V
DDE
75Ω
150Ω
0.500 *
V
DDE
0.51 *
V
DDE
V
Figure 3.Power on reset timing diagram
58/97Doc ID 16259 Rev 3
SPEAr600Electrical characteristics
Note:1The oscillator generates a stable clock 1.5 ms after the power supply becomes stable.
2The Pll lock time is given by the following formula:
Lock time = 4 ms / (decimal equivalent of PLL charge pump bit setting + 1)
The PLL charge pump (CP) bits are in the PLL1/2_CTR register in the Miscellaneous
register block. Please refer to the user manual for more details.
For example, if the application software sets CP = 01110 = 14 (decimal), then:
The characterization timing is done considering an output load of 10 pF on all the DDR
pads. The operating conditions are in worst case V = 0.90 V T
V=1.10 V T
= 40 °C.
A
6.1.1 DDR2 read cycle timings
Figure 4.DDR2 read cycle waveforms
= 125 °C and in best case
A
Figure 5.DDR2 read cycle path
Table 31.DDR2 read cycle path timings without pad delay
Rising best133 ps212 ps125 ps244 ps
Falling best134 ps205 ps127 ps239 ps
Rising worst336 ps611 ps311 ps646 ps
Falling worst348 ps550 ps324 ps590 ps
t3
MAX
Table 32.DDR2 read cycle timings without pad delay
(t1 + t2)
MIN
t3
MIN
(t1 + t2)
MAX
Period (T)Frequencyt4
3 ns333 MHz814 ps343 ps
3.75 ns266 MHz996 ps532 ps
60/97Doc ID 16259 Rev 3
MAX
t5
MAX
SPEAr600Timing characteristics
t4
t5
t5t4
DQS
DQ
t4
t5
Table 32.DDR2 read cycle timings without pad delay (continued)
Period (T)Frequencyt4
5 ns200 MHz1.31 ns842 ps
6 ns166 MHz1.56 ns1.10 ns
7.5 ns133 MHz1.93 ns1.47 ns
MAX
t5
MAX
Ta bl e 3 2 shows the internal chip timing without the contribution of the pads.
These values are obtained considering the nominal setting of DLL at T/4 period, in fact, the
DDR memory launches data (DQ) and data strobe (DQS) aligned. Internally the DQS is
delayed by T/4 (DLL) to guarantee correct data capture.
The waveforms in Figure 4 refers to the pad or memory side: so the data move around the
edges of DQS signals. In this case, we consider the maximum values for t4 and t5 to obtain
the minimum data valid window. For correct data capture (at the controller side) the last
arrival time of the data (last variation) must precede the first arrival of the data strobe:
t4
= DQS (delay)
MAX
- DQ (delay)
MIN
MAX
= (t1
t3
MAX
MIN
+ t2
+ T/4 ±one DLL element
MIN
(a)
) -
t5 can be expressed in a similar way:
t5
= DQ (delay)
MAX
element
- DQS (delay)
MIN
(a)
) = T/4 + t3
MIN
MAX
- t1
= (T/2 + t3
- t2
MAX
) - (t1
MIN
± one DLL element
MAX
MAX
+ t2
+ T/4 ± one DLL
MAX
(a)
Note:DQS (delay) is the combination of delays experienced by the DQS (data strobe) signal, DQ
(delay) is the combination of delays experienced by the DQ (data) signal (both until the
capture is performed by the controller).
DQS (delay) depends on t1 and t2 while DQ (delay) depends on t3.
6.1.2 DDR2 write cycle timings
Figure 6.DDR2 write cycle waveforms
a. The value “one DLL element” stands for the DLL accuracy, so we put ± one DLL element in the formulas. One
DLL element = 15 ps in best case and 85 ps in worst case.
Doc ID 16259 Rev 3 61/97
Timing characteristicsSPEAr600
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
t1t2
DLL2
t3
DQS
DQ
CLK
DLL1
Figure 7.DDR2 write cycle path
Table 33.DDR2 write cycle path timings without pad delay
t3
MAX
(t1 + t2)
MIN
t3
MIN
(t1 + t2)
MAX
Rising best2.19 ns2.08 ns1.91 ns2.13 ns
Falling best2.21 ns2.11 ns1.95 ns2.15 ns
Rising worst5.55 ns5.28 ns5.2 ns5.33 ns
Falling worst5.54 ns5.30 ns5.3 ns5.35 ns
Table 34.DDR2 write cycle timings without pad delay
Period (T)Frequencyt4
MIN
t5
MIN
3 ns333 MHz396 ps492 ps
3.75 ns266 MHz585 ps681 ps
5 ns200 MHz895 ps991 ps
6 ns166 MHz1.15 ns1.25 ns
7.5 ns133 MHz1.52 ns1.62 ns
Ta bl e 3 4 shows the internal chip timing without the contribution of the pads.
These values are obtained considering the nominal setting of DLL at T period for DQS path
and T*3/4 for DQ path, in fact the memory controller launches data (DQ) and data strobe
(DQS) misaligned. Internally the clock is delayed by T to produce the DQS and the same
clock is delayed by T*3/4 to clock the data DQ, in order to perform a correct write to the
memory. The table values are measured in a particular pad configuration:
Drive strength = strong (zprog_out = L)
Slope : prog_a = L ; prog_b = H (corresponding to 266 MHz)
The waveforms in Figure 6 refer to the pad or memory side, so the DQS edges are centered
on the data valid window. In this case, we consider the minimum values for t4 and t5 in order
to obtain the minimum data valid window. For a correct data write (on the memory side) the
last variation of the data must precede the first arrival of the data strobe. In other words, we
can consider t4 as the t
62/97Doc ID 16259 Rev 3
of the data that can be defined as the time range where the
SETUP
SPEAr600Timing characteristics
t4t5
CLK
ADDRESS, STROBEs,
and CONTROL LINES
Q
Q
SET
CLR
D
t2
t3
CLK
ADDRESS, STROBEs,
and CONTROL LINES
ADDRESS, STROBEs,
and CONTROL LINES
CLK
data are stable before the arrival of the DQS. To have a positive quantity the delay obtained
by the DQ (maximum delay or last variation) must be less than one obtained by the DQS
(minimum delay).
So:
t4
= DQS (delay)
MIN
± one DLL element
- DQ (delay)
MIN
(a)
+ t3
MAX
MAX
) = t1
= (t1
+ T/4 + t2
MIN
+ T ± one DLL element
MIN
± one DLL element
MIN
t5 can be expressed in a similar way, and can be defined as the t
t5
= DQ (delay)
MIN
(t1
+ T ± one DLL element
MAX
= T/4 + t3
MIN
- t2
- DQS (delay)
MIN
- t1
MAX
MAX
(a)
+ t2
MAX
± one DLL element
MAX
= (T/2 + T*3/4 ± one DLL element
) =
(a)
HOLD
(a)
+ t2
MIN
(a)
- t3
of the data:
(a)
+ t3
) - (T*3/4
MAX
) -
MIN
Note:DQS (delay) is the combination of delays experienced by the DQS (data strobe) signal, DQ
(delay) is the combination of delays experienced by the DQ (data) signal (both until the
capture performed by the controller).
6.1.3DDR2 command timings
Figure 8.DDR2 command waveforms
Figure 9.DDR2 command path
For the command and control timings, we have to consider that the commands are launched
on the negative edge of the clock and are captured on the next positive edge of the clock.
a. The value “one DLL element” stands for the DLL accuracy, so we put ± one DLL element in the formulas. One
DLL element = 15 ps in best case and 85 ps in worst case.
Doc ID 16259 Rev 3 63/97
Timing characteristicsSPEAr600
Therefore, we have to add the value T to the clock path and the value T/2 to the command
path.
The waveform shown in Figure 8 refers to the pad or memory side, so the CLK edges are
centered on the command valid window. In this case, we consider the minimum values for t4
and t5 in order to obtain the minimum command valid window. We can consider t4 as the
t
of the commands that can be defined as the time range where the commands are
SETUP
stable before the arrival of the clock. To have a positive quantity the delay obtained by the
commands (maximum delay or last variation) must be less than the one obtained by the
clock (minimum delay).
So:
t4
= CLK (delay)
MIN
t5 can be expressed in a similar way, and can be defined as the t
t5
= CMD (delay)
MIN
- CMD (delay)
MIN
- CLK (delay)
MIN
=(T + t3
MAX
= (T + T/2 + t2
MAX
+t2
MIN
) - (T/2 + t2
MIN
) - (T + t3
MIN
) = T/2 - t2
MAX
of the commands:
HOLD
) = T/2 - t3
MAX
MAX
+ t3
MIN
MAX
Note:CLK(delay) is the combination of delays experienced by the CLK signal, CMD(delay) is the
combination of delays experienced by the command/ctrl/address signal (both until the
capture performed by the memory).
Table 35.DDR2 command timings without pad delay
Period (T)Frequencyt4
3 ns333 MHz977 ps1.33 ns
3.75 ns266 MHz1.35 ns1.71 ns
5 ns200 MHz1.98 ns2.33 ns
6 ns166 MHz2.49 ns2.84 ns
7.5 ns133 MHz3.23 ns3.59 ns
MIN
Ta bl e 3 5 shows the internal chip timing without the contribution of the pads.
t5
MIN
64/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
6.2 EXPI timing characteristics
The characterization timing is done for an output load of 10 pF on PL_CLKx and 5 pF on
PL_GPIO_x .The operating conditions are in worst case V=0.90 V TA =125 °C and in best
case V=1.10 V TA= 40 °C.
The timings are measured using TEST [5:0] = 101xxx: (Selg_cfg5 = EXPI with internal
clock). Please refer to the user manual for the description of the SoC_cfg bits in the MISC
registers.
Figure 10. AHB EXPI transfer waveforms
Table 36.EXPI - pad signal assignment
EXPI signalDirectionPL_GPIOs signal assignment
HAdd(19:00)Bidir.PL_GPIO(19:00)
HAdd(21:20)Bidir.PL_GPIO(56:55)
HAdd(23-:22)Bidir.PL_GPIO(82:81)
HRWData(07:00)Bidir.PL_GPIO(27:20)
HRWData(15:08)Bidir.PL_GPIO(64:57)
HRWData(31:16)Bidir.PL_GPIO(80:65)
HSize(2-0)Bidir.PL_GPIO(30:28)
HWriteBidir.PL_GPIO(31)
HBurst(2-0)Bidir.PL_GPIO(34:32)
HTrans(1-0)Bidir.PL_GPIO(36:35)
Doc ID 16259 Rev 3 65/97
Timing characteristicsSPEAr600
Q
Q
SET
CLR
D
tout
t
ck _p ad
CLK
PL_GPIO[ x]
t
in
Q
Q
SET
CLR
D
PL _C L K 1
t
ck_ff
Table 36.EXPI - pad signal assignment (continued)
EXPI signalDirectionPL_GPIOs signal assignment
HLockInp.PL_GPIO_37
HMastlockOut.PL_GPIO_38
HBreqInp.PL_GPIO_39
HGrantOut.PL_GPIO_40
HResp(1-0)Bidir.PL_GPIO(42:41)
HReady_mstOut.PL_GPIO_43
HReady_outInp.PL_GPIO_44
HReady_inOut.PL_GPIO_45
HSelOut.PL_GPIO_46
DMA_LREQ(1:0)/ HAdd(25:24)Inp.PL_GPIO(48:47)
DMA_REQ(1:0) / HAdd(27:26)Inp.PL_GPIO(50:49)
DMACCLR(1:0)/ HAdd(29:28)Out.PL_GPIO(52:51)
DMACTC(1:0) / HAdd(31:30)Out.PL_GPIO(54:53)
INT_IN_2Inp.PL_GPIO_83
CLKBidir.PL_CLK_1
ResetBidir.PL_CLK_2
INT_IN_1Inp.PL_CLK_3
INT_OUTOut.PL_CLK_4
Note:For more details please refer to the Expansion interface (EXPI) chapter of the user manual.
6.2.1 Pad delay disabled
Figure 11. Pad delay disabled block diagram
Note:The pad of the clock is disabled or enabled using the expi_clk_retim bit in the
EXPI_CLK_CFG register. Refer to the MISC registers chapter of the user manual).
66/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
In put
t
hold
PL_CLK1
PL _GP IO [ x]
Tclock
TrTf
Output
t
setup
t
max
t
min
Figure 12. EXPI signal timing waveforms
Table 37.EXPI clock and reset parameters
ParameterValue (ns)Frequency (MHz)
CLK period15 66.6
Tf CLK fall0.81
Tr C L K r i s e0 . 8 1
Output
Signals t
(ns)t
min
max
Reset0.84 6
Table 38.SOC-master
Output
Signals t
(ns)t
min
max
HADDR-1.115.93
HSIZE,HWRITE, HBURST,
HTRANS, HMASTLOCK, HSEL,
-0.924.71
HReady_in (45)
HWDATA-1.007.3
Input
t
(ns)t
SETUP
HOLD
HReady_out(44), HRESP7-2.09
HRDATA6.32-1.94
I
Table 39.SOC-slave
Input
(ns)
(ns)
(ns)
Signals t
(ns)t
SETUP
HOLD
(ns)
HADDR7.77-1.94
Doc ID 16259 Rev 3 67/97
Timing characteristicsSPEAr600
Q
Q
SET
CLR
D
t
out
t
ck_pad
CLK
PL_GPIO [ x]
t
in
Q
Q
SET
CLR
D
PL _ C L K 1
t
ck _ff
Table 39.SOC-slave (continued)
Input
HSIZE,HWRITE, HBURST,
HTRANS, HLOCK, HBUSREQ,
HWDATA6.17-1.94
HGRANT, HReady_mst(43),
HRESP
HRDATA-1.097.34
Input path:
t
SETUP
t
HOLD
Output Path:
t
max
t
min
Note:For t
while the minimum value is taken for t
= t
= (t
= (t
SETUP
= t
SETUP_FF
HOLD_FF
OUT
OUT
, t
+ t
+ t
HOLD
+ t
- t
CK_FF
CK_FF
and t
7.02-1.94
Output
(ns)t
t
min
max
(ns)
-0.664.21
+ t
IN(max)
IN(min)
)(max) - t
)(min) - t
are taken the maximum value from worst case and best case,
max
CK_PAD(max)
- t
CK_PAD(min)
CK_PAD
CK_PAD
(max)
min
+ t
(min)
.
- t
CK_FF
CK_FF
6.2.2 Pad delay enabled
Figure 13. EXPI pad delay enabled block diagram
Note:The pad of the clock is disabled or enabled using the expi_clk_retim bit in the
EXPI_CLK_CFG register. Refer to the MISC registers chapter of the user manual).
68/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
In put
t
hold
PL_CLK1
PL _GP IO [ x]
Tclock
TrTf
Output
t
setup
t
max
t
min
Figure 14. EXPI signal timing waveforms
Table 40.Clock and Reset
ParameterValueFrequency
CLK period15 66.6 MHz
Tf CLK fall0.81 ns
Tr CLK rise0.81 ns
Output
Signals Tmin (ns)Tmax(ns)
Reset0.84 6
Table 41.SOC-master
Output
Signals Tmin(ns)Tmax(ns)
HADDR2.6612.33
HSIZE,HWRITE, HBURST,
HTRANS, HMASTLOCK, HSEL,
2.8511.11
HReady_in (45)
HWDATA2.7713.7
Input
Tsetup(ns)Thold(ns)
HReady_out(44), HRESP0.61.68
HRDATA-0.081.83
Table 42.SOC-slave
Input
Signals Tsetup(ns)Thold(ns)
HADDR1.371.83
HSIZE,HWRITE, HBURST,
HTRANS, HLOCK, HBUSREQ,
0.621.83
HWDATA0.231.83
Doc ID 16259 Rev 3 69/97
Timing characteristicsSPEAr600
Table 42.SOC-slave (continued)
Input
Output
Tmin(ns)Tmax(ns)
HGRANT, HReady_mst(43),
HRESP
HRDATA2.6813.74
3.1110.61
70/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
Tmin
Tmax
CLCP
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
Tclock
TrTf
Tstable
Q
Q
SET
CLR
D
t2
t3
CLCP
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
CLCDCLK
t1
6.3CLCD timing characteristics
The characterization timing is done considering an output load of 10 pF on all the
outputs.The operating conditions are in worst case V=0.90 V T=125 °C and in best case
V=1.10 V T= 40 °C.
The CLCD has a wide variety of configurations and setting and the parameters change
accordingly. Two main scenarios will be considered, one with direct clock to output (166
MHz), setting BCD bit to '1', and the second one with the clock passing through a clock
divider (83 MHz), setting BCD bit to '0'. Please refer to the Table 477 for more information on
the significance of bit BCD).
6.3.1 CLCD timing characteristics direct clock
Figure 15. CLCD waveform with CLCP direct
Figure 16. CLCD block diagram with CLCP direct
Table 43.CLCD timings with CLCP direct
ParameterValueFrequency
Tclock direct max (Tclock)6 ns166 MHz
Tclock direct max rise (Tr)0.81 ns
Tclock direct max (Tf)0.87 ns
Tmin-0.04 ns
Tmax3.62 ns
Tstable2.34 ns
Doc ID 16259 Rev 3 71/97
Timing characteristicsSPEAr600
Tmin
Tmax
CLCP
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
Tclock
TrTf
Tstable
Q
Q
SET
CLR
D
t2
CLCP
CLD[23:0], CLAC, CLLE,
CLLP, CLFP, CLPOWER
CLCDCLK
t1
Q
Q
SET
CLR
Dt3
Note:1Tstable = Tclock direct max - (Tmax + Tmin)
2For Tmax the maximum value is taken from the worst case and best case, while for Tmin the
minimum value is taken from the worst case and best case.
3CLCP should be delayed by {Tmax + [Tclock direct max - (Tmax + Tmin)]/2} = 4.7915 ns
6.3.2 CLCD timing characteristics divided clock
Figure 17. CLCD waveform with CLCP divided
Figure 18. CLCD block diagram with CLCP divided
Table 44.CLCD timings with CLCP divided
ParameterValueFrequency
Tclock divided max12 ns83.3 MHz
Tclock divided max rise (Tr)0.81 ns
Tclock divided max (Tf)0.87 ns
Tmin-0.49 ns
Tmax2.38 ns
Tstable9.13 ns
72/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
HCLK
SCL
SDA
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
HCLK
SDA
SCL
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Note:1Tstable = Tclock direct max - (Tmax + Tmin)
2For Tmax the maximum value is taken from the worst case and for Tmin the minimum value
is taken from the best case.
3CLCP should be delayed by {Tmax + [Tclock direct max - (Tmax + Tmin)]/2} = 6.945 ns
6.4 I2C timing characteristics
The characterization timing is given for an output load of 10 pF on SCL and SDA.
The operating conditions are V=0.90 V, T=125 °C in worst case and V=1.10 V, T
best case.
Figure 19. I
Figure 20. I
2
C output pads
2
C input pads
= 40 °C in
A
The flip-flops used to capture the incoming signals are re-synchronized with the AHB clock:
so no input delay calculation is required.
Doc ID 16259 Rev 3 73/97
Timing characteristicsSPEAr600
SCL
T
SU - S TA
SDA
T
HD- STA
T
HD-DAT
T
SU - ST O
T
HD- STO
T
SC L H i g h
T
SCLLow
T
SU - D AT
Figure 21. Output signal waveforms for I2C signals
The timings of high and low level of SCL (TSCLHigh and TSCLLow) are programmable.
Table 45.Timing characteristics for I2C in high-speed mode
ParameterMin
TSU-STA163.31 ns
THD-STA487.73 ns
TSU-DAT313.38 ns
THD-DAT7.04 ns
TSU-STO642.98 ns
THD-STO4.74 µs
Table 46.Timing characteristics for I2C in fast-speed mode
ParameterMin
TSU-STA643.27 ns
THD-STA601.73 ns
TSU-DAT1.19 µs
THD-DAT7.04 ns
TSU-STO642.98 ns
THD-STO4.74 µs
Table 47.Timing characteristics for I2C in standard-speed mode
ParameterMin
TSU-STA4.73 µs
THD-STA3.99 µs
TSU-DAT4.67 µs
THD-DAT7.04 ns
TSU-STO4.03 µs
THD-STO4.74 µs
74/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
SDA fr om SP EAr pa dSDA t o De v i ce
R
C
Note:The timings shown in Figure 21 depend on the programmed values of TSCLHigh and
TSCLLow: so, the values present in Ta b le 4 5 to Tab le 4 7 have been calculated using the
minimum programmable values of:
IC_HS_SCL_HCNT=19 and IC_HS_SCL_LCNT=53 registers (for High-Speed mode)
IC_FS_SCL_HCNT=99 and IC_FS_SCL_LCNT=215 registers (for Fast-Speed mode)
IC_SS_SCL_HCNT=664 and IC_SS_SCL_LCNT=780 registers (for Standard-Speed
mode).
These minimum values depend on the AHB clock frequency, which is 166 MHz.
Note:A device may internally require a hold time of at least 300 ns for the SDA signal (referred to
the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL
(Please refer to the I2C Bus Specification v3-0 Jun 2007). However, the SDA data hold time
in the I2C controller of SPEAr600 is one-clock cycle based (7 ns with the HCLK clock at 166
MHz). This time may be insufficient for some slave devices. A few slave devices may not
receive the valid address due to the lack of SDA hold time and will not acknowledge even if
the address is valid. If the SDA data hold time is insufficient, an error may occur.
Workaround: If a device needs more SDA data hold time than one clock cycle, an RC delay
circuit is needed on the SDA line a
Figure 22. RC delay circuit
s illustrated in Figure 22
For example, R=K and C=200 pF.
Doc ID 16259 Rev 3 75/97
Timing characteristicsSPEAr600
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
HCLK
NFALE
NFCLE
NFIO_0..7
NFCE
NFWE
NFRE
NFRWPRT
...
...
...
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
HCLK
NFIO_0..7
NFRB
NFCLE
NFCE
NFWE
NFIO
Command
T
CLE
T
WE
T
IO
6.5 FSMC timing characteristics
The characterization timing is done using primetime considering an output load of 3 pF on
the data, 15 pF on NF_CE, NF_RE and NF_WE and 10 pF on NF_ALE and NF_CLE.
The operating conditions are V=0.90 V, T=125 °C in worst case and V=1.10 V, T= 40 °C in
best case.
6.5.1 8-bit NAND Flash configuration
Figure 23. Output pads for 8-bit NAND Flash configuration
Figure 24. Input pads for 8-bit NAND Flash configuration
Figure 25. Output command signal waveforms for 8-bit NAND Flash configuration
76/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
NFALE
NFCE
NFWE
NFIO
Address
T
ALE
T
WE
T
IO
NFCE
NFWE
NFIO (out)
Data Out
T
IO
NFIO (in)
NFRE
T
RE -> IO
T
WE
T
RE
T
READ
T
NFIO -> FFs
(3)
Figure 26. Output address signal waveforms for 8-bit NAND Flash configuration
Figure 27. In/out data address signal waveforms for 8-bit NAND Flash configuration
Table 48.Timing characteristics for 8-bit NAND Flash configuration
ParameterMinMax
TCLE-16.85 ns-19.38 ns
TALE-16.84 ns-19.37 ns
TWE (s=1)
TRE (s=1)
TIO (h=1)
1. TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE,
respectively. Both are composed by the algebric sum of a fixed part (due to the internal delays of Spear)
and a programmable one in a FSMC register. The programmable one is equal to (s+1)*Thclk where
s=Tset. The values shown in the table are calculated using s=1
2. TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on
the min or the max timing. It's composed by the algebric sum of a fixed part (due to the internal delays of
Spear) and a programmable one in a FSMC register. The programmable one is equal to h*Thclk where
h=Thiz. The values shown in the table are calculated using h=1.
3. TREAD is the timing between the falling edge and the rising edge of NFRE. This value is fully
programmable and it's equal to
where w=Twait; T(re->io) is the output delay of the NAND Flash and T(nfio->FFs) is the SPEAr600 internal
delay (~9 ns).
(1)
(1)
(2)
Doc ID 16259 Rev 3 77/97
11.10 ns13.04 ns
11.18 ns13.05 ns
3.43 ns8.86 ns
Timing characteristicsSPEAr600
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
HCLK
NFALE
NFCLE
NFIO_0..7
NFCE
NFWE
NFRE
NFRWPRT
...
...
...
CLPOWER
CLLP
CLLE
CLFP
CLCP
CLAC
CLD_23..22
(NFIO_8..15)
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
HCLK
NFIO_0..7
NFRB
...
...
CLPOWER
CLLP
CLLE
CLFP
CLCP
CLAC
CLD_23..22
(NFIO_8..15)
NFCLE
NFCE
NFWE
NFIO
Command
T
CLE
T
WE
T
IO
Note:Values in Ta b le 4 8 are referred to the common internal source clock which has a period of
THCLK = 6 ns.
6.5.2 16-bit NAND Flash configuration
Figure 28. Output pads for 16-bit NAND Flash configuration
Figure 29. Input pads for 16-bit NAND Flash configuration
Figure 30. Output command signal waveforms 16-bit NAND Flash configuration
78/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
NFALE
NFCE
NFWE
NFIO
Address
T
ALE
T
WE
T
IO
NFCE
NFWE
NFIO (out)
Data Out
T
IO
NFIO (in)
NFRE
T
RE -> IO
T
WE
T
RE
T
READ
T
NFIO -> FFs
(3)
Figure 31. Output address signal waveforms 16-bit NAND Flash configuration
Figure 32. In/out data signal waveforms for 16-bit NAND Flash configuration
Table 49.Timing characteristics for 16-bit NAND Flash configuration
ParameterMinMax
TCLE-16.85 ns-19.38 ns
TALE-16.84 ns-19.37 ns
TWE (s=1)
TRE (s=1)
TIO (h=1)
1. TWE e TRE are the timings between the falling edge of NFCE and the once related to NFWE and NFRE,
respectively. Both are composed by the algebric sum of a fixed part (due to the internal delays of Spear)
and a programmable one in a FSMC register. The programmable one is equal to (s+1)*Thclk where
s=Tset. The values shown in the table are calculated using s=1
2. TIO is the timing between the falling edge of NFCE and the first or the last change of NFIO depending on
the min or the max timing. It's composed by the algebric sum of a fixed part (due to the internal delays of
Spear) and a programmable one in a FSMC register. The programmable one is equal to h*Thclk where
h=Thiz. The values shown in the table are calculated using h=1.
3. TREAD is the timing between the falling edge and the rising edge of NFRE. This value is fully
programmable and it's equal to
where w=Twait; T(re->io) is the output delay of the NAND Flash and T(nfio->FFs) is the SPEAr600 internal
delay (~9 ns).
(1)
(1)
(2)
11.10 ns13.04 ns
11.18 ns13.05 ns
3.27 ns11.35 ns
Doc ID 16259 Rev 3 79/97
Timing characteristicsSPEAr600
Tmin
Tmax
GMIITX_CLK
TXD0-TXD3,
GMIITX_D4-GMIITX_D7,
TXEN, TXER
Tclock
TrTf
Q
Q
SET
CLR
D
t2
t3
GMII_TXCLK
TX[0..3], GMII_TX[4..7],
TXEN, TXER
CLK
TX[0..3], GMII_TX[4..7],
TXEN, TXER
Note:Values in Ta b le 4 9 are referred to the common internal source clock which has a period of
THCLK = 6 ns.
6.6 Ether MAC 10/100/1000 Mbps (GMAC-Univ) timing
characteristics
The characterization timing is given for an output load of 5 pF on the GMII TX clock and 10
pF on the other pads. The operating conditions are in worst case V=0.90 V, T=125 ° C and
in best case V=1.10 V, T= 40 ° C.
6.6.1 GMII Transmit timing specifications
Figure 33. GMII TX waveforms
Figure 34. Block diagram of GMII TX pins
Table 50.GMII TX timing
ParameterValue using GMII [t
t
(tr)<1 ns
rise
(tf)<1 ns
t
fall
t
= t2
max
min
- t3
- t3
min
max
max
t
min
t
SETUP
= t2
period = 8 ns 125 MHz]
CLK
2.8 ns
0.4 ns
5.19 ns
80/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
TXD0-TXD3
Tmin
Tmax
TX_CLK
Tclock
TrTf
Q
Q
SET
CLR
D
t2
t3
TX_CLK
TXD[0..3]
TX[0..3]
Note:To calculate the t
you have to apply the following formula: t
value for the PHY you have to consider the next t
SETUP
SETUP
6.6.2 MII transmit timing specifications
Figure 35. MII TX waveforms
Figure 36. Block diagram of MII TX pins
= t
CLK
- t
max
rising edge, so
CLK
Table 51.MII TX timings
Parameter
t
= t2
max
min
- t3
- t3
min
max
max
t
min
t
SETUP
= t2
Note:To calculate the t
you have to apply the following formula: t
Value using MII 100 Mb [t
period = 40 ns 25 MHz]
6.8 ns6.8 ns
2.9 ns2.9 ns
33.2 ns393.2 ns
value for the PHY you have to consider the next t
SETUP
Doc ID 16259 Rev 3 81/97
SETUP
= t
CLK
- t
CLK
max
Value using MII 10 Mb [t
period = 400 ns 2.5 MHz]
rising edge, so
CLK
CLK
Timing characteristicsSPEAr600
RXD0-RXD3,
GMIIRX_D4-GMIIRX_D7,
RX_ER, RX_DV
RX_CLK
Ts
Th
Tclock
TrTf
t1
Q
Q
SET
CLR
D
t2
RX[0..3], GMII_RX[4..7],
RX_ER, RX_DV
RX_CLK
6.6.3GMII-MII Receive timing specifications
Figure 37. GMII-MII RX waveforms
Figure 38. Block diagram of GMII-MII RX pins
Table 52.GMII-MII RX timings
t
SETUPmax
t1
min
t
HOLDmin
t1
max
Note:The input stage is the same for all the interfaces (GMII and MII10/100) so t
values are equal in all the cases.
The receive path is optimized for the GMII interface: this also ensures correct capture of
data for the MII10/100 interface.
82/97Doc ID 16259 Rev 3
Parameter
(tS)= t2
(tH)= t2
min
Value using GMII [t
-
max
-
Value using MII 100Mb
CLK
period = 8 ns
125 MHz]
2.26 ns2.26 ns2.26 ns
-0.11 ns-0.11 ns-0.11 ns
[t
period = 40 ns
CLK
25 MHz]
Value using MII 10
Mb [t
CLK
ns 2.5 MHz]
SETUP
period = 400
and t
HOLD
SPEAr600Timing characteristics
Input
Thold
MDC
MDIO
Tcloc k
TrTf
Ou tp ut
Tsetup
Tmin
Tmax
Q
Q
SET
CLR
D
t2
t3
CLK
MDIO
t1
Q
Q
SET
CLR
D
MDC
INPUT
OUTPUT
6.6.4 MDIO timing specifications
Figure 39. MDC waveforms
Figure 40. Paths from MDC/MDIO pads
Table 53.MDC/MDIO timing
ParameterValueFrequency
period614.4 ns1.63 MHz
t
CLK
t
fall (tf)1.18 ns
CLK
rise (tr)1.14 ns
t
CLK
Output
t
t
max
min
= ~t
= ~t
/2307 ns
CLK
/2307 ns
CLK
Input
t
SETUPmax
t
HOLDmin
= t1
= t1
min
max
- t3
- t3
max
min
6.88 ns
-1.54 ns
Note:When MDIO is used as output the data are launched on the falling edge of the clock as
shown in Figure 39.
Doc ID 16259 Rev 3 83/97
Timing characteristicsSPEAr600
Thold
SMI _ CLK
SMI _D ATAIN
Tclock
TrTf
Ts etup
Tmin
Tmax
SM I_DATAOU T
Tfmin
Tfmax
SM I_CS_0
SM I_CS_1
SM I_CS_3
Trmin
Trmax
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
SMI_CLK
SMI _CL K
SMI_DATAIN
SMI_DATAOUT
SMI_CS_n
(n= 0,1,3)
SMI_DATAOUT
SM I_CS_n
(n= 0,1,3)
HCLK
6.7 SMI timing characteristics
The characterization timing is given for an output load of 5 pF on the clock and 10 pF on the
other pads. The operating conditions are in worst case V=0.90 V, T
case V=1.10 V, T
= 40° C.
A
6.7.1 SMI timing specifications
Figure 41. SMI waveforms
=125° C and in best
A
Figure 42. Block diagram of the SMI pins
Table 54.SMI timings in default configuration
SignalParameterValueDescription
t
CLK
t
SMI_CLK
CLK
t
r
t
f
t
SETUP
SMI_DATAIN
t
HOLD
84/97Doc ID 16259 Rev 3
50 nsSMI period (normal mode).
20 nsSMI period (fast read mode).
0.8 ns
0.84 ns
4.5 nsMax setup time and min hold time of
-0.08 ns
Transition times.
data in, referred to SMI_CLK rising
edge.
SPEAr600Timing characteristics
Table 54.SMI timings in default configuration (continued)
SignalParameterValueDescription
SMI_DATAOUT
t
max
t
min
t
rmax
0.65 ns
-0.41 ns
Max and min delay time of data out,
referred to SMI_CLK falling edge.
0.59 nsMax and min delay time of chip select
0 rising edge, referred to SMI_CLK
t
rmin
-0.52 ns
falling edge.
SMI_CS_0
t
fmax
0.46 nsMax and min delay time of chip select
0 falling edge, referred to SMI_CLK
t
fmin
t
rmax
-052 ns
falling edge.
0.67 nsMax and min delay time of chip select
0 rising edge, referred to SMI_CLK
t
rmin
-0.27 ns
falling edge.
SMI_CS_1
t
fmax
0.54 nsMax and min delay time of chip select
1 falling edge, referred to SMI_CLK
t
fmin
Table 55.SMI Timings of SMI_CS_3 in non-default configurations
-0.3 ns
falling edge.
SignalParameterValueDescription
t
rmax
2.64 nsMax and min delay time of chip select
3 rising edge, referred to SMI_CLK
NF_WP (SMI_CS_3 in
Disable_nand_flash)
t
rmin
t
fmax
1.32 ns
falling edge.
2.47 nsMax and min delay time of chip select
3 falling edge, referred to SMI_CLK
t
fmin
t
rmax
-0.31 ns
falling edge.
0.71nsMax and min delay time of chip select
3 rising edge, referred to SMI_CLK
CLD_14 (SMI_CS_3 in
Disable_LCD_ctr)
t
rmin
t
fmax
-0.08 ns
falling edge.
0.52 nsMax and min delay time of chip select
3 falling edge, referred to SMI_CLK
t
fmin
t
rmax
0.36 ns
falling edge.
3.99 nsMax and min delay time of chip select
3 rising edge, referred to SMI_CLK
0.6 ns
3.91 ns
1.56 ns
1.32 ns
falling edge.
Max and min delay time of chip select
3 falling edge, referred to SMI_CLK
falling edge.
2.47 nsMax and min delay time of chip select
RX_ER (SMI_CS_3 in
Disable_GMAC_ctr)
t
rmin
t
fmax
t
fmin
t
rmin
t
fmax
3 falling edge, referred to SMI_CLK
t
fmin
1.56 ns
falling edge.
Doc ID 16259 Rev 3 85/97
Timing characteristicsSPEAr600
6.8 SSP timing characteristics
The device SPEAr600 contains 3 SSP modules. The Low Speed Connectivity Subsystem
contains SSP1 and SSP2, the Application Subsystem contains SSP3. These 3 identical
modules provide a programmable length shift register which allows serial communication
with other SSP devices through a 3 or 4 wire interface (SSP_SCLK, SSP_MISO,
SSP_MOSI and SSP_SS). The SSP module supports the following features:
●Master/Slave mode operations
●Programmable clock bit rate and prescaler
●Programmable choice of interface operation: SPI, Microwire or TI synchronous serial
Programmable data frame size from 5 to 16 bits
●Separate transmit and receive FIFO, 16 bits wide, 8 locations deep
The features of the Motorola SPI-compatible interface are:
●Full duplex, four-wire synchronous transfers (SSP_SCLK, SSP_MISO, SSP_MOSI and
SSP_SS)
●Programmable Clock Polarity (CPOL) and Clock Phase (CPHA)
The following Tables show the Timing Requirements of the SPI four-wire synchronous
transfer for the 3 SSP modules present in the Spear600 configured in master mode
(indicated in the tables as SPI1, SPI2 and SPI3). Both the Timings on MISO (master input
slave output) pad and MOSI (master output slave input) pad are provided.
T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a
configurable divider.
Figure 43. SSP_CLK timing
86/97Doc ID 16259 Rev 3
SPEAr600Timing characteristics
The Motorola SPI interface is a four-wire interface where SSP_SS signal behaves as a slave
select.
The main feature of the Motorola SPI format is that the inactive state and phase of the
output clock signal are programmable through the CPOL (clock polarity) and CPHA (clock
phase) parameters inside an IP control register.
●CPOL, clock polarity:
When CPOL clock polarity control parameter is low, it produces a steady state low
value on the output clock pin. If this parameter is high, a steady state high value is
placed on the output clock pin when data is not being transferred.
●CPHA, clock phase:
The CPHA clock phase control parameter selects the clock edge that captures data
and allows it to change state. When CPHA is low, data is captured on the first clock
edge transition after slave selection and is changed on the second clock edge
transition. If the CPHA clock phase control parameter is high, data is captured on the
second clock edge transition after the slave selection and is changed on the first clock
edge transition.
6.8.1 SPI master mode timings (CPHA = 0)
Table 57.Timing requirements for SPI mode on MISO pad [CPHA = 0]
NoparametersCPOLSPI1SPI2SPI3unit
Setup time, MISO (input)
13
14
15
16
Table 58.Timing requirements for SPI mode on MOSI pad [CPHA = 0]
NoparametersCPOLSPI1SPI2SPI3unit
17
18
valid before SSP_SCLK
(output) rising edge
Setup time, MISO (input)
valid before SSP_SCLK
(output) falling edge
Hold time, MISO (input)
valid after SSP_SCLK
(output) rising edge
Hold time, MISO (input)
valid after SSP_SCLK
(output) falling edge
Delay time, SSP_SCLK
(output) falling edge to
MOSI (output) transition
Delay time, SSP_SCLK
(output) rising edge to
MOSI (output) transition
09.56310.75910.357ns
19.63210.80410.427ns
0-8.849-10.112-9.753ns
1-8.956-10.149-9.785ns
0-0.675-1.141-1.638ns
1-0.607-1.097-1.568ns
Doc ID 16259 Rev 3 87/97
Timing characteristicsSPEAr600
Table 58.Timing requirements for SPI mode on MOSI pad [CPHA = 0] (continued)
NoparametersCPOLSPI1SPI2SPI3unit
Delay time, SSP_SS
19
(output) falling edge to first
SSP_SCLK (output) rising
Tns
or falling edge
Delay time, SSP_SCLK
20
(output) rising or falling
edge to SSP_SS (output)
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
SPEAr600 is ROHS-6 compliant.
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
90/97Doc ID 16259 Rev 3
SPEAr600Package information
7.1 Package mechanical data
Table 61.PBGA420 (23 x 23 x 2.06 mm) mechanical data
mminches
Dim.
Min.Typ.Max.Min.Typ.Max.
A2.060.0811
A10.240.0094
A20.560.0220
A30.970.0382
A41.530.0602
b0.400.500.600.01570.01970.0236
D22.8023.0023.200.89760.90550.9134
D121.000.8268
D220.000.7874
E22.8023.0023.200.89760.90550.9134
E121.000.8268
E220.000.7874
e1.000.0394
F1.000.0394
ddd0.200.0079
eee0.250.0098
fff0.100.0039
Doc ID 16259 Rev 3 91/97
Package informationSPEAr600
Figure 46. PBGA420 (23 x 23 x 2.06 mm) package top view
92/97Doc ID 16259 Rev 3
SPEAr600Package information
Figure 47. PBGA420 (23 x 23 x 2.06 mm) package bottom view
Added I2S to Table 18: Memory map.
Modified pin list of I2S and EXPI Table 14: EXPI/I2S pins and
Table 15: EXPI pins.
Updated sections Features, Main features and I2S audio block
improving the description of I2S feature.
Updated Tab l e 19 : A b solute maximum ratings
Updated section DDR2 timing characteristics.
Updated Table 27: Driver characteristics.
Updated Section 5.1: Absolute maximum ratings
Updated Table 21: Recommended operating conditions.
Updated Section 2.15: UARTs
Updated introduction of Chapter 7: Package information
Updated Table 10: NAND Flash I/F pins.
Updated Tab l e 3: Pow e r supply pins.
Updated Table 6: USB pins.
8-Feb-20102
Updated Figure 1: Functional block diagram and Figure 2: Typical
system architecture using SPEAr600
Changed “SPI” with “SSP” where necessary.
Inserted the new Section 6.8: SSP timing characteristics
Corrected the frequency of DDR1.
Separated the Electrical characteristics and Timing characteristics in
two chapters
Changed the title of the Section 5.5: 3.3V I/O characteristic
Added Table 62: SPEAr600 PBGA420 thermal resistance
Added a line of explanation in the introduction of Section 3: Pin
description.
Added new Section 3.3: Configuration modes.
Added new Section 2.25: External Port Controller (EXPI I/F).
s
Doc ID 16259 Rev 3 95/97
Revision historySPEAr600
Table 63.Document revision history (continued)
DateRevisionChanges
Modified FSMC feature on page 1
Figure 2: Typical system architecture using SPEAr600:
– Deleted SRAM and ROM blocks which were connected to the
FSMC block
– Substituted SSP with 3xSSP
– Added the RAS block.
Section 1.1: Main features on page 9:
– Deleted the word “/parallel” from bullet seven (about FSMC)
– Replaced SPI with SSP in bullet sixteen.
– Modified number of GPIOs to 10
– Added information about RAS (Reconfigurable Array Subsystem)
Chapter 2: Architecture overview: reviewed the first introduction part.
Section 2.4: Flexible static memory controller:
– Updated the introduction.
– Main features: changed the sentence “Provides independent chip
select for each memory bank" by "Provides only one chip select for
the first memory bank"
Tab l e 3 : P o w e r supply pins: swapped ball R1 from the “Digital ground
group” to the “Analog ground group”.
09-May-20123
Section 2.15: UARTs: corrected the value of the baud rate to 3 Mbps
Table 48: Timing characteristics for 8-bit NAND Flash configuration
and Table 49: Timing characteristics for 16-bit NAND Flash
configuration: added three footnotes.
Tab l e 3 : P o w e r supply pins: swapped ball R1 from the “Digital ground
group” to the “Analog ground group”.
Section 2.15: UARTs: corrected the value of the baud rate in 3 Mbps
Table 48: Timing characteristics for 8-bit NAND Flash configuration
and Table 49: Timing characteristics for 16-bit NAND Flash
configuration: added three footnotes.
Created the new Section 2.24: Reconfigurable array subsystem
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