ST SPEAr310 User Manual

SPEAr310

Embedded MPU with ARM926 core, flexible memory support, extended set of powerful connectivity features

Features

■ARM926EJ-S 333 MHz core

■High-performance 8-channel DMA

■Dynamic power-saving features

■Configurable peripheral functions multiplexed on 102 shared I/Os

■Memory:

–32 KB ROM and 8 KB internal SRAM

–LPDDR-333/DDR2-666 external memory interface

–Serial Flash Memory interface (SMI)

–Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting NAND Flash

–External memory interface (EMI) up to 32bit data bus width, supporting NOR Flash and FPGAs

■Connectivity

–2 x USB 2.0 Host

–USB 2.0 Device

–1 x fast Ethernet MII port

–4 x fast Ethernet SMII ports

–1 x SSP Synchronous serial peripheral (SPI, Microwire or TI protocol) with 4 chip selects

–1 x I2C

–1 x fast IrDA interface

–6 x UART interface

–1x TDM/E1 HDLC interface with 128/32 timeslots per frame respectively

–2x RS485 HDLC ports

■Security

–C3 Cryptographic accelerator

■Miscellaneous functions

–Integrated real time clock, watchdog, and system controller

–8-channel 10-bit ADC, 1 Msps

LFBGA289 (15 x 15 x 1.7 mm)

–JPEG CODEC accelerator

–Six 16-bit general purpose timers with programmable prescaler, 4 capture inputs

–Up to 102 GPIOs with interrupt capability

Applications

The SPEAr310 embedded MPU is configurable for a range of telecom and networking applications such as:

■Routers, switches and gateways

■Remote apparatus control

■Metering concentrators

Table 1.	Device summary
Order code		Temp	Package	Packing
		range, ° C
			LFBGA289
SPEAR310-2		-40 to 85	(15x15 mm,	Tray
			pitch 0.8 mm)

March 2010

Doc ID 16482 Rev 2

1/72

www.st.com

Contents	SPEAr310

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
2	Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
	2.1	CPU ARM 926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	2.2	System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12

2.2.1 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.3 Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.4 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.5 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.6 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3	Multichannel DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
2.4	Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
2.5	Mobile DDR/DDR2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
2.6	Serial memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
2.7	External memory interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
2.8	Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . .		16
2.9	UARTs	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	2.9.1	UART with hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	2.9.2	UARTs with software flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17

2.10 Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.11 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 TDM/E1 HDLC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

	2.12.1	TDM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	2.12.2	E1 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
2.13	RS485 HDLC ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	2.13.1	HDLC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
2.14	GPIOs	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
2.15	8-channel ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
2.16	SMII Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
2.17	MII Ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22
2.18	USB2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		23

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2.19 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20 Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.21 JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	3.1	Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	3.2	Dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	3.3	Shared I/O pins (PL_GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32

3.3.1 PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.2 Configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.4 Boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.5 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.6 Multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4 PL_GPIO pin sharing for debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4	Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		40
5	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
	5.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	5.2	Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
	5.3	DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
	5.4	Overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44
	5.5	3.3V I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
	5.6	LPDDR and DDR2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .	45
	5.7	Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	46
	5.8	Removing power supplies for power saving . . . . . . . . . . . . . . . . . . . . . . .	46
	5.9	Power on reset (MRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	47
6	Timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		48
	6.1	DDR2 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	48

6.1.1 DDR2 read cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.2 DDR2 write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1.3 DDR2 command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.2 I2C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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6.3 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.3.1 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.2 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.4 Ether MAC 10/100 Mbps timing characteristics . . . . . . . . . . . . . . . . . . . . 57

6.4.1 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4.2 MII receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.4.3 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.5 SMI - Serial memory interface timing characteristics . . . . . . . . . . . . . . . . 61 6.6 SSP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.6.1 SPI master mode timings (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . 65 6.6.2 SPI master mode timings (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . 66

6.7UART (Universal asynchronous receiver/transmitter) timing characteristics

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	69
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	71

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SPEAr310	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Master clock, RTC, Reset and 3.3 V comparator pin descriptions . . . . . . . . . . . . . . . . . . . 26 Table 3. Power supply pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4. Debug pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. Serial memory interface (SMI) pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6. USB pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 7. ADC pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 8. DDR pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9. PL_GPIO pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 10. PL_GPIO multiplexing scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11. Table shading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 12. Ball sharing during debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 13. SPEAr310 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 14. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 15. Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 16. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 17. Overshoot and undershoot specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 18. Low voltage TTL DC input specification (3 V< VDD <3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 19. Low voltage TTL DC output specification (3 V< VDD <3.6 V) . . . . . . . . . . . . . . . . . . . . . . . 45

Table 20. Pull-up and pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 21. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 22. Driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 23. On die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 24. Reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 25. DDR2 Read cycle timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 26. DDR2 Write cycle timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 27. DDR2 Command timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 28. Output delays for I2C signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 29. Time characteristics for I2C in high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 30. Time characteristics for I2C in fast speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 31. Time characteristics for I2C in standard speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 32. Time characteristics for 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 33. Time characteristics for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 34. MII TX timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 35. MDC/MDIO timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 36. SMI_DATAIN timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 37. SMI_DATAOUT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 38. SMI_CSn fall timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 39. SMI_CSn rise timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 40. Timing requirements for SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 41. Timing requirements for SSP (all modes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 42. Timing requirements for SPI master mode (clock phase = 0). . . . . . . . . . . . . . . . . . . . . . . 65 Table 43. Switching characteristics over recommended operating conditions for SPI master mode

(clock phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 44. Timing requirements for SPI master mode (clock phase = 1). . . . . . . . . . . . . . . . . . . . . . . 66 Table 45. Switching characteristics over recommended operating conditions for SPI master mode

(clock phase = 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 46. UART transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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Table 47. UART receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 48. LFBGA289 (15 x 15 x 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 49. Thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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SPEAr310	List of figures

List of figures

Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Typical system architecture using SPEAr310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. Clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. Typical SMII system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5. Hierarchical multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 6. Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 7. Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 8. DDR2 Read cycle waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 9. DDR2 Read cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 10. DDR2 Write cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 11. DDR2 Write cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 12. DDR2 Command waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 13. DDR2 Command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 14. I2C output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 15. I2C input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 16. Output signal waveforms for I2C signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 17. RC delay circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 18. Output pads for 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 19. Input pads for 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 20. Output command signal waveforms for 8-bit NAND Flash configuration . . . . . . . . . . . . . . 54 Figure 21. Output address signal waveforms for 8-bit NAND Flash configuration. . . . . . . . . . . . . . . . 55 Figure 22. In/out data address signal waveforms for 8-bit NAND Flash configuration. . . . . . . . . . . . . 55 Figure 23. Output pads for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 24. Input pads for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 25. Output command signal waveforms 16-bit NAND Flash configuration. . . . . . . . . . . . . . . . 56 Figure 26. Output address signal waveforms 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . 57 Figure 27. In/out data signal waveforms for 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . 57 Figure 28. MII TX waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 29. Block diagram of MII TX pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 30. MII RX waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 31. Block diagram of MII RX pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 32. MDC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 33. Paths from MDC/MDIO pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 34. SMI_DATAIN data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 35. SMI_DATAOUT/SMI_CSn data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 36. SMI_DATAOUT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 37. SMICSn fall timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 38. SMI_CSn rise timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 39. SSP_CLK timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 40. SPI master mode external timing (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 41. SPI master mode external timing (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 42. UART transmit and receive timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 43. LFBGA289 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

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Description	SPEAr310

1 Description

The SPEAr310 is a member of the SPEAr family of embedded MPUs, optimized for telecom applications. It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required.

In addition, SPEAr310 has an MMU that allows virtual memory management -- making the system compliant with advanced operating systems, like Linux. It also offers 16 KB of data cache, 16 KB of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations.

A full set of peripherals allows the system to be used in many applications, some typical applications being routers, switches and gateways as well as remote apparatus control and metering concentrators.

Figure 1. Functional block diagram

EMI NOR Flash/
FPGA interface			Up to 102 GPIOs		1x Ethernet 10/100
					(MII interface)
FSMC NAND					4x Ethernet 10/100
Flash interface						2 x RS485 HDLC
					(SMII interface)
		MultiChannel DMA
Mobile DDR/DDR2				controller
memory controller					6x UART	TDM/E1 HDLC
Serial Flash memory				C3 Crypto
interface (SMI)					IrDA
				accelerator		USB Device 2.0 + Phy
32 Kbytes BootRom
					6x General purpose
			JPEG CODEC		timer		Phy
8 Kbytes SRAM						USB
				accelerator	ADC		Hub
						Host
						2.0	Phy
Interrupt		System		MMU	ARM926EJ-S		1 x SSP
controller		controller
					@333 MHz
				ICache
Watchdog	RTC	PLLs				I2C master/slave

DCache JTAG/trace

Functions with shared I/Os depending on the device configuration.

Refer to the pin description.

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SPEAr310	Description

●ARM926EJ-S 32-bit RISC CPU, up to 333 MHz

–16 Kbytes of instruction cache, 16 Kbytes of data cache

–3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, Java mode (Jazelle™) for direct execution of Java bytecode.

–AMBA bus interface

●32-KByte on-chip BootROM

●8-KByte on-chip SRAM

●External DRAM memory interface:

–8/16-bit (mobile DDR@166 MHz)

–8/16-bit (DDR2@333 MHz)

●Serial memory interface

●8/16-bits NAND Flash controller (FSMC)

●External memory interface (EMI) for connecting NOR Flash or FPGAs

●Boot capability from NAND Flash, serial/parallel NOR Flash

●Boot and field upgrade capability from USB

●High performance 8-channel DMA controller

●TDM/E1 HDLC, six-signal interface supporting duplex Tx/Rx communication

–For TDM applications, up to 8 Mbps per Tx/Rx channel 128 timeslots per frame (125 µs)

–For E1 applications, up to 2 Mbps per Tx/Rx channel 32 timeslots per frame (125 µs)

–Compliant with ISO/IEC13239

–Standard HDLC frame code/decode

●2x RS485 HDLC ports:

–Five interface signals

–Supports duplex Tx/Rx communication

–Maximum Tx/Rx data rate 3.88 Mbps

●4x Ethernet MAC 10/100 Mbps with SMII PHY interface

●1x Ethernet MAC 10/100 Mbps with MII PHY interface

●Two USB2.0 host (high-full-low speed) with integrated PHY transceiver

●One USB2.0 device (high-full-low speed) with integrated PHY transceiver

●Up to 102 GPIOs with interrupt capability

●Synchronous serial port (SSP), master/slave (supporting SPI, Microwire and TI sync protocols) up to 41.5 Mbps

●I2C master/slave interface (slow-fast-high speed, up to 1.2 Mb/s)

●1x UART with hardware flow control (up to 3 Mbps)

●5x UARTs with software flow control (up to 5 Mbps)

●ADC 10-bit, 1 Msps 8 inputs

●JPEG CODEC accelerator 1 clock/pixel

●C3 Crypto accelerator (DES/3DES/AES/SHA1)

●Advanced power saving features

–Normal, Slow, Doze and Sleep modes

–CPU clock with software-programmable frequency

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Description	SPEAr310

–Enhanced dynamic power-domain management

–Clock gating functionality

–Low frequency operating mode

–Automatic power saving controlled from application activity demands

●Vectored interrupt controller

●System and peripheral controller

–3 pairs of 16-bits general purpose timers with programmable prescaler

–RTC with separate power supply allowing battery connection

–Watchdog timer

–Miscellaneous registers array for embedded MPU configuration

●Programmable PLL for CPU and system clocks

●JTAG IEEE 1149.1

●Boundary scan

●ETM functionality multiplexed on primary pins

●Supply voltages

–1.2 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs, 1.5 V RTC and 3.3 V I/Os

●Operating temperature: - 40 to 85 °C

●LFBGA289 (15 x 15 mm, pitch 0.8 mm)

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SPEAr310	Architecture overview

2 Architecture overview

The SPEAr310 internal architecture is based on several shared subsystem logic blocks interconnected through a multilayer interconnection matrix.

The switch matrix structure allows different subsystem dataflow to be executed in parallel improving the core platform efficiency.

High performance master agents are directly interconnected with the memory controller reducing the memory access latency. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted roundrobin arbitration mechanism.

Figure 2. Typical system architecture using SPEAr310

	SP
2.1	CPU ARM 926EJ-S

The core of the SPEAr310 is an ARM926EJ-S reduced instruction set computer (RISC) processor.

It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes.

The ARM CPU is clocked at a frequency up to 333 MHz. It has a 16-Kbyte instruction cache, a 16-Kbyte data cache, and features a memory management unit (MMU) which makes it fully compliant with Linux and WindowsCE operating systems.

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Architecture overview	SPEAr310

It also includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock.

2.2System controller

The System Controller provides an interface for controlling the operation of the overall system.

Main features:

●Power saving system mode control

●Crystal oscillator and PLL control

●Configuration of system response to interrupts

●Reset status capture and soft reset generation

●Watchdog and timer module clock enable

2.2.1Clock and reset system

The clock system is a fully programmable block that generates all the clocks necessary to the chip (see Figure 3).

The default operating clock frequencies are:

●CPU_CLK @ 333 MHz for the CPU.

●HCLK @ 166 MHz for AHB bus and AHB peripherals.

●PCLK @ 83 MHz for, APB bus and APB peripherals.

●DDR_CLK @ 100-333 MHz for DDR memory interface.

The default values give the maximum allowed clock frequencies. The clock frequencies are fully programmable through dedicated registers.

The clock system consists of 2 main parts: a multi clock generator block and three internal PLLs.

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Figure 3. Clock generator overview

		333 MHz	CPU_CLK
	PLL1	166 MHz	HCLK
		DIV 2
		83 MHz	PCLK
	24 MHz	DIV 4
	OSC	166 MHz	DDR_CLK
	PLL2
		CLK12MHZ
	PLL3	CLK30MHZ
		CLK48MHZ
	32.768 kHz
	RTC	CLK32MHZ

The multi clock generator block, takes a reference signal (which is usually delivered by the PLL), generates all clocks for the IPs of SPEAr310 according to dedicated programmable registers.

Each PLL uses an oscillator input of 24 MHz to generate a clock signal at a frequency corresponding at the highest of the group. This is the reference signal used by the multi clock generator block to obtain all the other requested clocks for the group. Its main feature is electromagnetic interference reduction capability.

The user can set up the PLL in order to modulate the VCO with a triangular wave. The resulting signal has a spectrum (and power) spread over a small programmable range of frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic emissions. This method replaces all the other traditional methods of EMI reduction, such as filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal shielding and so on. This gives the customer appreciable cost savings.

In sleep mode the SPEAr310 runs with the PLL disabled so the available frequency is 24 MHz or a sub-multiple (/2, /4, /8).

2.2.2Power saving system mode control

Using three mode control bits, the system controller switch the SPEAr310 to any one of four different modes: DOZE, SLEEP, SLOW and NORMAL.

●SLEEP mode: In this mode the system clocks, HCLK and CPU_CLK, are disabled and the System Controller clock is driven by a low speed oscillator (nominally 32768 Hz). When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters

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Architecture overview	SPEAr310

DOZE mode. Additionally, the operating mode setting in the system control register automatically changes from SLEEP to DOZE.

●DOZE mode: In this mode the system clocks, HCLK and CPU_CLK, and the System Controller clock are driven by a low speed oscillator. The System Controller moves into SLEEP mode from DOZE mode only when none of the mode control bits are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL mode is required the system moves into the XTAL control transition state to initialize the crystal oscillator.

●SLOW mode: During this mode, both the system clocks and the System Controller clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode control bits are set, the system goes into the "Switch from XTAL" transition state.

●NORMAL mode: In NORMAL mode, both the system clocks and the System Controller clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the system goes into the "Switch from PLL" transition state.

2.2.3Vectored interrupt controller (VIC)

The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in response to peripheral interrupts. There are 32 interrupt lines and the VIC uses a separate bit position for each interrupt source. Software controls each request line to generate software interrupts.

2.2.4General purpose timers

SPEAr310 provides three general purpose timers (GPTs) acting as APB slaves. The timers can capture input signals from up to 4 external pins (enabled as PL_GPIO alternate functions).

Each GPT consists of 2 channels, each one made up of a programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock division by 1 up to 256, and different input frequencies can be chosen through configuration registers (a frequency range from 3.96 Hz to 48 MHz can be synthesized).

Two different modes of operation are available :

●Auto-reload mode, an interrupt source is activated, the counter is automatically cleared and then it restarts incrementing.

●Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT is disabled.

2.2.5Watchdog timer

The ARM watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generate an interrupt and a reset signal on timing out. The watchdog module is intended to be used to apply a reset to a system in the event of a software failure.

2.2.6RTC oscillator

The RTC provides a 1-second resolution clock. This keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. It has a

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clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update.

Main features:

●Time-of-day clock in 24 hour mode

●Calendar

●Alarm capability

●Isolation mode, allowing RTC to work even if power is not supplied to the rest of the device.

2.3Multichannel DMA controller

Within its basic subsystem, SPEAr310 provides an DMA controller (DMAC) able to service up to 8 independent DMA channels for sequential data transfers between single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral tomemory, and peripheral-to-peripheral).

Each DMA channel can support a unidirectional transfer, with internal four-word FIFO per channel.

2.4Embedded memory units

●32 Kbytes of BootROM

●8 Kbytes of SRAM

2.5Mobile DDR/DDR2 memory controller

SPEAr310 integrates a high performance multi-channel memory controller able to support low power Mobile DDR and DDR2 double data rate memory devices. The multi-port architecture ensures memory is shared efficiently among different high-bandwidth client modules.

It has 6 internal ports. One of them is reserved for register access during the controller initialization while the other five are used to access the external memory.

It also includes the physical layer (PHY) and DLLs for fine tuning the timing parameters to maximize the data valid windows at different frequencies.

2.6Serial memory interface

SPEAr310 provides a serial memory interface (SMI) to SPI-compatible off-chip memories.

These serial memories can be used either as data storage or for code execution.

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Architecture overview	SPEAr310

Main features:

●Supports the following SPI-compatible Flash and EEPROM devices:

–STMicroelectronics M25Pxxx, M45Pxxx

–STMicroelectronics M95xxx, except M95040, M95020 and M95010

–ATMEL AT25Fxx

–YMC Y25Fxx

–SST SST25LFxx

●Acts always as a SPI master and up to 2 SPI slave memory devices are supported (with seperate chip select signals), with up to 16 MB address space each

●SMI clock signal (SMICLK) is generated by SMI (and input to all slaves)

●SMICLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can be controlled by a programmable 7-bit prescaler allowing up to 127 different clock frequencies.

2.7External memory interface (EMI)

The EMI Controller provides a simple external memory interface that can be used for example to connect to NOR Flash memory or FPGA devices.

Main features:

●Multiplexed address and data bus.

●EMI bus master

●32, 16, 8-bit transfers.

●Can access 6 different peripherals using CS#, one at a time.

●Supports single asynchronous transfers.

●Supports peripherals which use Byte Lane procedure

2.8Flexible static memory controller (FSMC)

SPEAr310 provides a Flexible Static Memory Controller (FSMC) which interfaces the AHB bus to external parallel NAND Flash memories.

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Main features:

●8/16-bit wide data path

●FSMC performs only one access at a time and only one external device is accessed.

●Supports little-endian and big-endian memory architectures.

●AHB burst transfer handling to reduce access time to external devices.

●Supplies an independent configuration for each memory bank.

●Programmable timings to support a wide range of devices.

–Programmable wait states (up to 31).

–Programmable bus turnaround cycles (up to 15).

–Programmable output enable and write enable delays (up to 15).

●Independent chip select control for each memory bank.

●Shares the address bus and the data bus with all the external peripherals.

●Only chips selects are unique for each peripheral.

●External asynchronous wait control.

2.9UARTs

The SPEAr310 has 5 UARTs featuring software flow control and 1 UART featuring hardware and/or software flow control.

2.9.1UART with hardware flow control

Main features:

●Separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive FIFOs to reduce CPU interrupts

●Speed up to 3 Mbps

●Hardware and/or software flow control

2.9.2UARTs with software flow control

Main features:

●Separate 16 x 8 (16 location deep x 8-bit wide) transmit and 16 x 12 receive FIFOs to reduce CPU interrupts

●Speed up to 5 Mbps.

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Architecture overview	SPEAr310

2.10Synchronous serial port (SSP)

SPEAr310 provides one synchronous serial port (SSP) block that offers a master or slave interface to enables synchronous serial communication with slave or master peripherals.

Main features:

●Master or slave operation.

●Programmable clock bit rate and prescale.

●Separate transmit and receive first-in, first-out memory buffers, 16-bits wide, 8 locations deep.

●Programmable choice of interface operation:

–SPI (Motorola)

–Microwire (National Semiconductor)

–TI synchronous serial.

●Programmable data frame size from 4 to 16-bits.

●Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts.

●Internal loopback test mode available.

●DMA interface

●4 chip selects available for non concurrent operations on 4 different devices.

2.11I2C

Main features:

●Compliance to the I2C bus specification (Philips)

●Supports three modes:

–Standard (100 kbps)

–Fast (400 kbps)

–High-speed (3.4 Mbps)

●Clock synchronization

●Master and slave mode configuration possible

●Multi-master mode (bus arbitration)

●7-bit or 10-bit addressing

●7-bit or 10-bit combined format transfers

●Slave bulk transfer mode

●Ignores CBUS addresses (predessor to I2C that used to share the I2C bus)

●Transmit and receive buffers

●Interrupt or polled-mode operation

●handles bit and byte waiting at all bus speeds

●Digital filter for the received SDA and SCL lines

●Handles component parameters for configurable software driver support

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2.12TDM/E1 HDLC controller

SPEAr310 features a TDM/E1 HDLC controller which is composed of two main blocks: Time Division Multiplexing (TDM) and High-level Data Link Control (HDLC) engines.

The internal HDLC controller can service up to 128 Tx/Rx channels simultaneously in conventional HDLC mode and supports super-channel configuration. Each channel bit rate is programmable from 4 kbit/s to 64 kbit/s. The maximum bit rate of the TDM interface is 8 Mbps.

2.12.1TDM interface

Main features:

●Six interface signals

●Duplex Tx/Rx communication

●128 timeslots per frame (125 µs)

●Up to 8 Mbps per Tx/Rx channel

●Supports any timeslot banding on any Tx/Rx channel

●Tx/Rx Data sending/sampling time is configurable after/on the rising/falling edge of TxCLK/RxCLK.

●Delay between the bit 0 of TS0 and the SYNC signal is configurable (0 - up to 3 Tx/Rx clock cycles delay)

●The TDM/E1 interface is entirely dedicated to the HDLC protocol

2.12.2E1 interface

Main features:

●Six interface signals

●Duplex Tx/Rx communication

●Up to 2 Mbps per Tx/Rx channel

●32 timeslots / frame (125 µs)

●Supports any timeslot banding on any Tx/Rx channel

●Tx/Rx Data sending/sampling time is configurable after/on the rising/falling edge of TxCLK/RxCLK.

●Delay between the bit 0 of TS0 and the SYNC signal is configurable (0 - up to 3 Tx/Rx clock cycle delay)

2.13RS485 HDLC ports

SPEAr310 features two RS485 HDLC ports.

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Main features:

●Each RS485 interface has five signals

●Supports duplex Tx/Rx communication

●Maximum Tx/Rx data rate of RS485 HDLC is 3.88 Mbps

●Supports collision detection and automatic frame re-transmission

●Data sending/sampling timing is configurable:

–Tx Data can be sent out after the rising/falling edge of TxCLK

–Rx Data are sampled on the rising/falling edge of RxCLK

●No clock duty cycle constraints, data sending/receiving depends only on the rising/falling edge of Tx/Rx clock

2.13.1HDLC controller

Main features:

●Compliant with ISO/IEC13239

●Standard HDLC frame code/decode

●Opening flag

●One or two bytes for address recognition (reception) and insertion (transmission)

●Payload with bit stuffing

●Frame check sequence: 16 bit CRC with polynomial G(x) = X16+X12+X5+1

●Closing flag

2.14GPIOs

A maximum of 102 GPIOs are available when part of the embedded IPs are not needed (see "Pin description" table).

Within its basic subsystem, SPEAr310 provides twelve General Purpose Input/Output (GPIO) block. Each GPIO block provides 8 programmable inputs or outputs.

Main features of the GPIO are:

●Eight individually programmable input/output pins (default to input at reset)

●An APB slave acting as control interface in "software mode"

●Programmable interrupt generation capability on any number of pins.

●Hardware control capability of GPIO lines for different system configurations.

●Bit masking in both read and write operation through address lines.

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2.158-channel ADC

Main features:

●Successive approximation conversion method

●10-bit resolution @1 Msps

●Hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and accumulation

●Eight analog input (AIN) channels, ranging from 0 to 2.5 V

●INL ± 1 LSB, DNL ± 1 LSB

●Programmable conversion speed, (min. conversion time is 1 µs)

●Programmable averaging of results from 1 (No averaging) up to 128

●Programmable auto scan for all the eight channels.

2.16SMII Ethernet controller

SPEAr310 features four Ethernet MACs providing SMII interfaces.

Each MAC channel has dedicated TX/RX signals while synchronization and clock signals are common for PHY connection.

Figure 4 shows the typical SMII configuration (a generic example with four ports):

Figure 4. Typical SMII system

	1	TX
SMII 1	1	RX
SMII 2	1	TX
	1	RX
			Quad
	1	TX	PHY
SMII 3
	1	RX
SMII 4	1	TX
	1	RX
		SYNC
		Clock

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Architecture overview	SPEAr310

Each Ethernet port provides the following features:

●Compatible with IEEE Standard 802.3

●10 and 100 Mbit/s operation

●Full and half duplex operation

●Statistics counter registers for RMON/MIB

●Interrupt generation to signal receive and transmit completion

●Automatic pad and CRC generation on transmitted frames

●Automatic discard of frames received with errors

●Address checking logic supports up to four specific 48-bit addresses

●Supports promiscuous mode where all valid received frames are copied to memory

●Hash matching of unicast and multicast destination addresses

●External address matching of received frames

●Physical layer management through MDIO interface

●Supports serial network interface operation

●Half duplex flow control by forcing collisions on incoming frames

●Full duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames

●Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames

●Multiple buffers per receive and transmit frame

●Wake on LAN support

●Jumbo frames of up to 10240 bytes supported

●Configurable Endianess for the DMA Interface (AHB Master)

2.17MII Ethernet controller

	SPEAr310 provides an Ethernet MAC 10/100 Universal (commonly referred to as GMAC-
	UNIV), enabling to transmit and receive data over Ethernet in compliance with the IEEE
	802.3-2002 standard.
Note:	GMAC is a hardware block implementing Ethernet MAC layer 2 processing. GMAC is
	configured for 10/100 Mbps operation on SPEAr3xx family and up to 1 Gbps on SPEAr600.

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