ST SPEAr1340 User Manual
Dual-core Cortex A9 HMI embedded MPU
PBGA (23 x 23 mm)
Features
■ CPU subsystem:
– 2x ARM Cortex A9 cores, up to 600 MHz
– 32+32 KB L1 caches per core, with parity
check
– Shared 512 KB L2 cache
– Accelerator coherence port (ACP)
■ Network-on-chip bus matrix, up to 166 MHz
■ 32 KB Boot ROM, 32+4 KB Static RAMs
■ Memory interfaces:
– DDR controller (DDR3-1066, DDR2-1066
@533MHz), 16-/32-bit, up to 2 GB address
space
– Serial NOR Flash controller
– Parallel NAND Flash/NOR Flash/SRAM
controller
■ Connectivity:
– 2 x USB 2.0 Host ports (integrated PHY)
– 1 x USB 2.0 OTG port (integrated PHY)
– 1 x Giga/Fast Ethernet port (external GMII/
RGMII/MII/RMII PHY)
– 1 x PCIe 2.0 RC/EP port (integrated PHY)
– 1 x 3Gb/s Serial ATA Host port (integrated
PHY)
– 1 x memory card interface: SD/SDIO/MMC,
CF/CF+, xD
– 2 x UART ports, with IrDA option
– 2 x I2C bus controllers, master/slave
– 1 x synchronous serial port,
SPI/Microwire/TI protocols, master/slave
– 2 x consumer electronic control (HDMI
CEC) ports
– 10-bit ADC: 8 ch. 1 Msps, with autoscan
– Programmable bidirectional GPIO signals
with interrupt capability
■ HMI support:
– LCD display controller, incl.support for Full
HD, 1920 x 1080, 60 Hz, 24 bpp
SPEAr1340
Datasheet − preliminary data
– High-perf. 2D/3D GPU, up to 1080p
– Hardware video decoder: multistandard up
to 1080p, JPEG
– Hardware video encoder: H.264 up to
1080p, JPEG
– Video input parallel port, with alternate
configuration for 4 x camera interfaces
– Digital audio ports: up to 7.1 multichannel
surround, I2S (8 in, 8 out) and S/PDIF
– 6 x 6 keyboard controller
– Resistive touchscreen interface
■ Security:
– Cryptographic co-processor: DES, 3DES,
AES, HMAC, PKA, RNG
– Secure boot support
– JTAG disable option
■ Miscellaneous functions:
– Energy saving: power islands, clock gating,
dynamic frequency scaling
– 2 x DMA controllers (total 16 channels)
– 11 x general purpose timers, 2 x watchdogs,
1 x real-time clock
– 4 x PWM generators
– Embedded sensor for junction temperature
monitoring
– OTP (one-time programmable) bits
– Debug and trace interfaces: JTAG/PTM
Table 1. Device summary
Order code
SPEAr1340-2 -40 to 85
Temp.
range, °C
Package Packing
PBGA
(23x23mm,
pitch 0.8mm)
Tr ay
August 2012 Doc ID 023063 Rev 2 1/194
www.st.com
1
Contents SPEAr1340
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Device functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Multilayer interconnect matrix (BUSMATRIX) . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Internal memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1 BootROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 Static RAMs (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Multiport DDR controller (MPMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Serial NOR Flash controller (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 USB 2.0 Host controllers (UHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 USB 2.0 OTG port (UOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9 Giga/Fast Ethernet port (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.10 PCI Express controller (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.11 Serial ATA controller (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12 SATA/PCIe physical interface (MiPHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.13 Memory card interfaces (MCIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.14 UART ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.15 I2C bus controllers (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.16 Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.17 A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.18 HDMI CEC interfaces (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.19 General purpose I/O (GPIO/XGPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20 LCD display controller (CLCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.21 Graphics processing unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.22 Video decoder (VDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.23 Video encoder (VENC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.24 Camera input interfaces (CAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.25 Video input parallel port (VIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.26 I2S digital audio ports (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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2.27 S/PDIF digital audio port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.28 Keyboard controller (KBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.29 Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.30 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.31 DMA controllers (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.32 General purpose timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.33 PWM generators (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.34 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.35 Reset and clock generator (RCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.36 Power control module (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.37 Temperature sensor (THSENS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.38 One-time programmable antifuse (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . 38
3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1 Pin map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 Ball characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 Power supply signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.4 Multiplexed signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.1 MAC Ethernet port multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.2 KBD multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.4.3 MCIF multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.4.4 FSMC multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.5 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.5.1 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.5.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.5.3 Clocks and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.5.4 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.5.5 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.5.6 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.5.7 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.5.8 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.5.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.6 Strapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Contents SPEAr1340
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.3 Clocking parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.3.1 Master clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.3.2 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.4 I/O AC/DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.4.1 3V3/2V5/1V8 I/O buffers (IOTYPE1/IOTYPE2/IOTYPE3) . . . . . . . . . . 135
4.4.2 IOTYPE4 I/O buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.4.3 DDR2 and DDR3 mode I/O buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.5 Voltage regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.6 MiPHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.7 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
4.8 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.9 Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.10 Reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.1 Reset timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.2 ADC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.3 ARM trace/JTAG timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.3.1 JTAG timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.3.2 ARM trace timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.4 CAM timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.5 CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.6 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.6.1 NAND Flash configuration timing characteristics . . . . . . . . . . . . . . . . . 153
5.6.2 NOR Flash configuration timing characteristics . . . . . . . . . . . . . . . . . . 155
5.6.3 SRAM configuration timing characteristics . . . . . . . . . . . . . . . . . . . . . 158
5.7 GMAC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.7.1 GMII transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.7.2 GMII receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.7.3 MII transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.7.4 MII receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.7.5 MAC Ethernet asynchronous signals timing characteristics (MAC_CRS
and MAC_COL) 163
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5.7.6 MAC serial management channel timing characteristics (MDIO/MDC) 163
5.8 GPIO/XGPIO timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.9 I2C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.10 I2S timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.11 MCIF timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.11.1 Synchronous mode (SD/SDIO/MMC) . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.11.2 CompactFlash true IDE PIO mode/UDMA mode . . . . . . . . . . . . . . . . . 170
5.12 MPMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.13 PWM timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.14 SMI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.15 SSP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.15.1 SPI master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.15.2 SPI slave mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.16 UART timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.17 VIP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Appendix A Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Appendix B Copyright statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Description SPEAr1340
FPU PTM
CortexA9CPU
32KB
ICache
32KB
DCache
Interrupt
Controller
512KBL2Cache
ACP
Cache
Transfers
Snoop
Filtering
Timer&
Watchdog
CPU0
AXIBus
Master0
AXIBus
Master1
Coresight
Global
Timer
Timer&
Watchdog
CPU1
SCU
MPCore
CPU0
DisplayCtrl
2D/3DGPU
VideoDecoder
VideoEncoder
CameraI/F(4x)
VideoInput
I2SAudioI/F
(8in,8out)
S/PDIFAudioI/F
USB2.0HostCtrl
USB2.0OTGCtrl
USB
PHYs
Giga/Fast
EthernetCtrl
PCIe Ctrl
SATACtrl
PHY
Graphics,video,audio
Highspeedconnectivity
USB2.0HostCtrl
BUSMATRIXInterconnect
GPIO
XGPIO
I2C(2x)
SSP
UART(2x)
KBD
CEC(2x)
ADC
PWM(4x)
RTC
Lowspeedconnectivity
DDR2/3Ctrl
StaticMemoryCtrl
SerialMemoryI/F
MemorycardI/F
Memory
FPU PTM
CortexA9CPU
32KB
ICache
32KB
DCache
CPU1
BootROM
SRAMs
DMACtrl(2x)
Security
Coprocessor
Reset&clockGenerator
PowerControl
Configuration
registers
Timers
JTAG Trace
THSENS OTP
Opt.
Battery
1 Description
The SPEAr1340 device is a system-on-chip belonging to the SPEAr® (Structured Processor
Enhanced Architecture) family of embedded microprocessors. The product is suitable for
consumer and professional applications where an advanced human machine interface
(HMI) combined with high performance are required, such as low-cost tablets, thin clients,
media phones and industrial/printer smart panels.
The device is hardware-compliant to the support of both real-time (RTOS) and high-level
(HLOS) operating systems, such as Android, Linux and Windows Embedded Compact 7.
The architecture of SPEAr1340 is based on several internal components, communicating
through a multilayer interconnection matrix (BUSMATRIX). This switching structure enables
different data flows to be carried out concurrently, improving the overall platform efficiency.
In particular, high-performance master agents are directly interconnected with the DDR
memory controller in order to reduce access latency. The overall memory bandwidth
assigned to each master port can be programmed and optimized through an internal
weighted round-robin (WRR) arbitration scheme.
Figure 1. SPEAr1340 architectural block diagram
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SPEAr1340 Device functions
2 Device functions
2.1 CPU subsystem
The CPU subsystem is based on the ARM Cortex A9 processor, and has a dual-core
configuration.
Main features:
Each core has the following features:
● ARM v7 CPU at 600 MHz
● 32 KB of L1 instruction CACHE with parity check
● 32 KB of L1 data CACHE with parity check
● Embedded FPU for single and double data precision scalar floating-point operations
● Memory management unit (MMU)
● ARM, Thumb2 and Thumb2-EE instruction set support
● Program Trace Macrocell (PTM) and CoreSight
● 32-bit timer with 8-bit prescaler
● Internal watchdog (working also as timer)
©
component for software debug
The dual core configuration is completed by a common set of components:
● Snoop control unit (SCU) to manage inter-process communication, cache-to-cache and
system memory transfer, cache coherency
● Generic interrupt control (GIC) unit configured to support 128 independent interrupt
sources with software configurable priority and routing between the two cores
● 64-bit global timer with 8-bit prescaler
● Accelerator coherence port (ACP)
● Parity support to detect runtime failures for other internal memories
● 512 KB of unified 8-way set associative L2 cache with support for ECC
● L2 Cache controller based on PL310 IP released by ARM
● Dual asynchronous 64-bit AMBA 3 AXI interface with possible filtering on the second
one to use a single port for DDR memory access
● JTAG interface and Trace port: debug and trace can be inhibited through OTP
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Device functions SPEAr1340
2.2 Multilayer interconnect matrix (BUSMATRIX)
The multilayer interconnect matrix is the connectivity infrastructure that enables data
exchange between the various blocks of the device. The BUSMATRIX supports parallel
communications between master and slave components, and ensures the maximum level of
system throughput.
Main features:
● Hierarchical structure to meet the requirements of different system blocks and
peripherals:
– high performance low latency
– high performance medium latency
– medium performance medium/long latency
– slow peripherals and configurations
● Power awareness through the power down request/acknowledgement of the power
management module
● Single interrupt for outband signaling
2.3 Internal memories
SPEAr1340 integrates two embedded memories:
● 32 KB Boot ROM (BootROM)
● Static RAM areas (SRAM)
2.3.1 BootROM
BootROM refers to the on-chip 32 KB ROM as well as the booting firmware pre-stored in
such memory. The supported booting devices are:
● Serial NOR Flash
● Parallel NOR Flash
● NAND Flash
● USB OTG
● UART
● SD/MMC
The BootROM firmware selects the booting device after reset by reading the status of the
STRAP[3:0] pins.
2.3.2 Static RAMs (SRAM)
A part of these memory areas is used during the bootstrap phase by BootROM firmware.
After booting, all SRAM areas are fully available for general purpose applications.
Main features:
● 32 KB of system RAM (SYSRAM0, single port)
When all power islands are switched off, SYSRAM0 loses its data content.
● 4 KB of Always-on RAM (SYSRAM1, single port)
When all power islands are switched off, SYSRAM1 maintains its data content.
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SPEAr1340 Device functions
2.4 Multiport DDR controller (MPMC)
MPMC is a high-performance multichannel memory controller able to support DDR2 and
DDR3 memory devices. The multiport architecture ensures that memory is shared efficiently
among different high-bandwidth client modules.
Main features:
● Supports both DDR3 and DDR2 devices; wide range of memory device cuts supported
up to 2 GB (Note: 1)
● Two chip selects supported
● Programmable memory data path size of full memory 32-bit data width or half memory
16-bit data width
● Clock frequencies from 100 MHz to 533 MHz supported
● 6 AXI interfaces with a data interface width of 64 bits. Each port is configured with a
thread ID of 4 bits
● Exclusive and locked accesses support
● Weighted round-robin arbitration scheme support to ensure high memory bandwidth
utilization
● DRAM command processing
● Register port with an AHB interface with a data interface width of 32 bits
● A programmable register interface to control memory device parameters and protocols
including auto pre-charge
● Full initialization of memory on memory controller reset
● Automatically maps user addresses to the DRAM memory in a contiguous block
addressing starts at user address 0 and ends at the highest available address
according to the size and number of DRAM devices present
● Fully pipelined command, read and write data interfaces to the memory controller
● Advanced bank look-ahead features for high memory throughput
Note: 1 When the 2GB address space is enabled, the ACP function is not available.
2.5 Serial NOR Flash controller (SMI)
The serial NOR Flash controller integrated in SPEAr1340 acts as an AHB slave interface
(32-, 16- or 8-bit) to SPI-compatible off-chip memories. SMI allows the CPU to use these
serial memories either as data storage or for code execution.
Main features:
● Supports a group of SPI-compatible Flash and EEPROM devices
● Acts always as an SPI master and up to 2 SPI slave memory devices are supported
(through as many chip select signals), with up to 16 MB address space each.
● The SMI clock signal (smi_clk_o) is generated by SMI (and inputs to all slaves) using a
clock provided by the AHB bus
● smi_clk_o can be controlled by a programmable 7-bit prescaler allowing 127 different
clock frequencies.
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Device functions SPEAr1340
2.6 Flexible static memory controller (FSMC)
The flexible static memory controller enables to interface external parallel Flash memories
as well as static RAMs.
Main features:
● Support for parallel NAND Flash:
– 8-bit or 16-bit data bus
– 2 chip select signals
– no limitation on NAND capacity (number of pages)
– hardware ECC (error correction code) support, correcting up to 8 errors per page
(512 bytes wide)
– support for SLC (single-level cell) and MLC (multi-level cell) Flash devices, as far
as compatible with available ECC features
● Support for parallel NOR Flash:
– 8-bit or 16-bit data bus
– 26-bit address bus
– 2 chip select (CS) signals
– Maximum capacity is 64 MB for each CS, hence up to 128 MB with 2 external
Flash devices
● Support for asynchronous static RAMs (SRAMs):
– 8-bit or 16-bit data bus
– 26-bit address bus
– 2 chip select (CS) signals
– Maximum capacity is 64 MB for each CS, hence up to 128 MB with 2 external
SRAM devices
● Support for multiplexed NOR and SRAM
● Write FIFO: 16 words depth, each word is 32 bits wide
● Independent read/write timings and protocol, allowing matching the widest variety of
memories and timings
● Wait signal for timings handshake
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SPEAr1340 Device functions
2.7 USB 2.0 Host controllers (UHC)
The SPEAr1340 device integrates 2 USB Host interfaces. Each interface provides a highspeed Host controller (EHCI standard) and a full-speed/low-speed controller (OHCI
standard). The UHC has 2 physical ports (2 separate instances) that are fully compliant with
the Universal Serial Bus specification (version 2.0), and provides an interface to the
industry-standard AHB bus.
Main features:
● A PHY interface implementing a USB 2.0 transceiver macro-cell interface plus (UTMI+)
fully compliant with UTMI+ specification (revision 1.0), to execute serialization and deserialization of transmissions over the USB line
● Either 30 MHz clock for 16-bit interface or 60 MHz for 8-bit interface supported by the
UTMI + PHY interface
● A USB 2.0 host controller (UHC) connected to the AHB bus that generates the
commands for the UTMI+PHY
● Complies with both the enhanced host controller interface (EHCI) specification (version
1.0) and the open host controller interface (OHCI) specification (version 1.0a)
● The UHC supports the 480 Mbps high-speed (HS) for USB 2.0 through an embedded
EHCI Host Controller, as well as the 12 Mbps full-speed (FS) and the 1.5 Mbps lowspeed (LS) for USB 1.1 through one integrated OHCI Host controller
● All clock synchronization is handled within the UHC
● An AHB slave for each controller (1 EHCI and 1 OHCI), acting as programming
interface to access to control and status registers
● An AHB master for each controller (1 EHCI and 1 OHCI) for data transfer to system
memory, supporting 8-, 16-, and 32-bit wide data transactions on the AHB bus
● 32-bit AHB bus addressing
2.8 USB 2.0 OTG port (UOC)
Main features:
● Complies with the On-The-Go supplement to the USB 2.0 specification (revision 1.3)
● Supports the Session Request Protocol (SRP)
● Supports the Host Negotiation Protocol (HNP)
● A PHY interface implementing the USB 2.0 transceiver macrocell interface (UTMI+
specification, revision 1.0 (Level 3)) to execute serialization and de-serialization of
transmissions over the USB line
● Unidirectional and bidirectional 16-bit UTMI data bus interfaces
● Support for the following speeds:
– High speed (HS): 480 Mbps
– Full speed (FS): 12 Mbps
– Low speed (LS): 1.5 Mbps (only in Host mode)
● Both of the DMA and slave-only modes are supported
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Device functions SPEAr1340
2.9 Giga/Fast Ethernet port (GMAC)
The GMAC IP provides the capability to transmit and receive data over Ethernet.
Main features:
● Supports 10/100/1000 Mbps data transfer rates with the following PHY interfaces:
– IEEE 802.3-compliant GMII/MII interface (default) to communicate with an external
Gigabit/Fast Ethernet PHY
– RGMII interface to communicate with an external gigabit PHY
– RMII interface (specification version 1.2 from RMII consortium) to communicate
with an external Fast Ethernet PHY (for 10/100 Mbps operations only)
● Full-duplex operation:
– IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on
flow control input de-assertion
– Optional forwarding of received pause control frames to the user application
● Half-duplex operation:
– CSMA/CD Protocol support
– Flow control using back-pressure support
– Frame bursting and frame extension in 1000 Mbps half-duplex operation
● Automatic CRC and pad generation controllable on a per-frame basis
● Provides options for automatic pad/CRC stripping on receive frames
● Supports a variety of flexible address filtering modes, such as:
– Up to 31 48-bit SA address comparison check with masks for each byte
– 64-bit hash filter for multicast and unicast (DA) addresses
– Option to pass all multicast addressed frames
– Promiscuous mode support to pass all frames without any filtering for network
monitoring
– Passes all incoming packets (per filter) with a status report
● Programmable frame length to support standard or jumbo Ethernet frames with up to
16 KB of size
● Programmable interframe gap (IFG) (40-96 bit times in steps of 8)
● Separate 32-bit status for transmit and receive packets
● IEEE 802.1Q VLAN tag detection for reception frames
● Self-managed DMA transfers with an internal DMA block
● Separate transmission, reception, and control interfaces to the application
– The host CPU uses a 32-bit AHB (AMBA 2.0) slave interface to access the GMAC
subsystem control and status registers (CSRs)
– The GMAC transfers data to system memory through a 32-bit AXI (AMBA 3.0)
master interface
● Support for network statistics with RMON/MIB counters (RFC2819/RFC2665)
● A module for detection of LAN remote wake-up frames and AMD magic packet frames:
power management module (PMT)
● A receive module for checksum off-load for received IPv4 and TCP packets
encapsulated by the Ethernet frame (Type 1)
● An enhanced receive module for checking IPv4 header checksum and TCP, UDP, or
ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type 2)
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SPEAr1340 Device functions
● An enhanced module to calculate and insert IPv4 header checksum and TCP, UDP, or
ICMP checksum in frames transmitted in store-and-forward mode.
● A module to support Ethernet frame time stamping as described in IEEE 1588- 2002
and IEEE 1588-2008 (standard for precision networked clock synchronization). Sixtyfour-bit time stamps are given in the transmit or receive status of each frame.
● MDIO master interface for PHY device configuration and management: station
management agent (SMA), MDIO module
● Supports the standard IEEE P802.3az, version D2.0 for energy efficient Ethernet;
allows physical layers to operate in the low-power idle (LPI) mode
The MAC transaction level (MTL) block consists of two sets of FIFOs: a transmit FIFO
with programmable threshold capability, and a receive FIFO with a programmable threshold
(default of 64 bytes). The MTL block has the following features:
● 32-bit transaction layer block that provides a bridge between the application and the
GMAC
● Single-channel transmit and receive engines
● Synchronization for all clocks in the design (transmit, receive, and system clocks)
● Optimization for packet-oriented transfers with frame delimiters
● Four separate ports for system-side and GMAC side transmission and reception
● FIFO instantiation outside the top-level module to facilitate memory testing/instantiation
● 4 KB receive FIFO size on reception
● Supports receive status vectors insertion into the receive FIFO after the EOF transfer.
This enables multiple-frame storage in the receive FIFO without requiring another FIFO
to store those frames
● Configurable receive FIFO threshold (default fixed at 64 bytes) in cut-through or
threshold mode
● Provides an option to filter all error frames on reception and not forward them to the
application in store-and-forward mode.
● Provides an option to forward under-sized good frames
● Supports statistics by generating pulses for frames dropped or corrupted (due to
overflow) in the receive FIFO
● 2 KB FIFO size on transmission
● Store and forward mechanism for transmission to the GMAC
● Threshold control for transmit buffer management
● Automatic retransmission of collision frames for transmission
● Discards frames on late collision, excessive collisions, excessive deferral, and under-
run conditions
● Software control to flush TX FIFO
The DMA block exchanges data between the MTL block and host memory. The host can
use a set of registers (DMA CSR) to control the DMA operations. The DMA block supports
the following features:
● 32-bit data transfers
● Single-channel transmit and receive engines
● Fully synchronous design operating on a single system clock (except for CSR module,
when a separate CSR clock is configured)
● Optimization for packet-oriented DMA transfers with frame delimiters
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Device functions SPEAr1340
● Byte-aligned addressing for data buffer support
● Dual-buffer (ring) or linked-list (chained) descriptor chaining
● Descriptor architecture that allows large blocks of data transfer with minimum CPU
intervention
● Comprehensive status reporting for normal operation and transfers with errors
● Individual programmable burst size for transmit and receive DMA engines for optimal
host bus utilization
● Programmable interrupt options for different operational conditions
● Complete per-frame transmit/receive interrupt control
● Round-robin or fixed-priority arbitration between receive and transmit engines
● Start/stop modes
● Separate ports for host CSR access and host data interface
The GMAC audio video (AV) enables transmission of time-sensitive traffic over bridged
local area networks (LANs). The GMAC AV has the following features:
● Compliant to IEEE 802.1-AS standard, version D6.0: specifies the protocol and
procedures used to ensure that the synchronization requirements are met for timesensitive applications
● Compliant to IEEE 802.1-Qav standard, version D6.0: allows the bridges to provide
time-sensitive and loss-sensitive real-time audio video data transmission (AV traffic). It
specifies the priority regeneration and controlled bandwidth queue draining algorithms
that are used in bridges and AV traffic sources
● Supports one additional channel (channel 1) on the transmit and receive paths for AV
traffic in 100 Mbps and 1000 Mbps modes. The channel 0 is available by default and
carries the legacy best-effort Ethernet traffic on the transmit side.
● Supports IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for the
additional transmit channels
● Provides separate DMA, TxFIFO, and RxFIFO MTL for the additional channel (to avoid
“head of line blocking” issues); the system-side interface remains the same.
The GMAC has the following additional features for monitoring, testing, and debugging:
● Supports internal loopback on the GMII/MII for debugging
● Provides DMA states (Tx and Rx) as status bits
● Provides debug status register that gives status of FSMs in transmit and receive data-
paths and FIFO fill-levels
● Application abort status bits
● MMC (RMON) module in the GMAC core
● Current Tx/Rx buffer pointer as status registers
● Current Tx/Rx descriptor pointer as status registers
● Statistical counters that help in calculating the bandwidth served by each transmit
channel when AV support is enabled
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SPEAr1340 Device functions
2.10 PCI Express controller (PCIe)
The PCI Express core incorporates a dual-mode (DM) core which can implement a PCIe
interface for a PCIe Root Complex (RC) or Endpoint (EP). The dual-mode core can operate
in EP or RC port modes, depending on value written in a register during PCIe configuration.
PCIe is compliant with the PCI Express Base 2.0 specification, but it is also compliant with
the PCIe 1.1 specification.
The core features a proprietary user-configurable and high-performance application
interface for generating and receiving PCIe traffic. It is available with standard AMBA 3 AXI
interfaces.
Typical applications for a PCI Express device built with the DM core include:
● Motherboard components for desktop and mobile computers
● Graphics devices
● Add-in cards for desktop and mobile computers
● Components and add-in cards in server applications
● Embedded applications
● Data communications equipment
● Telecommunications equipment
● Storage devices
● Wireless devices
● Other applications
The DM core in EP mode supports PCI Express Legacy Endpoint devices. However, the
application must ensure that the device obeys the Legacy Endpoint device rules defined in
the PCI Express Base 2.0 specification.
Note: The core is not intended for use in a root complex integrated endpoint.
Main features (common to both EP and RC mode of the DM cores):
● Support for all non-optional features and some optional features defined in the PCI
Express Base 2.0 specification.
● Ultra low transmit and receive latency
● Support a max payload size of 256 bytes
● 4 KB maximum request size
● Very high accessible bandwidth
● Support for both Gen1 (at 125 MHz) and Gen2 (at 250 MHz) operation
● 2.5 Gbps (Gen1) or 5.0 Gbps (gen2) Lane (x1)
● Automatic lane reversal as specified in the PCI Express 2.0 specification (transmit and
receive)
● Polarity inversion on receive
● Multiple virtual channels (VCs) (maximum of 2)
● Multiple traffic classes (TCs)
● ECRC generation and checking
● PCI Express beacon and wake-up mechanism
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Device functions SPEAr1340
● PCI power management
● PCI Express active state power management (ASPM)
● PCI Express advanced error reporting
● Vital product data (VPD)
● PCIe messages for both transmit and receive.
● External priority arbitration (in addition to the internally implemented transmit
arbitration)
● Expansion ROM support
Additional features specific to RC mode
● Type 1 configuration space
● Application-initiated Lane reversal for situations where the core does not detect Lane 0
(for example, an x4 core connected to an x8 device that has its Lanes reversed)
Additional features specific to EP mode
● Completion time-out ranges
● Type 0 configuration space
● MSI interrupt capability
2.11 Serial ATA controller (SATA)
The SATA AHCI Core implements the serial advanced technology attachment (SATA)
storage interface for physical storage devices.
Main features:
● SATA 3.0 Gb/s Gen II
● eSATA (external analog logic also needs to support eSATA)
● Compliant with the following specifications:
– Serial ATA 3.0 (except FIS-based switching)
– AHCI Revision 1.3 (except FIS-based switching)
– AMBA 3 AXI interfaces
● User-defined PHY status and control ports
● RX data buffer for recovered clock systems
● Data alignment circuitry when RX data buffer is also included
● OOB signaling detection and generation
● 8b/10b encoding/decoding
● Asynchronous signal recovery, including retry polling
● Digital support of device hot-plugging
● Power management features including automatic partial-to-slumber transition
● BIST loopback modes
● Single SATA device
● Internal DMA engine per port
● Hardware-assisted native command queuing for up to 32 entries
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SPEAr1340 Device functions
● Port Multiplier with command-based switching
● Disabling RX and TX Data clocks during power down modes
● Integrated SATA link layer and transport layer logic
● Supports PIO, first party and legacy DMA modes
● Supports legacy command queuing
● Supports ATA and ATAPI master-only emulation mode (for instance, register and
command compatible with these standards)
● Power-down mode
● Data scrambling
● CRC computation
● Automatic data flow control
● Far end loop-back re-timed
2.12 SATA/PCIe physical interface (MiPHY)
The MiPHY macrocell implements the lower (physical) layer protocols providing data
transmission and reception over a dual differential pair cable. The TX (transmit) and RX
(receive) serial channels operate plesiochronously (NRZ). The macrocell can be used in
Host or Device applications.
Main features:
● Serial transceiver (PHYsical layer) serializer and deserializer
● Direct support for 1.5/ 3.0 and 1.25/ 2.5/ 5.0 Gbit/s bit rates
● 20-bit parallel interface
● Comma detect to provide word alignment of incoming serial stream
● SSC modulation
● Integrated impedance adaptation to transmission line characteristics
● Out-of-band (OOB) signaling
● Supported 1.2 V and 2.5 V power supply
● High-performance PLL (input reference 100 MHz for PCIe and 100 or 25 MHz for
SATA)
● Programmable TX buffer pre-emphasis, slew-rate and amplitude
● Dedicated TX buffer regulator for:
– Transmit buffer noise immunity
– Buffer level stability
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Device functions SPEAr1340
2.13 Memory card interfaces (MCIF)
MCIF is a hardware IP that interfaces with the most common memory cards on the market:
● SD/SDIO 2.0
● SDHC
● CF/CF+ Rev 4.1
● MMC 4.2/4.3
● xD
The device interface multiplexes different memory cards on the same IOs; only one memory
card is accessible at a given time. At the board level, discrete elements are required to
handle host-swap management.
Main features:
SD/SDIO/MMC controller
● Compliant with:
– SD Host controller standard specification version 2.0
– SDIO card specification version 2.0
– SD memory card specification draft version 2.0
– SD memory card security specification version 1.01
– MMC specification version 3.31, 4.2 and 4.3
– AMBA specification AHB (version 2.0)
● Data transfer with the system core through:
– PIO mode on the Host AHB slave interface
– DMA mode on the Host AHB master interface
● Host clock rate variable from 0 to 50 MHz
● Maximum data rate achievable:
– 200 Mbps (sd4 bit mode)
– 400 Mbps (mmc8 bit mode)
● Data transfer:
– SD mode: 1 bit, 4 bit, and SPI mode
– MMC mode: 1 bit, 4 bit, 8 bit, and SPI mode
● Cyclic redundancy check for commands (CRC7) and for data integrity (CRC16)
● Variable length data transfer
● Read wait control and suspend/resume operations supported
● Works with IO cards, read-only cards and read/write cards
● Supports MMC Plus and MMC Mobile
● Error correction code support for MMC 4.3 cards
● Card detection (insertion/removal)
● Card password protection
● Two 4K FIFO to aid data transfer between the CPU and the controller
● FIFO overrun and underrun handled by stopping the SD clock
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SPEAr1340 Device functions
CF/CF+ Host controller
● CF Specification Revision 4.1 compliance (True IDE Mode only)
● Multiword DMA to transfer data between the host and the CF/+ device
● Ultra DMA mode for accessing the CF/+ card using the 16-bit data path
● PIO timing mode0 through mode6
● Multiword DMA timing mode0 through mode4
● Ultra DMA timing mode0 through mode6
● Data transfers up to 256 (512 byte) blocks
● Variable-length data transfer in multiword DMA and Ultra DMA modes
● Interrupt-driven data transfers in PIO mode
xD Host controller (Xtreme Digital)
● Comfortable erase mechanism
● Programmable access timing
● Read, write, erase, read device ID, status and reset commands
● ECC generation and checking
● Multiblock programming and multiblock erase
● 1 Gbit, 2 Gbit support
2.14 UART ports
The SPEAr1340 device integrates 2 instances of an asynchronous serial port (UART) digital
block, identified as UART0 and UART1.
Asynchronous serial ports are responsible for performing the main tasks in serial
communications with computers. The device converts incoming parallel information into
serial data and incoming serial information into parallel data that can be sent on a
communication line connected to an external peripheral device.
The SPEAr1340 embedded MPU provides two independent UART controllers. One of the
typical uses of UART is connecting the SPEAr-based platforms to debugging consoles, the
communication with modems and the interfacing of Bluetooth, DECT or ZigBee chipsets.
The UART features inside SPEAr1340 offer similar functionality to the industry-standard
16C650 UART device.
UART ports usually do not directly generate or receive the external signals used between
different items of equipment. External interface devices are used to convert the logic level
signals of the UART to and from the external signaling levels. External signals may be of
many different forms, such as RS-232, infrared and wireless radio. In particular, the UART
interfaces inside SPEAr1340 directly support (by software selection) the IrDA-compliant
Serial InfraRed (SIR) protocol.
The UART supports standard asynchronous communication bits (start, stop, and parity),
which
are added prior to transmission and removed on reception.
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Device functions SPEAr1340
Main features:
UART0 and UART1:
● Support baud rate up to UARTCLK/16
● Programmable baud rate generation (integer and fractional parts)
● Support three options on the UARTCLK clock frequency:
– 48 MHz: maximum baud rate of 3 Mbps (48/16)
– 24 MHz: maximum baud rate of 1.5 Mbps (24/16)
– Programmable by software: up to 125 MHz with a maximum baud rate of 7.81
Mbps (125/16).
● Separate 16x8 transmit and 16x12 receive first-in, first-out memory buffers (FIFOs)
● Programmable FIFO disabling for 1-byte depth
● FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4 and 7/8
● Independent masking of transmit FIFO, receive FIFO, receive time-out, and error
condition interrupts
● Support for direct memory access (DMA)
● False start bit detection
● Line break generation and detection
● Programmable usage of IrDA SIR encoder/decoder:
IrDA SIR ENDEC block provides:
– Support of IrDA SIR ENDEC functions for data rates up to 115.2 Kbits/second
half-duplex
– Support of normal 3/16 and low-power bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to
256 for low-power mode bit duration
● Fully-programmable serial interface characteristics:
– data can be 5, 6, 7, or 8 bits
– even, odd, stick, or no-parity bit generation and detection
– 1 or 2 stop bit generation
UART0 only:
● Programmable hardware flow control which uses the CTS input and the RTS output to
automatically control the serial data flow
● Support modem status which uses:
– Input signals: Clear To Send (CTS), Data Carrier Detect (DCD), Data Set Ready
(DSR), and Ring Indicator (RI)
– Output modem control lines: Request To Send (RTS), and Data Terminal Ready
(DTR)
● Independent masking of modem status
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SPEAr1340 Device functions
2.15 I2C bus controllers (I2C)
The SPEAr1340 device integrates 2 instances of an I2C controller, identified as I2C0 and
I2C1, which can be used to connect to the I2C bus peripheral.
Main features:
● Compliant to the I2C-bus specification from Philips
● Three different operating modes:
– Standard-speed mode (data rates up to 100 Kb/s)
– Fast-speed mode (data rates up to 400 Kb/s)
– High-speed mode
● Clock synchronization
● Master or slave I2C operation mode
● Multimaster operation mode (bus arbitration)
● Support for direct memory access (DMA)
● 7-bit or 10-bit addressing
● 7-bit or 10-bit combined format transfers
● Slave bulk transfer mode
● Ignores CBUS addresses (an older ancestor of I2C that used to share the I2C bus)
● Buffer transmission and reception
● Interrupt or polled-mode operation
● Handles bit and byte waiting at all bus speeds
● Digital filter for the received SDA and SCL lines
2.16 Synchronous serial port (SSP)
The synchronous serial port block includes a master or slave interface to enable
synchronous serial communication with slave or master peripherals.
Main features:
● Master or slave operation
● Programmable clock bit rate and prescaler
● Separate transmit and receive first-in, first-out memory buffers, 16-bit wide, 8 locations
deep
● Programmable choice of interface operation, SPI, Microwire, or TI synchronous serial
● Programmable data frame size from 4 to 16 bits
● Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts
● Internal loopback test mode available
● Support for direct memory access (DMA)
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Device functions SPEAr1340
2.17 A/D converter (ADC)
SPEAr1340 integrates an analog-to-digital converter.
Main features:
● Successive approximation A/D conversion
● 10-bit resolution for the analog cell which can be extended up to 12 bits with embedded
oversampling techniques performed by the controller
● 1 MSPS
● 8 analog input channels (0 – 2.5 V)
● INL ± 1 LSB
● DNL ± 1 LSB
● Programmable conversion speed – minimum conversion time 1 µs
● Support for resistive touchscreen
2.18 HDMI CEC interfaces (CEC)
The SPEAr1340 device integrates 2 instances of a Consumer Electronics Control (CEC)
digital block, identified as CEC0 and CEC1.
CEC is an asynchronous transfer mode adaptation layer (AAL) protocol that provides highlevel control functions among the various audiovisual products in a user’s environment. CEC
operates at low speeds, with minimal processing and memory overhead.
Main features:
● AMBA 2.0 compatible
● One touch play: Play a device and make it the active source with the press of a button
● System standby: Set all devices to standby with the press of a button
● Preset transfer: Auto-configures device presets to match those of the TV
● One-touch record: Enables one-button recording
● Timer programming: Any device can program a recording device’s timer
● System information: Devices can auto-configure their language and country settings
● Deck control: A device can control and interrogate a playback device
● Tuner control: A device can control the tuner of another device
● Vendor specific commands: Enables the use of vendor-defined commands
● On-screen display (OSD): A device can display text on the TV screen
● Device menu control: A device can control the menu of another device
● Routing control: Enables CEC switch control, to stream a new source device
● Remote control pass through: Enables the passing on of remote control commands to
other devices
● Device OSD name transfer: System devices can request the preferred object-based
storage device (OSD) name of other system devices
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SPEAr1340 Device functions
2.19 General purpose I/O (GPIO/XGPIO)
SPEAr1340 handles generic input/outputs in 3 ways. First, the device integrates 2 instances
of a general purpose I/O (GPIO) digital block, identified as GPIOA and GPIOB. Second, an
extended GPIO (XGPIO) feature is provided. Finally, it is possible to use the KBD controller
in GPIO mode (this feature is documented in
The GPIO block provides 16 programmable inputs or outputs (8 for GPIOA and 8 for
GPIOB). Each input/output can be controlled by software.
GPIO main features:
● 16 individually programmable input/output pins (by default input at reset)
● An APB slave acting as control interface in software mode
● Programmable interrupt generation capability on any number of pins
● Bit masking in both read and writes operation through address lines
The XGPIOs are individually programmable input/output pins (by default output) that can be
controlled through an AHB slave interface.
XGPIO main features:
● 234 individually programmable input/output pins: XGPIO0 to XGPIO7, and XGPIO24 to
XGPIO249 (by default output). There is just an exception for the bit XGPIO169 which is
always an output.
● Programmable interrupt (rise or fall edge sensitive) generation on any number of pins
● An AHB slave interface as control
Section 2.28: Keyboard controller (KBD)).
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Device functions SPEAr1340
2.20 LCD display controller (CLCD)
The TFT LCD controller provides all the necessary control signals to interface directly to a
variety of TFT LCD panels.
Main features:
● Wide range of programmable LCD panel resolutions
● Support for 1 port TFT LCD panel interfaces:
– 18-bit digital (6-bit/color)
– 24-bit digital (8-bit/color) CMOS
● Support for 2 Port TFT LCD panel interfaces (2
signals)
● Support for up to 2 overlay windows.
● Programmable frame buffer bits-per-pixel (bpp) color depths:
– 1, 2, 4, 8 bpp mapped through the color palette to 18-bit LCD pixel
– up to 18 bpp directly drive 18-bit LCD pixel
– 24 bpp directly drive 24-bit LCD pixel
● Color Palette RAM to reduce Frame Buffer memory storage requirements bandwidth
● Programmable output format support:
– RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface
– RGB 8:8:8 on 24-bit digital interface
● Programmable horizontal timing parameters:
– horizontal front porch, back porch, sync width, pixels-per-line
– horizontal sync polarity
● Programmable vertical timing parameters:
– vertical front porch, back porch, sync width, lines-per-panel
– vertical sync polarity
● Programmable pixel clock frequency up to 148MHz (1080p resolution)
● Programmable data enable timing signal:
– derived from horizontal and vertical timing parameters
– display enable polarity
● Power up and down sequencing support
● Programmable endianness
● Pulse width modulation for LCD panel LED backlight brightness control
nd
port available by programmable
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SPEAr1340 Device functions
2.21 Graphics processing unit (GPU)
The Mali GPU is a hardware accelerator for 2D and 3D graphics systems that forms the
basis of a high performance graphics processing solution. When implemented as part of a
system-on-chip (SoC) device, the GPU forms an integral part of the graphics solution. The
GPU comprises the following:
● an ARM
● a MaliGP2 geometry processor
● a memory management unit (MMU)
● associated software (programmed using OpenVG or OpenGL base layers)
Main features (pixel processor):
● Programmable fragment shader
● Access to framebuffer from fragment shaders
● Alpha blending
● Arbitrary memory reads and writes
● Complete non-power-of-2 texture support
● Cube mapping
● Dynamic recursion
● Fast dynamic branching
● Fast trigonometric functions, including arctangent
● Full floating-point arithmetic
● Framebuffer blend with destination Alpha
● High dynamic range (HDR) textures and framebuffers
● Indexable texture samplers
● Line, quad, triangle, and point sprites
● Multiple render targets
● No limit on program length
● Perspective anisotropic filtering (AF)
● Perspective correct texturing
● Point sampling, bilinear, and trilinear filtering
● Programmable mipmap level-of-detail biasing and replacement
● Register indirect jumps
● Stencil buffering, 8-bit
● Two-sided stencil
● Unlimited dependent texture reads
● Virtualized texture samplers
● 4-level hierarchical Z and stencil operations
● 4 times and 16 times full scene anti-aliasing (FSAA)
● 4-bit per texel texture compression.
®
Mali™200 pixel processor
Geometry processor
● Programmable vertex shader
● Autonomous operation tile list generation
● Flexible input and output formats
● Indexed and non-indexed geometry input
● Primitive constructions with points, lines, triangles and quads.
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Device functions SPEAr1340
Software
● Compatibility with the following graphics standards:
– OpenGL ES 2.0
– OpenGL ES 1.1
– OpenVG 1.0
The geometry processor must be programmed using OpenVG or Open GL base layers.
2.22 Video decoder (VDEC)
Main features:
● All algorithms in hardware - minimal CPU load
● Minimal power consumption - functional level clock gating and synthesis time clock
gating (> 90% of registers under gating)
Supported video codecs:
● H.264 profile and level
– Baseline, main and high profiles
– Decoding up to 1080p/30fps
– Scalable video coding (SVC):
– Baseline and high profiles (base layer only)
● MPEG-4 visual profile and level
– Simple and advanced simple profiles, levels 0 –5
●
H.263 profile and level
– Profile 0, levels 10 –70 (image size up to 720x576)
● Sorenson Spark
● WMV9 / VC-1
– Simple, main and advanced profiles, levels 0 -3
● MPEG-1&2 main profile
– Low, medium and high levels
● RealVideo8/9/10
● DivX®3/4/5/6 support
– Home theater profile qualification
● VP6, VP7 versions 0-3
● VP8 version 2 (WebM)
● AVS Jizhun Profile
● JPEG, all common sampling formats
– Baseline interleaved
(1)
(2)
1. Achievable resolution and frame rate depending on specific stream content and system load.
2. Global motion compensation (GMC) is not supported.
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Supported post-processing features:
● Input image source
– Internal source (combined mode): G1decoder
– External source (standalone mode): for example, a software decoder or camera
interface
● Input image size
– Combined mode: 48 x 48 to 8176 x 8176 (66.8 Mpixels)
– Standalone mode: width from 48 to 8176, height from 48 to 8176 (maximum size
limited to 16.7 Mpixels)
● Output image size
– 16 x 16 to 1920 x 1088
● Image scaling
– Bicubic polynomial interpolation for upscaling
– Proprietary averaging filter for downscaling
– Arbitrary, non-integer scaling ratio separately for both dimensions
● YCbCr to RGB color conversion
– BT.601-5 compliant
– BT.709 compliant
– User definable conversion coefficient
● Dithering
– 2x2 ordered spatial dithering for 4-, 5- and 6-bit RGB channel precision
● Alpha blending
– Output image can be alpha blended with two rectangular areas
● Deinterlacing
– Conditional spatial deinterlace filtering; supports only YCbCr 4:2:0 input format
● linear RGB image contrast, brightness and color saturation adjustment
● Deblocking filter for MPEG-4 simple profile /H.263 / Sorenson
– Using a modified H.264 in-loop filter as a postprocessing filter; filtering has to be
performed in combined mode.
● Image cropping / digital zoom
– User definable start position, height and width
– Usable only for JPEG or stand-alone mode
● Output image masking
● Image rotation
– Rotation 90, 180 or 270 degrees
– Horizontal/vertical flip
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Device functions SPEAr1340
2.23 Video encoder (VENC)
A multiformat video encoder is integrated in SPEAr1340 with 64-bit AXI master and 32-bit
AHB slave interfaces. It supports H.264 high profile video resolution up to 1080p and JPEG
still picture up to 64
Main features:
● H.264 profile and level
– Baseline, main and high profiles, levels 1- 4.0
● JPEG profile and level
– Baseline (DCT sequential)
● Video stabilization
● I and P slices support
● CAVLC baseline and CABAC main profile
● Error resilience
– Constrained intra prediction
– Slices, multiple of macro blocks rows
● Maximum motion vector length
– Vertical ±14 pixels
– Horizontal ±30pixels
● 12 intra prediction modes
● Motion vector pixel accuracy
– 720p resolution ¼ pixels
– 1080p resolution ½ pixels
● Macroblock and sub-macroblock partitions: 16x16, 8x16, 16x8, 8x8, 4x8, 8x4,4x4
● Transforms 4x4 baseline, main and high profiles
● 1 reference frame support
● Maximum 1 slice group support
● Input data formats
– Planar YCbCr 4:2:0, semiplanar YCbCr 4:2:0, interleaved YCbCr 4:2:2
● Output data formats
– H.264 (Byte and NAL unit stream)
– JPEG( JFIF file format 1.02 and non progressive JPEG)
● Supported image size
– H.264: 96x96 to1920x1020
– JPEG: 96x96 to 8192x8192
– Step size 4 pixels
● Pre-processing features
– YCbCr 4:2:2 to YCbCr 4:2:0 color space conversion for all YCbCr input formats
– Cropping from 8192 x 8192 to any supported encoding size
– Rotation of 90 or 270 degrees
Mpixel.
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SPEAr1340 Device functions
2.24 Camera input interfaces (CAM)
The SPEAr1340 device integrates 4 instances of a camera input (CAM) digital block,
identified as CAM1, CAM2, CAM3, CAM4.
Each CAM interface enables SPEAr1340 to interface with an external image sensor. An
incoming image is stored in CAMIF memory per a programmed mode, and then transferred
to external memory using system direct memory access.
Main features:
● AMBA 2.0 compatible
● Slave interface with connection to external system DMA
● 8-bit parallel data interface
● YCbCr4:2:2, RGB888 packed, RGB888 un-packed, RGB565, JPEG mode
● Video mode with all running frame
● Compliant with ITU-R BT.601 (External synchronization) as well as ITU-R BT.656
(embedded synchronization)
● Image cropping
● Programmable polarity of pixel clock and external synchronization signals (HSYNCH,
VSYNCH)
Note: For 1080p 30 Hz video maximum pixel clock frequency for CAM required is
(2x2200x1125x30)=148.5
MHz.
2.25 Video input parallel port (VIP)
The video input parallel port is used to interface with some external image sensors.
Incoming images are stored inside its internal FIFO as per some programmed mode and
then transferred to the external memory through the master interface.
Main features:
● Supports HDMI, DVI, DP and CVBS
● Supports output format RGB along with HSYNC, VSYNC and pixel clock
● Clock polarity configuration provided (Positive edge/Negative edge)
● HSYNC and VSYNC polarity configurable
● Handling of data enable signal
● Dual-port display in DVI mode for 16 bpp and 24 bpp supported
● Input bit width 16 bpp, 24 bpp and 32 bpp supported
● Only unpacked data format supported
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Device functions SPEAr1340
2.26 I2S digital audio ports (I2S)
The I2S controller is a highly configurable IP for use in audio applications. It provides a
simple interface to standard audio components.
Main features:
● Compliant to Philips I2S serial bus specifications
● I2S master for output operations and I2S slave for input operations
● Configurable number of stereo channels (up to 4) for both transmitter and receiver
● Supports up to 7.1 audio Tx and Rx
● Supports 12-/16-/20-/24-/32-bit audio data interface
● Fully synchronous design with serial clock and system clock
● Interrupt support for reporting FIFO and other conditions
● Programmable FIFO thresholds
● Supports data exchange to the system memory through DMA interface
● Software controlled block resets and enables
● Software controlled FIFO flush
2.27 S/PDIF digital audio port
The S/PDIF audio interface detects bi-phase encoded S/PDIF signals, and plays PCM audio
data or audio encoded bit streams stored in memory in the S/PDIF format.
Main features:
Input
● Fully compliant with IEC-60958 for audio data
● Supports typical audio sampling frequencies, such as 32, 44.1, 48, 96, and 192 kHz.
● Programmable DMA trigger threshold
● VUCP storage can optionally be disabled
● Audio data can be stored in bit lengths of 16 to 24 bits
Output
● Compliant with IEC-60958 for audio data and IEC-61937 for compressed audio data
● Supports typical audio sampling frequencies such as 32, 44.1, 48, 96, and 192 kHz
● Supports one-bit audio mode (HDMI)
● Supports DTS-HD mode
● Programmable system DMA trigger limit
● Programmable VUCP insertion
● Supports 16/0 or 16/16 audio data format in memory
2.28 Keyboard controller (KBD)
The GPIO keyboard controller integrated in SPEAr1340 offers a 3-mode input and output
port. It provides an12-bit GPIO, or 6x6 keyboard, or 2x2 keyboard plus 8-bit GPIO, and
offers an interface to the industry standard APB bus.
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