SPEAr1340
Dual-core Cortex A9 HMI embedded MPU
Features
โ CPU subsystem:
โ2x ARM Cortex A9 cores, up to 600 MHz
โ32+32 KB L1 caches per core, with parity check
โShared 512 KB L2 cache
โAccelerator coherence port (ACP)
โ Network-on-chip bus matrix, up to 166 MHz
โ 32 KB Boot ROM, 32+4 KB Static RAMs
โ Memory interfaces:
โDDR controller (DDR3-1066, DDR2-1066 @533MHz), 16-/32-bit, up to 2 GB address space
โSerial NOR Flash controller
โParallel NAND Flash/NOR Flash/SRAM controller
โ Connectivity:
โ2 x USB 2.0 Host ports (integrated PHY)
โ1 x USB 2.0 OTG port (integrated PHY)
โ1 x Giga/Fast Ethernet port (external GMII/ RGMII/MII/RMII PHY)
โ1 x PCIe 2.0 RC/EP port (integrated PHY)
โ1 x 3Gb/s Serial ATA Host port (integrated PHY)
โ1 x memory card interface: SD/SDIO/MMC, CF/CF+, xD
โ2 x UART ports, with IrDA option
โ2 x I2C bus controllers, master/slave
โ1 x synchronous serial port, SPI/Microwire/TI protocols, master/slave
โ2 x consumer electronic control (HDMI CEC) ports
โ10-bit ADC: 8 ch. 1 Msps, with autoscan
โProgrammable bidirectional GPIO signals with interrupt capability
โ HMI support:
โLCD display controller, incl.support for Full HD, 1920 x 1080, 60 Hz, 24 bpp
Datasheet โ preliminary data
PBGA (23 x 23 mm) |
โHigh-perf. 2D/3D GPU, up to 1080p
โHardware video decoder: multistandard up to 1080p, JPEG
โHardware video encoder: H.264 up to 1080p, JPEG
โVideo input parallel port, with alternate configuration for 4 x camera interfaces
โDigital audio ports: up to 7.1 multichannel surround, I2S (8 in, 8 out) and S/PDIF
โ6 x 6 keyboard controller
โResistive touchscreen interface
โ Security:
โCryptographic co-processor: DES, 3DES, AES, HMAC, PKA, RNG
โSecure boot support
โJTAG disable option
โ Miscellaneous functions:
โEnergy saving: power islands, clock gating, dynamic frequency scaling
โ2 x DMA controllers (total 16 channels)
โ11 x general purpose timers, 2 x watchdogs,
1 x real-time clock
โ4 x PWM generators
โEmbedded sensor for junction temperature monitoring
โOTP (one-time programmable) bits
โDebug and trace interfaces: JTAG/PTM
Table 1. |
Device summary |
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Order code |
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Temp. |
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Packing |
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range, ยฐC |
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PBGA |
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SPEAr1340-2 |
-40 to 85 |
(23x23mm, |
Tray |
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pitch 0.8mm) |
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August 2012 |
Doc ID 023063 Rev 2 |
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www.st.com
Contents |
SPEAr1340 |
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Contents
1 |
Description . |
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Device functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.1 |
CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.2 |
Multilayer interconnect matrix (BUSMATRIX) . . . . . . . . . . . . . . . . . . . . . . . |
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2.3 |
Internal memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.3.1 |
BootROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.3.2 |
Static RAMs (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.4 |
Multiport DDR controller (MPMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.5 |
Serial NOR Flash controller (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.6 |
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . |
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2.7 |
USB 2.0 Host controllers (UHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.8 |
USB 2.0 OTG port (UOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.9 |
Giga/Fast Ethernet port (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.10 |
PCI Express controller (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.11 |
Serial ATA controller (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.12 |
SATA/PCIe physical interface (MiPHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.13 |
Memory card interfaces (MCIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.14 |
UART ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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I2C bus controllers (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.16 |
Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.17 |
A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.18 |
HDMI CEC interfaces (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.19 |
General purpose I/O (GPIO/XGPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.20 |
LCD display controller (CLCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.21 |
Graphics processing unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.22 |
Video decoder (VDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.23 |
Video encoder (VENC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Camera input interfaces (CAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.25 |
Video input parallel port (VIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.26 |
I2S digital audio ports (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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2.27 S/PDIF digital audio port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.28 Keyboard controller (KBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.29 Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.30 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.31 DMA controllers (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.32 General purpose timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.33 PWM generators (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.34 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.35 Reset and clock generator (RCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.36 Power control module (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.37 Temperature sensor (THSENS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.38 One-time programmable antifuse (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3.1 |
Pin map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3.2 |
Ball characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3.3 |
Power supply signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3.4 |
Multiplexed signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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3.4.1 MAC Ethernet port multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . 91 3.4.2 KBD multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.4.3 MCIF multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.4.4 FSMC multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.5 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.5.1 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.5.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.5.3 Clocks and resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.5.4 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.5.5 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.5.6 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.5.7 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 3.5.8 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.5.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.6 Strapping options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.1 |
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.2 |
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.3 |
Clocking parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.3.1 |
Master clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.3.2 |
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.4 |
I/O AC/DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.4.1 3V3/2V5/1V8 I/O buffers (IOTYPE1/IOTYPE2/IOTYPE3) . . . . . . . . . . 135 4.4.2 IOTYPE4 I/O buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.4.3 DDR2 and DDR3 mode I/O buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
4.5 Voltage regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.6 MiPHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.7 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.8 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.9 Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 4.10 Reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.1 |
Reset timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.2 |
ADC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3 |
ARM trace/JTAG timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.3.1 JTAG timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 5.3.2 ARM trace timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.4 CAM timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 5.5 CLCD timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.6 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.6.1 NAND Flash configuration timing characteristics . . . . . . . . . . . . . . . . . 153 5.6.2 NOR Flash configuration timing characteristics . . . . . . . . . . . . . . . . . . 155 5.6.3 SRAM configuration timing characteristics . . . . . . . . . . . . . . . . . . . . . 158
5.7 GMAC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.7.1 GMII transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.7.2 GMII receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.7.3 MII transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.7.4 MII receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.7.5MAC Ethernet asynchronous signals timing characteristics (MAC_CRS and MAC_COL) 163
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5.7.6MAC serial management channel timing characteristics (MDIO/MDC) 163
5.8 GPIO/XGPIO timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.9 I2C timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 5.10 I2S timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 5.11 MCIF timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.11.1 Synchronous mode (SD/SDIO/MMC) . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.11.2 CompactFlash true IDE PIO mode/UDMA mode . . . . . . . . . . . . . . . . . 170
5.12 MPMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.13 PWM timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.14 SMI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 5.15 SSP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.15.1 SPI master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 5.15.2 SPI slave mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.16 UART timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 5.17 VIP timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
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Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Appendix A |
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Appendix B |
Copyright statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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Description |
SPEAr1340 |
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The SPEAr1340 device is a system-on-chip belonging to the SPEArยฎ (Structured Processor Enhanced Architecture) family of embedded microprocessors. The product is suitable for consumer and professional applications where an advanced human machine interface (HMI) combined with high performance are required, such as low-cost tablets, thin clients, media phones and industrial/printer smart panels.
The device is hardware-compliant to the support of both real-time (RTOS) and high-level (HLOS) operating systems, such as Android, Linux and Windows Embedded Compact 7.
The architecture of SPEAr1340 is based on several internal components, communicating through a multilayer interconnection matrix (BUSMATRIX). This switching structure enables different data flows to be carried out concurrently, improving the overall platform efficiency.
In particular, high-performance master agents are directly interconnected with the DDR memory controller in order to reduce access latency. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal weighted round-robin (WRR) arbitration scheme.
Figure 1. SPEAr1340 architectural block diagram
JTAG Trace
Boot ROM
SRAMs
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Reset & clock Generator |
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THSENS |
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Power Control |
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Configuration |
DMA Ctrl (2x) |
Timers |
Security |
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registers |
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Co processor |
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Opt.
Battery
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The CPU subsystem is based on the ARM Cortex A9 processor, and has a dual-core configuration.
Main features:
Each core has the following features:
โARM v7 CPU at 600 MHz
โ32 KB of L1 instruction CACHE with parity check
โ32 KB of L1 data CACHE with parity check
โEmbedded FPU for single and double data precision scalar floating-point operations
โMemory management unit (MMU)
โARM, Thumb2 and Thumb2-EE instruction set support
โProgram Trace Macrocell (PTM) and CoreSightยฉ component for software debug
โ32-bit timer with 8-bit prescaler
โInternal watchdog (working also as timer)
The dual core configuration is completed by a common set of components:
โSnoop control unit (SCU) to manage inter-process communication, cache-to-cache and system memory transfer, cache coherency
โGeneric interrupt control (GIC) unit configured to support 128 independent interrupt sources with software configurable priority and routing between the two cores
โ64-bit global timer with 8-bit prescaler
โAccelerator coherence port (ACP)
โParity support to detect runtime failures for other internal memories
โ512 KB of unified 8-way set associative L2 cache with support for ECC
โL2 Cache controller based on PL310 IP released by ARM
โDual asynchronous 64-bit AMBA 3 AXI interface with possible filtering on the second one to use a single port for DDR memory access
โJTAG interface and Trace port: debug and trace can be inhibited through OTP
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Device functions |
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The multilayer interconnect matrix is the connectivity infrastructure that enables data exchange between the various blocks of the device. The BUSMATRIX supports parallel communications between master and slave components, and ensures the maximum level of system throughput.
Main features:
โHierarchical structure to meet the requirements of different system blocks and peripherals:
โhigh performance low latency
โhigh performance medium latency
โmedium performance medium/long latency
โslow peripherals and configurations
โPower awareness through the power down request/acknowledgement of the power management module
โSingle interrupt for outband signaling
SPEAr1340 integrates two embedded memories:
โ32 KB Boot ROM (BootROM)
โStatic RAM areas (SRAM)
BootROM refers to the on-chip 32 KB ROM as well as the booting firmware pre-stored in such memory. The supported booting devices are:
โSerial NOR Flash
โParallel NOR Flash
โNAND Flash
โUSB OTG
โUART
โSD/MMC
The BootROM firmware selects the booting device after reset by reading the status of the STRAP[3:0] pins.
A part of these memory areas is used during the bootstrap phase by BootROM firmware. After booting, all SRAM areas are fully available for general purpose applications.
Main features:
โ32 KB of system RAM (SYSRAM0, single port)
When all power islands are switched off, SYSRAM0 loses its data content.
โ4 KB of Always-on RAM (SYSRAM1, single port)
When all power islands are switched off, SYSRAM1 maintains its data content.
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MPMC is a high-performance multichannel memory controller able to support DDR2 and DDR3 memory devices. The multiport architecture ensures that memory is shared efficiently among different high-bandwidth client modules.
Main features:
โSupports both DDR3 and DDR2 devices; wide range of memory device cuts supported up to 2 GB (Note: 1)
โTwo chip selects supported
โProgrammable memory data path size of full memory 32-bit data width or half memory 16-bit data width
โClock frequencies from 100 MHz to 533 MHz supported
โ6 AXI interfaces with a data interface width of 64 bits. Each port is configured with a thread ID of 4 bits
โExclusive and locked accesses support
โWeighted round-robin arbitration scheme support to ensure high memory bandwidth utilization
โDRAM command processing
โRegister port with an AHB interface with a data interface width of 32 bits
โA programmable register interface to control memory device parameters and protocols including auto pre-charge
โFull initialization of memory on memory controller reset
โAutomatically maps user addresses to the DRAM memory in a contiguous block addressing starts at user address 0 and ends at the highest available address according to the size and number of DRAM devices present
โFully pipelined command, read and write data interfaces to the memory controller
โAdvanced bank look-ahead features for high memory throughput
Note: 1 When the 2GB address space is enabled, the ACP function is not available.
The serial NOR Flash controller integrated in SPEAr1340 acts as an AHB slave interface (32-, 16or 8-bit) to SPI-compatible off-chip memories. SMI allows the CPU to use these serial memories either as data storage or for code execution.
Main features:
โSupports a group of SPI-compatible Flash and EEPROM devices
โActs always as an SPI master and up to 2 SPI slave memory devices are supported (through as many chip select signals), with up to 16 MB address space each.
โThe SMI clock signal (smi_clk_o) is generated by SMI (and inputs to all slaves) using a clock provided by the AHB bus
โsmi_clk_o can be controlled by a programmable 7-bit prescaler allowing 127 different clock frequencies.
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The flexible static memory controller enables to interface external parallel Flash memories as well as static RAMs.
Main features:
โSupport for parallel NAND Flash:
โ8-bit or 16-bit data bus
โ2 chip select signals
โno limitation on NAND capacity (number of pages)
โhardware ECC (error correction code) support, correcting up to 8 errors per page (512 bytes wide)
โsupport for SLC (single-level cell) and MLC (multi-level cell) Flash devices, as far as compatible with available ECC features
โSupport for parallel NOR Flash:
โ8-bit or 16-bit data bus
โ26-bit address bus
โ2 chip select (CS) signals
โMaximum capacity is 64 MB for each CS, hence up to 128 MB with 2 external Flash devices
โSupport for asynchronous static RAMs (SRAMs):
โ8-bit or 16-bit data bus
โ26-bit address bus
โ2 chip select (CS) signals
โMaximum capacity is 64 MB for each CS, hence up to 128 MB with 2 external SRAM devices
โSupport for multiplexed NOR and SRAM
โWrite FIFO: 16 words depth, each word is 32 bits wide
โIndependent read/write timings and protocol, allowing matching the widest variety of memories and timings
โWait signal for timings handshake
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The SPEAr1340 device integrates 2 USB Host interfaces. Each interface provides a highspeed Host controller (EHCI standard) and a full-speed/low-speed controller (OHCI standard). The UHC has 2 physical ports (2 separate instances) that are fully compliant with the Universal Serial Bus specification (version 2.0), and provides an interface to the industry-standard AHB bus.
Main features:
โA PHY interface implementing a USB 2.0 transceiver macro-cell interface plus (UTMI+) fully compliant with UTMI+ specification (revision 1.0), to execute serialization and deserialization of transmissions over the USB line
โEither 30 MHz clock for 16-bit interface or 60 MHz for 8-bit interface supported by the UTMI + PHY interface
โA USB 2.0 host controller (UHC) connected to the AHB bus that generates the commands for the UTMI+PHY
โComplies with both the enhanced host controller interface (EHCI) specification (version 1.0) and the open host controller interface (OHCI) specification (version 1.0a)
โThe UHC supports the 480 Mbps high-speed (HS) for USB 2.0 through an embedded EHCI Host Controller, as well as the 12 Mbps full-speed (FS) and the 1.5 Mbps lowspeed (LS) for USB 1.1 through one integrated OHCI Host controller
โAll clock synchronization is handled within the UHC
โAn AHB slave for each controller (1 EHCI and 1 OHCI), acting as programming interface to access to control and status registers
โAn AHB master for each controller (1 EHCI and 1 OHCI) for data transfer to system memory, supporting 8-, 16-, and 32-bit wide data transactions on the AHB bus
โ32-bit AHB bus addressing
Main features:
โComplies with the On-The-Go supplement to the USB 2.0 specification (revision 1.3)
โSupports the Session Request Protocol (SRP)
โSupports the Host Negotiation Protocol (HNP)
โA PHY interface implementing the USB 2.0 transceiver macrocell interface (UTMI+ specification, revision 1.0 (Level 3)) to execute serialization and de-serialization of transmissions over the USB line
โUnidirectional and bidirectional 16-bit UTMI data bus interfaces
โSupport for the following speeds:
โHigh speed (HS): 480 Mbps
โFull speed (FS): 12 Mbps
โLow speed (LS): 1.5 Mbps (only in Host mode)
โBoth of the DMA and slave-only modes are supported
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The GMAC IP provides the capability to transmit and receive data over Ethernet.
Main features:
โSupports 10/100/1000 Mbps data transfer rates with the following PHY interfaces:
โIEEE 802.3-compliant GMII/MII interface (default) to communicate with an external Gigabit/Fast Ethernet PHY
โRGMII interface to communicate with an external gigabit PHY
โRMII interface (specification version 1.2 from RMII consortium) to communicate with an external Fast Ethernet PHY (for 10/100 Mbps operations only)
โFull-duplex operation:
โIEEE 802.3x flow control automatic transmission of zero-quanta pause frame on flow control input de-assertion
โOptional forwarding of received pause control frames to the user application
โHalf-duplex operation:
โCSMA/CD Protocol support
โFlow control using back-pressure support
โFrame bursting and frame extension in 1000 Mbps half-duplex operation
โAutomatic CRC and pad generation controllable on a per-frame basis
โProvides options for automatic pad/CRC stripping on receive frames
โSupports a variety of flexible address filtering modes, such as:
โUp to 31 48-bit SA address comparison check with masks for each byte
โ64-bit hash filter for multicast and unicast (DA) addresses
โOption to pass all multicast addressed frames
โPromiscuous mode support to pass all frames without any filtering for network monitoring
โPasses all incoming packets (per filter) with a status report
โProgrammable frame length to support standard or jumbo Ethernet frames with up to 16 KB of size
โProgrammable interframe gap (IFG) (40-96 bit times in steps of 8)
โSeparate 32-bit status for transmit and receive packets
โIEEE 802.1Q VLAN tag detection for reception frames
โSelf-managed DMA transfers with an internal DMA block
โSeparate transmission, reception, and control interfaces to the application
โThe host CPU uses a 32-bit AHB (AMBA 2.0) slave interface to access the GMAC subsystem control and status registers (CSRs)
โThe GMAC transfers data to system memory through a 32-bit AXI (AMBA 3.0) master interface
โSupport for network statistics with RMON/MIB counters (RFC2819/RFC2665)
โA module for detection of LAN remote wake-up frames and AMD magic packet frames: power management module (PMT)
โA receive module for checksum off-load for received IPv4 and TCP packets encapsulated by the Ethernet frame (Type 1)
โAn enhanced receive module for checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type 2)
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โAn enhanced module to calculate and insert IPv4 header checksum and TCP, UDP, or ICMP checksum in frames transmitted in store-and-forward mode.
โA module to support Ethernet frame time stamping as described in IEEE 15882002 and IEEE 1588-2008 (standard for precision networked clock synchronization). Sixty- four-bit time stamps are given in the transmit or receive status of each frame.
โMDIO master interface for PHY device configuration and management: station management agent (SMA), MDIO module
โSupports the standard IEEE P802.3az, version D2.0 for energy efficient Ethernet; allows physical layers to operate in the low-power idle (LPI) mode
The MAC transaction level (MTL) block consists of two sets of FIFOs: a transmit FIFO with programmable threshold capability, and a receive FIFO with a programmable threshold (default of 64 bytes). The MTL block has the following features:
โ32-bit transaction layer block that provides a bridge between the application and the GMAC
โSingle-channel transmit and receive engines
โSynchronization for all clocks in the design (transmit, receive, and system clocks)
โOptimization for packet-oriented transfers with frame delimiters
โFour separate ports for system-side and GMAC side transmission and reception
โFIFO instantiation outside the top-level module to facilitate memory testing/instantiation
โ4 KB receive FIFO size on reception
โSupports receive status vectors insertion into the receive FIFO after the EOF transfer. This enables multiple-frame storage in the receive FIFO without requiring another FIFO to store those frames
โConfigurable receive FIFO threshold (default fixed at 64 bytes) in cut-through or threshold mode
โProvides an option to filter all error frames on reception and not forward them to the application in store-and-forward mode.
โProvides an option to forward under-sized good frames
โSupports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the receive FIFO
โ2 KB FIFO size on transmission
โStore and forward mechanism for transmission to the GMAC
โThreshold control for transmit buffer management
โAutomatic retransmission of collision frames for transmission
โDiscards frames on late collision, excessive collisions, excessive deferral, and underrun conditions
โSoftware control to flush TX FIFO
The DMA block exchanges data between the MTL block and host memory. The host can use a set of registers (DMA CSR) to control the DMA operations. The DMA block supports the following features:
โ32-bit data transfers
โSingle-channel transmit and receive engines
โFully synchronous design operating on a single system clock (except for CSR module, when a separate CSR clock is configured)
โOptimization for packet-oriented DMA transfers with frame delimiters
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โByte-aligned addressing for data buffer support
โDual-buffer (ring) or linked-list (chained) descriptor chaining
โDescriptor architecture that allows large blocks of data transfer with minimum CPU intervention
โComprehensive status reporting for normal operation and transfers with errors
โIndividual programmable burst size for transmit and receive DMA engines for optimal host bus utilization
โProgrammable interrupt options for different operational conditions
โComplete per-frame transmit/receive interrupt control
โRound-robin or fixed-priority arbitration between receive and transmit engines
โStart/stop modes
โSeparate ports for host CSR access and host data interface
The GMAC audio video (AV) enables transmission of time-sensitive traffic over bridged local area networks (LANs). The GMAC AV has the following features:
โCompliant to IEEE 802.1-AS standard, version D6.0: specifies the protocol and procedures used to ensure that the synchronization requirements are met for timesensitive applications
โCompliant to IEEE 802.1-Qav standard, version D6.0: allows the bridges to provide time-sensitive and loss-sensitive real-time audio video data transmission (AV traffic). It specifies the priority regeneration and controlled bandwidth queue draining algorithms that are used in bridges and AV traffic sources
โSupports one additional channel (channel 1) on the transmit and receive paths for AV traffic in 100 Mbps and 1000 Mbps modes. The channel 0 is available by default and carries the legacy best-effort Ethernet traffic on the transmit side.
โSupports IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for the additional transmit channels
โProvides separate DMA, TxFIFO, and RxFIFO MTL for the additional channel (to avoid โhead of line blockingโ issues); the system-side interface remains the same.
The GMAC has the following additional features for monitoring, testing, and debugging:
โSupports internal loopback on the GMII/MII for debugging
โProvides DMA states (Tx and Rx) as status bits
โProvides debug status register that gives status of FSMs in transmit and receive datapaths and FIFO fill-levels
โApplication abort status bits
โMMC (RMON) module in the GMAC core
โCurrent Tx/Rx buffer pointer as status registers
โCurrent Tx/Rx descriptor pointer as status registers
โStatistical counters that help in calculating the bandwidth served by each transmit channel when AV support is enabled
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The PCI Express core incorporates a dual-mode (DM) core which can implement a PCIe interface for a PCIe Root Complex (RC) or Endpoint (EP). The dual-mode core can operate in EP or RC port modes, depending on value written in a register during PCIe configuration.
PCIe is compliant with the PCI Express Base 2.0 specification, but it is also compliant with the PCIe 1.1 specification.
The core features a proprietary user-configurable and high-performance application interface for generating and receiving PCIe traffic. It is available with standard AMBA 3 AXI interfaces.
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Typical applications for a PCI Express device built with the DM core include: |
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โ Motherboard components for desktop and mobile computers |
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โ Add-in cards for desktop and mobile computers |
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โ Components and add-in cards in server applications |
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Data communications equipment |
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The DM core in EP mode supports PCI Express Legacy Endpoint devices. However, the |
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the PCI Express Base 2.0 specification. |
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Main features (common to both EP and RC mode of the DM cores):
โSupport for all non-optional features and some optional features defined in the PCI Express Base 2.0 specification.
โUltra low transmit and receive latency
โSupport a max payload size of 256 bytes
โ4 KB maximum request size
โVery high accessible bandwidth
โSupport for both Gen1 (at 125 MHz) and Gen2 (at 250 MHz) operation
โ2.5 Gbps (Gen1) or 5.0 Gbps (gen2) Lane (x1)
โAutomatic lane reversal as specified in the PCI Express 2.0 specification (transmit and receive)
โPolarity inversion on receive
โMultiple virtual channels (VCs) (maximum of 2)
โMultiple traffic classes (TCs)
โECRC generation and checking
โPCI Express beacon and wake-up mechanism
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โPCI power management
โPCI Express active state power management (ASPM)
โPCI Express advanced error reporting
โVital product data (VPD)
โPCIe messages for both transmit and receive.
โExternal priority arbitration (in addition to the internally implemented transmit arbitration)
โExpansion ROM support
Additional features specific to RC mode
โType 1 configuration space
โApplication-initiated Lane reversal for situations where the core does not detect Lane 0 (for example, an x4 core connected to an x8 device that has its Lanes reversed)
Additional features specific to EP mode
โCompletion time-out ranges
โType 0 configuration space
โMSI interrupt capability
The SATA AHCI Core implements the serial advanced technology attachment (SATA) storage interface for physical storage devices.
Main features:
โSATA 3.0 Gb/s Gen II
โeSATA (external analog logic also needs to support eSATA)
โCompliant with the following specifications:
โSerial ATA 3.0 (except FIS-based switching)
โAHCI Revision 1.3 (except FIS-based switching)
โAMBA 3 AXI interfaces
โUser-defined PHY status and control ports
โRX data buffer for recovered clock systems
โData alignment circuitry when RX data buffer is also included
โOOB signaling detection and generation
โ8b/10b encoding/decoding
โAsynchronous signal recovery, including retry polling
โDigital support of device hot-plugging
โPower management features including automatic partial-to-slumber transition
โBIST loopback modes
โSingle SATA device
โInternal DMA engine per port
โHardware-assisted native command queuing for up to 32 entries
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โPort Multiplier with command-based switching
โDisabling RX and TX Data clocks during power down modes
โIntegrated SATA link layer and transport layer logic
โSupports PIO, first party and legacy DMA modes
โSupports legacy command queuing
โSupports ATA and ATAPI master-only emulation mode (for instance, register and command compatible with these standards)
โPower-down mode
โData scrambling
โCRC computation
โAutomatic data flow control
โFar end loop-back re-timed
The MiPHY macrocell implements the lower (physical) layer protocols providing data transmission and reception over a dual differential pair cable. The TX (transmit) and RX (receive) serial channels operate plesiochronously (NRZ). The macrocell can be used in Host or Device applications.
Main features:
โSerial transceiver (PHYsical layer) serializer and deserializer
โDirect support for 1.5/ 3.0 and 1.25/ 2.5/ 5.0 Gbit/s bit rates
โ20-bit parallel interface
โComma detect to provide word alignment of incoming serial stream
โSSC modulation
โIntegrated impedance adaptation to transmission line characteristics
โOut-of-band (OOB) signaling
โSupported 1.2 V and 2.5 V power supply
โHigh-performance PLL (input reference 100 MHz for PCIe and 100 or 25 MHz for SATA)
โProgrammable TX buffer pre-emphasis, slew-rate and amplitude
โDedicated TX buffer regulator for:
โTransmit buffer noise immunity
โBuffer level stability
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MCIF is a hardware IP that interfaces with the most common memory cards on the market:
โSD/SDIO 2.0
โSDHC
โCF/CF+ Rev 4.1
โMMC 4.2/4.3
โxD
The device interface multiplexes different memory cards on the same IOs; only one memory card is accessible at a given time. At the board level, discrete elements are required to handle host-swap management.
Main features:
SD/SDIO/MMC controller
โCompliant with:
โSD Host controller standard specification version 2.0
โSDIO card specification version 2.0
โSD memory card specification draft version 2.0
โSD memory card security specification version 1.01
โMMC specification version 3.31, 4.2 and 4.3
โAMBA specification AHB (version 2.0)
โData transfer with the system core through:
โPIO mode on the Host AHB slave interface
โDMA mode on the Host AHB master interface
โHost clock rate variable from 0 to 50 MHz
โMaximum data rate achievable:
โ200 Mbps (sd4 bit mode)
โ400 Mbps (mmc8 bit mode)
โData transfer:
โSD mode: 1 bit, 4 bit, and SPI mode
โMMC mode: 1 bit, 4 bit, 8 bit, and SPI mode
โCyclic redundancy check for commands (CRC7) and for data integrity (CRC16)
โVariable length data transfer
โRead wait control and suspend/resume operations supported
โWorks with IO cards, read-only cards and read/write cards
โSupports MMC Plus and MMC Mobile
โError correction code support for MMC 4.3 cards
โCard detection (insertion/removal)
โCard password protection
โTwo 4K FIFO to aid data transfer between the CPU and the controller
โFIFO overrun and underrun handled by stopping the SD clock
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CF/CF+ Host controller
โCF Specification Revision 4.1 compliance (True IDE Mode only)
โMultiword DMA to transfer data between the host and the CF/+ device
โUltra DMA mode for accessing the CF/+ card using the 16-bit data path
โPIO timing mode0 through mode6
โMultiword DMA timing mode0 through mode4
โUltra DMA timing mode0 through mode6
โData transfers up to 256 (512 byte) blocks
โVariable-length data transfer in multiword DMA and Ultra DMA modes
โInterrupt-driven data transfers in PIO mode
xD Host controller (Xtreme Digital)
โComfortable erase mechanism
โProgrammable access timing
โRead, write, erase, read device ID, status and reset commands
โECC generation and checking
โMultiblock programming and multiblock erase
โ1 Gbit, 2 Gbit support
The SPEAr1340 device integrates 2 instances of an asynchronous serial port (UART) digital block, identified as UART0 and UART1.
Asynchronous serial ports are responsible for performing the main tasks in serial communications with computers. The device converts incoming parallel information into serial data and incoming serial information into parallel data that can be sent on a communication line connected to an external peripheral device.
The SPEAr1340 embedded MPU provides two independent UART controllers. One of the typical uses of UART is connecting the SPEAr-based platforms to debugging consoles, the communication with modems and the interfacing of Bluetooth, DECT or ZigBee chipsets. The UART features inside SPEAr1340 offer similar functionality to the industry-standard 16C650 UART device.
UART ports usually do not directly generate or receive the external signals used between different items of equipment. External interface devices are used to convert the logic level signals of the UART to and from the external signaling levels. External signals may be of many different forms, such as RS-232, infrared and wireless radio. In particular, the UART interfaces inside SPEAr1340 directly support (by software selection) the IrDA-compliant Serial InfraRed (SIR) protocol.
The UART supports standard asynchronous communication bits (start, stop, and parity), which are added prior to transmission and removed on reception.
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Main features:
UART0 and UART1:
โSupport baud rate up to UARTCLK/16
โProgrammable baud rate generation (integer and fractional parts)
โSupport three options on the UARTCLK clock frequency:
โ48 MHz: maximum baud rate of 3 Mbps (48/16)
โ24 MHz: maximum baud rate of 1.5 Mbps (24/16)
โProgrammable by software: up to 125 MHz with a maximum baud rate of 7.81 Mbps (125/16).
โSeparate 16x8 transmit and 16x12 receive first-in, first-out memory buffers (FIFOs)
โProgrammable FIFO disabling for 1-byte depth
โFIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4 and 7/8
โIndependent masking of transmit FIFO, receive FIFO, receive time-out, and error condition interrupts
โSupport for direct memory access (DMA)
โFalse start bit detection
โLine break generation and detection
โProgrammable usage of IrDA SIR encoder/decoder: IrDA SIR ENDEC block provides:
โSupport of IrDA SIR ENDEC functions for data rates up to 115.2 Kbits/second half-duplex
โSupport of normal 3/16 and low-power bit durations
โProgrammable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration
โFully-programmable serial interface characteristics:
โdata can be 5, 6, 7, or 8 bits
โeven, odd, stick, or no-parity bit generation and detection
โ1 or 2 stop bit generation
UART0 only:
โProgrammable hardware flow control which uses the CTS input and the RTS output to automatically control the serial data flow
โSupport modem status which uses:
โInput signals: Clear To Send (CTS), Data Carrier Detect (DCD), Data Set Ready (DSR), and Ring Indicator (RI)
โOutput modem control lines: Request To Send (RTS), and Data Terminal Ready (DTR)
โIndependent masking of modem status
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The SPEAr1340 device integrates 2 instances of an I2C controller, identified as I2C0 and I2C1, which can be used to connect to the I2C bus peripheral.
Main features:
โCompliant to the I2C-bus specification from Philips
โThree different operating modes:
โStandard-speed mode (data rates up to 100 Kb/s)
โFast-speed mode (data rates up to 400 Kb/s)
โHigh-speed mode
โClock synchronization
โMaster or slave I2C operation mode
โMultimaster operation mode (bus arbitration)
โSupport for direct memory access (DMA)
โ7-bit or 10-bit addressing
โ7-bit or 10-bit combined format transfers
โSlave bulk transfer mode
โIgnores CBUS addresses (an older ancestor of I2C that used to share the I2C bus)
โBuffer transmission and reception
โInterrupt or polled-mode operation
โHandles bit and byte waiting at all bus speeds
โDigital filter for the received SDA and SCL lines
The synchronous serial port block includes a master or slave interface to enable synchronous serial communication with slave or master peripherals.
Main features:
โMaster or slave operation
โProgrammable clock bit rate and prescaler
โSeparate transmit and receive first-in, first-out memory buffers, 16-bit wide, 8 locations deep
โProgrammable choice of interface operation, SPI, Microwire, or TI synchronous serial
โProgrammable data frame size from 4 to 16 bits
โIndependent masking of transmit FIFO, receive FIFO, and receive overrun interrupts
โInternal loopback test mode available
โSupport for direct memory access (DMA)
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SPEAr1340 integrates an analog-to-digital converter.
Main features:
โSuccessive approximation A/D conversion
โ10-bit resolution for the analog cell which can be extended up to 12 bits with embedded oversampling techniques performed by the controller
โ1 MSPS
โ8 analog input channels (0 โ 2.5 V)
โINL ยฑ 1 LSB
โDNL ยฑ 1 LSB
โProgrammable conversion speed โ minimum conversion time 1 ยตs
โSupport for resistive touchscreen
The SPEAr1340 device integrates 2 instances of a Consumer Electronics Control (CEC) digital block, identified as CEC0 and CEC1.
CEC is an asynchronous transfer mode adaptation layer (AAL) protocol that provides highlevel control functions among the various audiovisual products in a userโs environment. CEC operates at low speeds, with minimal processing and memory overhead.
Main features:
โAMBA 2.0 compatible
โOne touch play: Play a device and make it the active source with the press of a button
โSystem standby: Set all devices to standby with the press of a button
โPreset transfer: Auto-configures device presets to match those of the TV
โOne-touch record: Enables one-button recording
โTimer programming: Any device can program a recording deviceโs timer
โSystem information: Devices can auto-configure their language and country settings
โDeck control: A device can control and interrogate a playback device
โTuner control: A device can control the tuner of another device
โVendor specific commands: Enables the use of vendor-defined commands
โOn-screen display (OSD): A device can display text on the TV screen
โDevice menu control: A device can control the menu of another device
โRouting control: Enables CEC switch control, to stream a new source device
โRemote control pass through: Enables the passing on of remote control commands to other devices
โDevice OSD name transfer: System devices can request the preferred object-based storage device (OSD) name of other system devices
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SPEAr1340 handles generic input/outputs in 3 ways. First, the device integrates 2 instances of a general purpose I/O (GPIO) digital block, identified as GPIOA and GPIOB. Second, an extended GPIO (XGPIO) feature is provided. Finally, it is possible to use the KBD controller in GPIO mode (this feature is documented in Section 2.28: Keyboard controller (KBD)).
The GPIO block provides 16 programmable inputs or outputs (8 for GPIOA and 8 for GPIOB). Each input/output can be controlled by software.
GPIO main features:
โ16 individually programmable input/output pins (by default input at reset)
โAn APB slave acting as control interface in software mode
โProgrammable interrupt generation capability on any number of pins
โBit masking in both read and writes operation through address lines
The XGPIOs are individually programmable input/output pins (by default output) that can be controlled through an AHB slave interface.
XGPIO main features:
โ234 individually programmable input/output pins: XGPIO0 to XGPIO7, and XGPIO24 to XGPIO249 (by default output). There is just an exception for the bit XGPIO169 which is always an output.
โProgrammable interrupt (rise or fall edge sensitive) generation on any number of pins
โAn AHB slave interface as control
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The TFT LCD controller provides all the necessary control signals to interface directly to a variety of TFT LCD panels.
Main features:
โWide range of programmable LCD panel resolutions
โSupport for 1 port TFT LCD panel interfaces:
โ18-bit digital (6-bit/color)
โ24-bit digital (8-bit/color) CMOS
โSupport for 2 Port TFT LCD panel interfaces (2nd port available by programmable signals)
โSupport for up to 2 overlay windows.
โProgrammable frame buffer bits-per-pixel (bpp) color depths:
โ1, 2, 4, 8 bpp mapped through the color palette to 18-bit LCD pixel
โup to 18 bpp directly drive 18-bit LCD pixel
โ24 bpp directly drive 24-bit LCD pixel
โColor Palette RAM to reduce Frame Buffer memory storage requirements bandwidth
โProgrammable output format support:
โRGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface
โRGB 8:8:8 on 24-bit digital interface
โProgrammable horizontal timing parameters:
โhorizontal front porch, back porch, sync width, pixels-per-line
โhorizontal sync polarity
โProgrammable vertical timing parameters:
โvertical front porch, back porch, sync width, lines-per-panel
โvertical sync polarity
โProgrammable pixel clock frequency up to 148MHz (1080p resolution)
โProgrammable data enable timing signal:
โderived from horizontal and vertical timing parameters
โdisplay enable polarity
โPower up and down sequencing support
โProgrammable endianness
โPulse width modulation for LCD panel LED backlight brightness control
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The Mali GPU is a hardware accelerator for 2D and 3D graphics systems that forms the basis of a high performance graphics processing solution. When implemented as part of a system-on-chip (SoC) device, the GPU forms an integral part of the graphics solution. The GPU comprises the following:
โan ARMยฎ Maliโข200 pixel processor
โa MaliGP2 geometry processor
โa memory management unit (MMU)
โassociated software (programmed using OpenVG or OpenGL base layers)
Main features (pixel processor):
โProgrammable fragment shader
โAccess to framebuffer from fragment shaders
โAlpha blending
โArbitrary memory reads and writes
โComplete non-power-of-2 texture support
โCube mapping
โDynamic recursion
โFast dynamic branching
โFast trigonometric functions, including arctangent
โFull floating-point arithmetic
โFramebuffer blend with destination Alpha
โHigh dynamic range (HDR) textures and framebuffers
โIndexable texture samplers
โLine, quad, triangle, and point sprites
โMultiple render targets
โNo limit on program length
โPerspective anisotropic filtering (AF)
โPerspective correct texturing
โPoint sampling, bilinear, and trilinear filtering
โProgrammable mipmap level-of-detail biasing and replacement
โRegister indirect jumps
โStencil buffering, 8-bit
โTwo-sided stencil
โUnlimited dependent texture reads
โVirtualized texture samplers
โ4-level hierarchical Z and stencil operations
โ4 times and 16 times full scene anti-aliasing (FSAA)
โ4-bit per texel texture compression.
Geometry processor
โProgrammable vertex shader
โAutonomous operation tile list generation
โFlexible input and output formats
โIndexed and non-indexed geometry input
โPrimitive constructions with points, lines, triangles and quads.
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Software
โCompatibility with the following graphics standards:
โOpenGL ES 2.0
โOpenGL ES 1.1
โOpenVG 1.0
The geometry processor must be programmed using OpenVG or Open GL base layers.
Main features:
โAll algorithms in hardware - minimal CPU load
โMinimal power consumption - functional level clock gating and synthesis time clock gating (> 90% of registers under gating)
Supported video codecs:
โH.264 profile and level
โBaseline, main and high profiles
โDecoding up to 1080p/30fps(1)
โScalable video coding (SVC):
โBaseline and high profiles (base layer only)
โMPEG-4 visual profile and level
โSimple and advanced simple profiles, levels 0 โ5(2)
โH.263 profile and level
โProfile 0, levels 10 โ70 (image size up to 720x576)
โSorenson Spark
โWMV9 / VC-1
โSimple, main and advanced profiles, levels 0 -3
โMPEG-1&2 main profile
โLow, medium and high levels
โRealVideo8/9/10
โDivXยฎ3/4/5/6 support
โHome theater profile qualification
โVP6, VP7 versions 0-3
โVP8 version 2 (WebM)
โAVS Jizhun Profile
โJPEG, all common sampling formats
โBaseline interleaved
1.Achievable resolution and frame rate depending on specific stream content and system load.
2.Global motion compensation (GMC) is not supported.
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Supported post-processing features:
โInput image source
โInternal source (combined mode): G1decoder
โExternal source (standalone mode): for example, a software decoder or camera interface
โInput image size
โCombined mode: 48 x 48 to 8176 x 8176 (66.8 Mpixels)
โStandalone mode: width from 48 to 8176, height from 48 to 8176 (maximum size limited to 16.7 Mpixels)
โOutput image size
โ16 x 16 to 1920 x 1088
โImage scaling
โBicubic polynomial interpolation for upscaling
โProprietary averaging filter for downscaling
โArbitrary, non-integer scaling ratio separately for both dimensions
โYCbCr to RGB color conversion
โBT.601-5 compliant
โBT.709 compliant
โUser definable conversion coefficient
โDithering
โ2x2 ordered spatial dithering for 4-, 5- and 6-bit RGB channel precision
โAlpha blending
โOutput image can be alpha blended with two rectangular areas
โDeinterlacing
โConditional spatial deinterlace filtering; supports only YCbCr 4:2:0 input format
โlinear RGB image contrast, brightness and color saturation adjustment
โDeblocking filter for MPEG-4 simple profile /H.263 / Sorenson
โUsing a modified H.264 in-loop filter as a postprocessing filter; filtering has to be performed in combined mode.
โImage cropping / digital zoom
โUser definable start position, height and width
โUsable only for JPEG or stand-alone mode
โOutput image masking
โImage rotation
โRotation 90, 180 or 270 degrees
โHorizontal/vertical flip
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A multiformat video encoder is integrated in SPEAr1340 with 64-bit AXI master and 32-bit AHB slave interfaces. It supports H.264 high profile video resolution up to 1080p and JPEG still picture up to 64 Mpixel.
Main features:
โH.264 profile and level
โBaseline, main and high profiles, levels 1- 4.0
โJPEG profile and level
โBaseline (DCT sequential)
โVideo stabilization
โI and P slices support
โCAVLC baseline and CABAC main profile
โError resilience
โConstrained intra prediction
โSlices, multiple of macro blocks rows
โMaximum motion vector length
โVertical ยฑ14 pixels
โHorizontal ยฑ30pixels
โ12 intra prediction modes
โMotion vector pixel accuracy
โ720p resolution ยผ pixels
โ1080p resolution ยฝ pixels
โMacroblock and sub-macroblock partitions: 16x16, 8x16, 16x8, 8x8, 4x8, 8x4,4x4
โTransforms 4x4 baseline, main and high profiles
โ1 reference frame support
โMaximum 1 slice group support
โInput data formats
โPlanar YCbCr 4:2:0, semiplanar YCbCr 4:2:0, interleaved YCbCr 4:2:2
โOutput data formats
โH.264 (Byte and NAL unit stream)
โJPEG( JFIF file format 1.02 and non progressive JPEG)
โSupported image size
โH.264: 96x96 to1920x1020
โJPEG: 96x96 to 8192x8192
โStep size 4 pixels
โPre-processing features
โYCbCr 4:2:2 to YCbCr 4:2:0 color space conversion for all YCbCr input formats
โCropping from 8192 x 8192 to any supported encoding size
โRotation of 90 or 270 degrees
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The SPEAr1340 device integrates 4 instances of a camera input (CAM) digital block, identified as CAM1, CAM2, CAM3, CAM4.
Each CAM interface enables SPEAr1340 to interface with an external image sensor. An incoming image is stored in CAMIF memory per a programmed mode, and then transferred to external memory using system direct memory access.
Main features:
โAMBA 2.0 compatible
โSlave interface with connection to external system DMA
โ8-bit parallel data interface
โYCbCr4:2:2, RGB888 packed, RGB888 un-packed, RGB565, JPEG mode
โVideo mode with all running frame
โCompliant with ITU-R BT.601 (External synchronization) as well as ITU-R BT.656 (embedded synchronization)
โImage cropping
โProgrammable polarity of pixel clock and external synchronization signals (HSYNCH, VSYNCH)
Note: |
For 1080p 30 Hz video maximum pixel clock frequency for CAM required is |
ย |
(2x2200x1125x30)=148.5 MHz. |
The video input parallel port is used to interface with some external image sensors. Incoming images are stored inside its internal FIFO as per some programmed mode and then transferred to the external memory through the master interface.
Main features:
โSupports HDMI, DVI, DP and CVBS
โSupports output format RGB along with HSYNC, VSYNC and pixel clock
โClock polarity configuration provided (Positive edge/Negative edge)
โHSYNC and VSYNC polarity configurable
โHandling of data enable signal
โDual-port display in DVI mode for 16 bpp and 24 bpp supported
โInput bit width 16 bpp, 24 bpp and 32 bpp supported
โOnly unpacked data format supported
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The I2S controller is a highly configurable IP for use in audio applications. It provides a simple interface to standard audio components.
Main features:
โCompliant to Philips I2S serial bus specifications
โI2S master for output operations and I2S slave for input operations
โConfigurable number of stereo channels (up to 4) for both transmitter and receiver
โSupports up to 7.1 audio Tx and Rx
โSupports 12-/16-/20-/24-/32-bit audio data interface
โFully synchronous design with serial clock and system clock
โInterrupt support for reporting FIFO and other conditions
โProgrammable FIFO thresholds
โSupports data exchange to the system memory through DMA interface
โSoftware controlled block resets and enables
โSoftware controlled FIFO flush
The S/PDIF audio interface detects bi-phase encoded S/PDIF signals, and plays PCM audio data or audio encoded bit streams stored in memory in the S/PDIF format.
Main features:
Input
โFully compliant with IEC-60958 for audio data
โSupports typical audio sampling frequencies, such as 32, 44.1, 48, 96, and 192 kHz.
โProgrammable DMA trigger threshold
โVUCP storage can optionally be disabled
โAudio data can be stored in bit lengths of 16 to 24 bits
Output
โCompliant with IEC-60958 for audio data and IEC-61937 for compressed audio data
โSupports typical audio sampling frequencies such as 32, 44.1, 48, 96, and 192 kHz
โSupports one-bit audio mode (HDMI)
โSupports DTS-HD mode
โProgrammable system DMA trigger limit
โProgrammable VUCP insertion
โSupports 16/0 or 16/16 audio data format in memory
The GPIO keyboard controller integrated in SPEAr1340 offers a 3-mode input and output port. It provides an12-bit GPIO, or 6x6 keyboard, or 2x2 keyboard plus 8-bit GPIO, and offers an interface to the industry standard APB bus.
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