ST SPEAr1310 User Manual

Dual-core Cortex A9 embedded MPU for communications

Features

■ CPU subsystem:

– 2x ARM Cortex A9 cores, up to 600 MHz
– Supporting both symmetric (SMP) and

asymmetric (AMP) multiprocessing

– 32+32 KB L1 Instructions/Data cache per

core with parity check

– Shared 512 KB L2 cache (ECC protected)

with parity check

– Accelerator coherence port (ACP)

■ Bus: 64-bit multilayer network-on-chip

■ Memories:

– 32 KB BootROM
– 32 KB internal SRAM
– Multi-port controller (MPMC) for external

DDR2-800/DDR3-1066 with 16/32 bits
datapath, up to 1GB addressable with ECC
option for SEC/DED

– Controller (FSMC) for external NAND

Flash, parallel NOR Flash and
asynchronous SRAM

– Controller (SMI) for external serial NOR

flash

■ Connectivity:

– 2x Giga/Fast Ethernet ports (for external

GMII/RGMII/MII PHY)

– 3x Fast Ethernet (for external SMII/RMII

PHY)
– 3x PCIe 2.0 links (embedded PHY)
– 3x SATA gen-2 host port
– 1x 32-bit PCI expansion bus (up to 66 MHz)
– 2x USB 2.0 host ports with integrated

PHYs
– 1x USB2.0 OTG port with integrated PHY
– 2x CAN 2.0 a/b interfaces
– 2x TDM/E1 HDLC controllers with 256/32

time slots per frame respectively
– 2x HDLC controllers for external RS485

PHYs

SPEAr1310

Data brief

PBGA (23 x 23 mm)

– 2x I2S ports for external audio/modem
– 6x UARTs (up to 5 Mbaud)
– 1x SSP port (SPI and other protocols),

master/slave, up to 41 Mbps

– 2x I2C ports master/slave

■ Integrated support for external peripherals:

– TFT LCD controller, up to 1920 x 1200 (60

Hz), 24 bpp
– Touchscreen I/F (4-wire resistive)
– 9 x 9 keyboard controller
– Memory card interface (MCIF) supporting

SD/SDIO 2.0, SDHC, MMC 4.2/4.3,

CF/CF+ Rev 4.1, XD

■ Expansion interface (EXPI)

■ Security: C3 cryptographic accelerator

■ 13x timers and 1x real time clock

■ Miscellaneous functions:

– 2x high-performance 8-channels DMA

controllers
– JPEG HW codec
– 10 bit ADC, up to 1 Msps, 8 inputs with

autoscan capability
– Programmable bidirectional GPIO signals

with interrupt capability
– 510 + 209 one time programmable (OTP)

bits
– Embedded sensor for junction temperature

monitoring
– JTAG-PTM (debugging and test interface)

■ Power saving features:

– Power islands for leakage reduction
– IP clock gating for dynamic power reduction
– Dynamic frequency scaling

September 2010 Doc ID 17528 Rev 4 1/57

For further information contact your local STMicroelectronics sales office.

www.st.com

1

Contents SPEAr1310

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Multilayer interconnect matrix (BUSMATRIX) . . . . . . . . . . . . . . . . . . . . 11

2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 CortexA9 subsystem (A9SM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Reset and clock generator (RCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Power control module (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 BootROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8 Static RAM (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9 Multiport memory controller (MPMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . 19

10.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

11 Serial memory interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

12 Giga/Fast Ethernet media access controller (GMAC) . . . . . . . . . . . . . 21

12.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

13 PCI Express (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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SPEAr1310 Contents

13.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

14 SATA gen-2 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

14.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

15 PCIe/SATA physical interface (MiPHY) . . . . . . . . . . . . . . . . . . . . . . . . . 28

16 32-bit PCI expansion bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

17 USB Host controller (UHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

17.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

18 USB On-The-Go controller (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

18.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

19 Controller area network interfaces (CAN) . . . . . . . . . . . . . . . . . . . . . . . 32

19.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

20 TDM/E1 HDLC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

20.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

21 RS485 HDLC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

21.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

22 Inter-IC sound controller (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

22.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

23 Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . 37

23.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

24 Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

24.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

25 I2C controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

25.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Contents SPEAr1310

26 TFT LCD controller (CLCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

26.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

27 Keyboard controller (KBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

27.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

28 Memory card interface (MCIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

28.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

29 Expansion interface (EXPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

29.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

30 Security co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

30.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

31 One-time programmable antifuse (OTP) . . . . . . . . . . . . . . . . . . . . . . . . 47

31.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

32 General purpose timer (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

32.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

33 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

33.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

34 Direct memory access controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . 50

34.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

35 JPEG Codec (JPGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

35.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

36 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

36.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

37 General purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . 54

37.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

38 Temperature sensor (THSENS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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SPEAr1310 Contents

38.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Doc ID 17528 Rev 4 5/57

Description SPEAr1310

1 Description

The SPEAr1310 is a member of the SPEAr family of embedded MPUs for network devices.

It offers an unprecedented combination of processing performance and aggressive power
reduction control for next-generation communication appliances.

The SPEAr1310 is based on ARM's new multi-core technology (Cortex-A9 SMP/AMP) and it
is manufactured with ST's 55nm HCMOS low power silicon process.

SPEAr1310 targets cost and power sensitive networking applications for the home and
small business as well as telecom infrastructure equipment, with lowest overall leakage
under real operating conditions. The device integrates ARM's latest generation ARMv7 CPU
cores, ST's proven C3 security coprocessor, and advanced connectivity interfaces and
controllers.

Figure 1. SPEAr1310 system connectivity

Serial

NOR

Flash

NAND/NOR

DDR2/3 RAM

Mass

Storage

Parallel

Flash

Memory

Card

FE/GE

PHYs

TFT Display

SMI

FSMC

MPMC

3x SATA

MCIF

3x FE MAC
2x GE MAC

LCD

Keypad

KBD 2x I2S

SPEAr1310

4x HDLC

(TDM/E1/RS485)

Audio I/O

Frontend

6x UART

Audi o

2x I2C

2x CAN

SPI Peripherals

SSP

USB OTG

2x USBH

3x PCIe

PCI

ADC

EXPI

GPIO

JTAG

USB Host or

Peripheral

USB Peripherals

PCIe
Cards /
Modules

PCI Cards

Analog

Sources

FPGA

Any device

Power

Supply

Add title on master page

LAN/WAN

Telecom

Equipment

Add subtitle on master page

The SPEAr1310 internal architecture is based on several shared subsystem logic blocks
that are interconnected through a multilayer interconnection matrix (the BUSMATRIX). The
switch matrix structure allows different subsystem data flows to be executed in parallel
improving the core platform efficiency.

High performance master agents are directly interconnected with the memory controller to
reduce memory access latency. The overall memory bandwidth assigned to each master

6/57 Doc ID 17528 Rev 4

Terminals

CAN Network

Test &

Debug

SPEAr1310 Description

port can be programmed and optimized through an internal, weighted round-robin (WRR)
arbitration scheme.

Figure 2 is the internal connectivity block diagram.

Figure 2. SPEAr1310 block diagram of the internal connectivity

A9 Subsystem Module

PTM

FPU

I/F

A9 CPU

Instr

Data

Cache

Cache

cache2cache

transfers

SCU

L2 cache

CoreSight Subsystem

G

I

C

Temp. sensor (THSENS)

OTP memory

Power management

32 KB BootROM

32 KB RAM

Reset and clock

control

FSMC

Flash/SRAM controller

Snoop

filtering

FPU

A9 CPU

Instr

Cache

Timers

PTM

Data

Cache

LCD display

controller

FI/

2x Giga/Fast Ethernet

3x Fast Ethernet

A
C
P

3x PCIe

3x SATA

PCI 32-bit @ 66 MHz

Network-on-chip

1x USB OTG

2x UHC

USB Host controller

2x HDLC (TDM/E1)

2x HDLC (RS485)

EXPI

MCIF

Expansion interface

Memory card interface

2x DMAC

SMI

Serial memory interface

C3

Crypto accelerator

MPMC

DDR2/3 controller

KBD

2x I2S

RTC

2x CAN

6x UART

SSP

2x I2C

ADC

keyboard

JPEG

Codec

GPIO

MISC

Doc ID 17528 Rev 4 7/57

Description SPEAr1310

Ta bl e 1 provides an overview of SPEAr1310 features and capabilities.

Table 1. SPEAr1310 features and capabilities overview

Category Feature Instances / Details Notes

Processor
cores

CPU subsystem

L2 Cache

Debug & test

Interconnect Internal bus

Reset and clock

RCG
generator

2x
Cortex A9@600 MHz

32+32 KB L1 per core

1x
512 KB ECC

2x
JTAG-PTM

1x
64 bit @ 166 MHz

1x

Configuration MISC 1x

Includes:
– 1x 64-bit global timer
– 2x 32-bit timers
– 2x watchdog/timers

Network-on-chip

Reset and clock
generation module

Miscellaneous SoC
configuration registers

Power management PCM 1x Power control module

BootROM

SRAM

1x
32 KB

2x
32 KB + 4 KB

On-chip ROM for boot
firmware

Static RAM

1x

MPMC

Memories

up to 1 GB
DDR2: 400 MHz + ECC

DDR3: 533 MHz + ECC

DDR 2/3 controller

1x

FSMC

16-/32-bit
Parallel NAND/NOR Flash

1x

SMI

4x 16 MB C.S.@50Mbps
Serial NOR Flash

8/57 Doc ID 17528 Rev 4

Parallel Flash controller

SPI Flash controller

SPEAr1310 Description

Table 1. SPEAr1310 features and capabilities overview (continued)

Category Feature Instances / Details Notes

Connectivity

Ethernet

MIPHY

PCIe

SATA

2x Giga
3x Fast (see Tab l e 2 )

3x PHYs
(single + dual macro)

3x
root complex/endpoint

3x
gen.2

MAC controllers

PHYs for PCIe and SATA

PCIe controllers

SATA controllers

1x

PCI

32 bit @ 66 MHz

Legacy PCI bus controller

host/device

USB

CAN bus

HDLC

2x USB2.0 Host
1x USB2.0 OTG

2x
CAN2.0 a/b

2x TDM/E1
2x RS485

USB controllers with
PHYs

CAN controllers

HDLC controllers

I2S 2x Digital audio

UART 6x Async. serial ports

SSP/SPI 1x

Sync. serial port
(master/slave)

I2C 2x I2C bus (master/slave)

TFT LCD
controller

Integrated support
for external
peripherals

Keyboard
controller

Memory card
interfaces

Expansion EXPI

1x
24bpp, 1920x1200 @ 60 fps +

PWM

1x
9x9 matrix

1x SD/SDIO 2.0/SDHC/MMC 4.x
1x CF/CF+ Rev 4.1, XD

1x
32 bit AHB like @83 MHz

1x
DES, 3DES, AES

C3

Security

OTP

univ. hashing
SHA1/2, MD5, HMAC
PKA, True_RNG

1x
510+209

Cryptography accelerator

One-time programmable
antifuse

Doc ID 17528 Rev 4 9/57

Description SPEAr1310

Table 1. SPEAr1310 features and capabilities overview (continued)

Category Feature Instances / Details Notes

GPT

4x
(total 8 timers)

RTC 1x Real-time clock

2x
(total 16 channels)

1x
8 channels x 10bit, 1Msps

2x
(total 16 I/O)

Other

DMAC

JPEG Codec 1x JPEG encoder/decoder

ADC

GPIO

THSENS 1x Temperature sensor

Table 2. MAC Phy interfaces available

MAC controller Rate Interfaces

GE (1 Gbps) GMII / RGMII

MAC1

FE (10/100 Mbps) MII / RMII

MAC2 GE (1 Gbps) RGMII

MAC3 FE (10/100 Mbps) SMII / RMII

MAC4 FE (10/100 Mbps) SMII / RMII

General purpose timers

DMA controller

A/D converter
Also used for touchscreen

I/F

General-purpose I/O

MAC5 FE (10/100 Mbps) SMII / RMII

10/57 Doc ID 17528 Rev 4

SPEAr1310 Multilayer interconnect matrix (BUSMATRIX)

2 Multilayer interconnect matrix (BUSMATRIX)

The multilayer interconnect matrix is the connectivity infrastructure that enables data
exchange between the various blocks of the device. This structure supports parallel
communications between master and slave components, and ensures the maximum level of
system throughput.

Note: In this document, the words initiator agent (IA) and master are synonyms ; target agent (TA)

and slave are synonyms.

2.1 Main features

● Hierarchical structure to meet the requirements of different system blocks and

peripherals:

– High performance low latency

– High performance medium latency

– Medium performance medium/long latency

– Slow peripherals and configurations

● Power awareness through the power down request/acknowledgement of the power

management module

● Single interrupt for outbound signaling

Doc ID 17528 Rev 4 11/57

CortexA9 subsystem (A9SM) SPEAr1310

3 CortexA9 subsystem (A9SM)

The CPU subsystem is based on the ARM Cortex A9 processor, and has a dual core
configuration.

3.1 Main features

Each core has the following features:

● ARM v7 CPU at 600 MHz

● 32 KB of L1 instruction CACHE with parity check

● 32 KB of L1 data CACHE with parity check

● Embedded FPU for single and double data precision scalar floating-point operations

● Memory management unit (MMU)

● ARM, Thumb2 and Thumb2-EE instruction set support

● TrustZone© security extension

● Program Trace Macrocell and CoreSight© component for software debug

● JTAG interface

● AMBA© 3 AXI 64-bit interface

● 32-bit timer with 8-bit prescaler

● Internal watchdog (working also as timer)

The dual core configuration is completed by a common set of components:

● Snoop control unit (SCU) to manage inter-process communication, cache-2-cache and

system memory transfer, cache coherency

● Generic interrupt control (GIC) unit configured to support 128 independent interrupt

sources with software configurable priority and routing between the two cores

● 64-bit global timer with 8-bit prescaler

● Asynchronous accelerator coherency port (ACP)

● Parity support to detect internal memory failures during runtime

● 512 KB of unified 8-way set associative L2 cache with support for parity check and

ECC

● L2 Cache controller based on PL310 IP released by ARM

● Dual 64-bit AMBA 3 AXI interface with possible filtering on the second one to use a

single port for DDR memory access

12/57 Doc ID 17528 Rev 4

SPEAr1310 Clock and reset system

4 Clock and reset system

This centralized structure provides system synchronization and includes the following
features:

● Six PLLs. Four of them are fully programmable and offer an EMI reduction mode

(spread spectrum clock generation through dithering) that can replace all traditional
EMI reduction techniques.

– PLL1 programmable dithered pll, dedicated for Core1 & 2 & AXI/AHB bus &

peripherals. Both core need to run at the same speed

– PLL2 programmable dithered PLL, dedicated for the 125 MHz clock of the Gigabit

Ethernet MACs

– PLL3 programmable dithered PLL, for specific embedded IP functions

– PLL4 programmable dithered PLL, dedicated for the DDR memory controller

(Asynchronous access memory mode)

– PLL5 low jitter, dedicated for the USB

– PLL6 for the PCIe controllers

● Several synthesizers provide different frequencies for different IPs

● Fully programmable control of clock and reset signals for all slave blocks allowing

sophisticated power management.

Doc ID 17528 Rev 4 13/57

Reset and clock generator (RCG) SPEAr1310

5 Reset and clock generator (RCG)

The reset and clock generator (RCG) provides the system clocks and resets. It is highly
configurable through the miscellaneous registers.

5.1 Main features

● Three main clock sources:

– osci1: 24 MHz clock coming from internal oscillator connected to external quartz.

– osci2: 32 kHz clock coming from internal oscillator used for RTC block (optional)

– osci3: 25/100 MHz clock coming from MIPHY macro (optional).

● Three programmable dithered PLLs (to reduce EMI):

– PLL1: primarily used to generate the 1 GHz clock for the AMBA subsystem

– PLL2, PLL3: primarily used to generate clocks for RAS logic and generic IPs

● Seven configurable clock generators:

– SSCG1-4: dedicated to RAS logic

– SSCG5: for CLCD clock

– SSCG6: for EXPI clock

– SSCG7: for AMBA system clocks

● Three operating modes for AMBA clocks:

– DOZE: the clock source is osci2 (osci1 after power on)

– SLOW: the clock source is the osci1 or a divided version

– NORMAL: the clock source is PLL1 (by default), PLL2, PLL3 or SSCG7

● Configurable clock gating and software reset for most peripherals

● Global software reset and watchdog reset

14/57 Doc ID 17528 Rev 4

SPEAr1310 Power control module (PCM)

6 Power control module (PCM)

PCM is the core of the SPEAr1310 leakage power management system. Its role is to
properly manage the power supply shutoff of the switchable sections of the embedded MPU.

6.1 Main features

● Generation of supply switch control signals for SPEAr1310 power islands

● Generation of isolation control signals for SPEAr1310 power islands

● Generation of shutoff commands for external DDR 1V2 and 1V5/1V8 supply lines

● Acknowledge generation for user requested power island configuration

● Monitoring of voltage detector outputs for each power island

● Wake-up source management

Doc ID 17528 Rev 4 15/57

BootROM SPEAr1310

7 BootROM

The term BootROM refers to the on-chip 32 KB ROM as well as the booting firmware pre­stored in such memory. Supported booting devices are:

● Serial NOR Flash

● Parallel NOR Flash

● NAND Flash

● I2C EEPROM

● PCIe

● USB Device

● UART

The BootROM firmware selects the booting device after reset by reading the status of the
STRAP[3:0] pins.

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SPEAr1310 Static RAM (SRAM)

8 Static RAM (SRAM)

SPEAr1310 has internal static RAM (SRAM) areas. A part of these memory areas is used
during the bootstrap phase by BootROM firmware. After booting, all SRAM areas are fully
available for general purpose applications.

8.1 Main features

● 4 KB of Always-on RAM (SYSRAM1, single port)

When all of the power islands are switched off, SYSRAM1 maintains its data content.

● 32 KB of system RAM (SYSRAM0, single port)

When all of the power islands are switched off, SYSRAM0 loses its data content.

Doc ID 17528 Rev 4 17/57

Multiport memory controller (MPMC) SPEAr1310

9 Multiport memory controller (MPMC)

MPMC is a high performance multichannel memory controller able to support DDR2 and
DDR3 double data rate memory devices. The multiport architecture ensures that memory is
shared efficiently among different high-bandwidth client modules.

9.1 Main features

● Supports both DDR3 and DDR2 devices. Wide range of memory device cuts

supported: from 128 Mb to 4 Gb for each chip select. Two chip selects supported.

● Programmable memory datapath size of full memory 32-bit data width or half memory

16 bits data width

● Clock frequencies from 100 MHz to 533 MHz supported

● 6 AXI interfaces with a data interface width of 64 bits. Each port is configured with a

thread ID of 4 bits

● Exclusive and locked accesses support Weighted Round-Robin arbitration scheme

support to ensure high memory bandwidth utilization

● DRAM command processing

● Register port with an AHB Interface with a data interface width of 32 bits

● A programmable register interface to control memory device parameters and protocols

including auto pre-charge

● Full initialization of memory on memory controller reset

● Automatically maps user addresses to the DRAM memory in a contiguous block

addressing starts at user address 0 and ends at the highest available address
according to the size and number of DRAM devices present

● Fully pipelined command, read and write data interfaces to the memory controller

● Advanced bank look-ahead features for high memory throughput

● 7-bit ECC functionality with single-bit and double-bit error reporting and automatic

correction of single-bit error events. Programmable reporting and correction.
Programmable removal of ECC storage

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