SPC560B40x, SPC560B50x
SPC560C40x, SPC560C50x
32-bit MCU family built on the Power Architecture® for automotive body electronics applications
Features
■High-performance 64 MHz e200z0h CPU
–32-bit Power Architecture® technology
–Up to 60 DMIPs operation
–Variable length encoding (VLE)
■Memory
–Up to 512 Kbytes Code Flash, with ECC
–64 Kbytes Data Flash, with ECC
–Up to 48 Kbytes SRAM, with ECC
–8-entry memory protection unit (MPU)
■Interrupts
–16 priority levels
–Non-maskable interrupt (NMI)
–Up to 34 ext. int. including 18 wakeup lines
■GPIO: LQFP64/45, LQFP100/75, LQFP144/123
■Timer units
–6-channel 32-bit periodic interrupt timers
–4-channel 32-bit system timer module
–System watchdog timer
–Real-time clock timer
■16-bit counter time-triggered I/Os
–Up to 56 channels with PWM/MC/IC/OC
–ADC diagnostic via CTU
■Communications interface
–Up to 6 FlexCAN interfaces (2.0B active) with 64-message objects each
–Up to 4 LINFlex/UART
–3 DSPI / I2C
Table 1. Device summary
LQFP100 (14 x 14 x 1.4 mm)
LQFP64 (10 x 10 x 1.4 mm)
LQFP144 (20 x 20 x 1.4 mm)
■10-bit A/D converter with up to 36 channels
–Up to 64 channels via external multiplexing
–Individual conversion registers
–Cross triggering unit
■Dedicated diagnostic module for lighting
–Advanced PWM generation
–Time-triggered diagnostic
–PWM-synchronized ADC measurements
■Clock generation
–4 to 16 MHz fast external crystal oscillator
–32 KHz slow external crystal oscillator
–16 MHz fast internal RC oscillator
–128 kHz slow internal RC oscillator
–Software-controlled FMPLL
–Clock monitoring unit
■Exhaustive debugging capability
–Nexus1 on all devices
–Nexus2+ available on emulation package
■Low power capabilities
–Ultra-low power standby with RTC, SRAM and CAN monitoring
–Fast wakeup schemes
■Operating temp. range up to -40 to 125 °C
■Single 5 V or 3.3 V supply
Package |
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Part number |
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256 KB code Flash memory |
512 KB code Flash memory |
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LQFP144 |
SPC560B40L5 |
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SPC560B50L5 |
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LQFP100 |
SPC560B40L3 |
SPC560C40L3 |
SPC560B50L3 |
SPC560C50L3 |
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LQFP64(1) |
SPC560B40L1 |
SPC560C40L1 |
SPC560B50L1 |
SPC560C50L1 |
1. All LQFP64 information is indicative and must be confirmed during silicon validation.
October 2011 |
Doc ID 14619 Rev 9 |
1/117 |
www.st.com
Contents |
SPC560B40x/50x, SPC560C40x/50x |
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Contents
1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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1.1 |
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
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1.2 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
8 |
2 |
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
11 |
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3 |
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . |
14 |
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3.1 |
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
14 |
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3.2 |
Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . |
17 |
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3.3 |
Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
18 |
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3.4 |
Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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3.5 |
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
19 |
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3.6 |
Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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3.7 |
Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
42 |
4 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
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4.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
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4.2 |
Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
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4.3 |
NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
4.3.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 44 4.3.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 44
4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.5 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.6.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.7 |
I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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4.7.1 |
I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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4.7.2 |
I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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4.7.3 |
I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
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4.7.4 |
Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
54 |
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4.7.5 |
I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
54 |
2/117 |
Doc ID 14619 Rev 9 |
SPC560B40x/50x, SPC560C40x/50x |
Contents |
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4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.9 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 63
4.9.1 |
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . |
63 |
4.9.2 |
Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . |
68 |
4.10 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.11 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.11.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.11.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.12 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . |
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4.12.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . |
73 |
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4.12.2 |
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
74 |
4.12.3 |
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . |
74 |
4.13Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 75
4.14 |
Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . |
78 |
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4.15 |
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
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4.16 |
Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . |
81 |
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4.17 |
Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . |
82 |
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4.18 |
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
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4.18.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.18.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4.18.3 |
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.19.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.19.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5 |
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
101 |
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5.1 |
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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5.2 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
101 |
5.2.1 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.2.2 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.2.3 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Doc ID 14619 Rev 9 |
3/117 |
Contents |
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SPC560B40x/50x, SPC560C40x/50x |
6 |
Ordering information . . . . . . . . . . . . . . . . |
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Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . |
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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4/117 |
Doc ID 14619 Rev 9 |
SPC560B40x/50x, SPC560C40x/50x |
List of tables |
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. SPC560B40x/50x and SPC560C40x/50x device comparison . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary . . . . . . . . . . . . . . . . . . . . 12 Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 9. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 10. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 11. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 13. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 14. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 15. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 16. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 17. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 18. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 19. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 52 Table 20. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 21. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 22. I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 23. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 24. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 26. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 27. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 28. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 29. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 30. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 31. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 32. Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 33. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 34. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 36. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 37. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 77 Table 39. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 80 Table 41. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 81 Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 82 Table 44. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 45. ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 46. On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 47. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 48. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Doc ID 14619 Rev 9 |
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List of tables |
SPC560B40x/50x, SPC560C40x/50x |
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Table 49. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 50. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 51. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 52. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 53. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 54. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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Doc ID 14619 Rev 9 |
SPC560B40x/50x, SPC560C40x/50x |
List of figures |
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List of figures
Figure 1. SPC560B40x/50x and SPC560C40x/50x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. LQFP 64-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. LQFP 100-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. LQFP 144-pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. LBGA208 confguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 7. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 10. VDD and VDD_BV maximum slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 11. VDD and VDD_BV supply constraints during STANDBY mode exit. . . . . . . . . . . . . . . . . . 65 Figure 12. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 13. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 14. Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 15. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 16. Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 17. Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 18. ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 19. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 20. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 21. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 22. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 23. DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 24. DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 25. DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 26. DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 27. DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 28. DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 29. DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 30. DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 31. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 32. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 33. Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 34. LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 35. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 36. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 37. LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 38. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Doc ID 14619 Rev 9 |
7/117 |
Introduction |
SPC560B40x/50x, SPC560C40x/50x |
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This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet.
The SPC560B40x/50x and SPC560C40x/50x is a family of next generation microcontrollers built on the Power Architecture embedded category.
The SPC560B40x/50x and SPC560C40x/50x family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.
8/117 |
Doc ID 14619 Rev 9 |
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Table 2. |
SPC560B40x/50x and SPC560C40x/50x device comparison(1) |
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Device |
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Feature |
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SPC560B |
SPC560B |
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SPC560B |
SPC560C |
SPC560C |
SPC560B |
SPC560B |
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SPC560B |
SPC560C |
SPC560C |
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SPC560B |
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40L1 |
40L3 |
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40L5 |
40L1 |
40L3 |
50L1 |
50L3 |
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50L5 |
50L1 |
50L3 |
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50B2 |
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CPU |
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e200z0h |
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Execution |
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Static – up to 64 MHz |
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speed(2) |
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Code Flash |
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256 KB |
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512 KB |
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Data Flash |
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64 KB (4 × 16 KB) |
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RAM |
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24 KB |
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32 KB |
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32 KB |
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48 KB |
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MPU |
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8-entry |
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IDDoc |
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ADC (10-bit) |
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12 ch |
28 ch |
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36 ch |
8 ch |
28 ch |
12 ch |
28 ch |
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36 ch |
8 ch |
28 ch |
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36 ch |
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14619 |
CTU |
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Yes |
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Total timer I/O(3) |
12 ch, |
28 ch, |
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56 ch, |
12 ch, |
28 ch, |
12 ch, |
28 ch, |
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56 ch, |
12 ch, |
28 ch, |
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56 ch, |
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9Rev |
eMIOS |
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16-bit |
16-bit |
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16-bit |
16-bit |
16-bit |
16-bit |
16-bit |
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16-bit |
16-bit |
16-bit |
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16-bit |
– PWM + MC + |
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2 ch |
5 ch |
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10 ch |
2 ch |
5 ch |
2 ch |
5 ch |
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10 ch |
2 ch |
5 ch |
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10 ch |
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IC/OC(4) |
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– PWM + |
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10 ch |
20 ch |
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40 ch |
10 ch |
20 ch |
10 ch |
20 ch |
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40 ch |
10 ch |
20 ch |
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40 ch |
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IC/OC(4) |
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– IC/OC(4) |
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— |
3 ch |
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6 ch |
— |
3 ch |
— |
3 ch |
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6 ch |
— |
3 ch |
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6 ch |
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SCI (LINFlex) |
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3(5) |
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4 |
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SPI (DSPI) |
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2 |
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3 |
2 |
3 |
2 |
3 |
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2 |
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CAN (FlexCAN) |
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2(6) |
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5 |
6 |
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3(7) |
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5 |
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I2C |
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1 |
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32 kHz oscillator |
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Yes |
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GPIO(8) |
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45 |
79 |
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123 |
45 |
79 |
45 |
79 |
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123 |
45 |
79 |
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123 |
9/117 |
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SPC560C40x/50x SPC560B40x/50x,
Introduction
10/117
9 Rev 14619 ID Doc
Table 2. |
SPC560B40x/50x and SPC560C40x/50x device comparison(1) (continued) |
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Device |
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Feature |
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SPC560B |
SPC560B |
SPC560B |
SPC560C |
SPC560C |
SPC560B |
SPC560B |
SPC560B |
SPC560C |
SPC560C |
SPC560B |
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40L1 |
40L3 |
40L5 |
40L1 |
40L3 |
50L1 |
50L3 |
50L5 |
50L1 |
50L3 |
50B2 |
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Debug |
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JTAG |
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Nexus2+ |
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Package |
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LQFP64(9) |
LQFP100 |
LQFP144 |
LQFP64(9) |
LQFP100 |
LQFP64(9) |
LQFP100 |
LQFP144 |
LQFP64(9) |
LQFP100 |
LBGA208 |
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(10) |
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1.Feature set dependent on selected peripheral multiplexing—table shows example implementation
2.Based on 125 °C ambient operating temperature
3.See the eMIOS section of the device reference manual for information on the channel configuration and functions.
4.IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter
5.SCI0, SCI1 and SCI2 are available. SCI3 is not available.
6.CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.
7.CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.
8.I/O count based on multiplexing with peripherals
9.All LQFP64 information is indicative and must be confirmed during silicon validation.
10.LBGA208 available only as development package for Nexus2+
Introduction
SPC560C40x/50x SPC560B40x/50x,
SPC560B40x/50x, SPC560C40x/50x |
Block diagram |
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Figure 1 shows a top-level block diagram of the SPC560B40x/50x and SPC560C40x/50x device series.
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JTAG |
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JTAG port |
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Nexus port |
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e200z0h |
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Nexus |
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NMI |
Nexus 2+ |
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SIUL |
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Voltage |
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regulator |
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NMI |
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Interrupt requests |
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from peripheral |
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blocks |
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INTC
Clocks |
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CMU |
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FMPLL |
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RTC |
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STM |
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SWT |
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ECSM |
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PIT |
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SRAM 48 KB
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Instructions |
Switch |
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SRAM |
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(Master) |
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controller |
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Crossbar |
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(Master) |
MPU |
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Data |
64-bit 2 x 3 |
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MPU registers
MC_RGM MC_CGM MC_ME MC_PCU
Peripheral bridge
Code Flash |
Data Flash |
512 KB |
64 KB |
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Flash controller
(Slave)
(Slave)
BAM SSCM
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SIUL |
36 Ch. |
CTU |
2 x |
4 x |
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3 x |
I2C |
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6 x |
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Reset control |
ADC |
eMIOS |
LINFlex |
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DSPI |
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FlexCAN |
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Interrupt |
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External |
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request |
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interrupt |
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request |
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IMUX |
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WKPU |
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GPIO and |
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pad control |
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Interrupt |
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request with |
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wakeup |
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functionality |
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Legend: |
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MC_CGM |
Clock Generation Module |
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ADC |
Analog-to-Digital Converter |
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BAM |
Boot Assist Module |
MC_ME |
Mode Entry Module |
FlexCAN |
Controller Area Network |
MC_PCU |
Power Control Unit |
CMU |
Clock Monitor Unit |
MC_RGM |
Reset Generation Module |
CTU |
Cross Triggering Unit |
MPU |
Memory Protection Unit |
DSPI |
Deserial Serial Peripheral Interface |
Nexus |
Nexus Development Interface (NDI) Level |
eMIOS |
Enhanced Modular Input Output System |
NMI |
Non-Maskable Interrupt |
FMPLL |
Frequency-Modulated Phase-Locked Loop |
PIT |
Periodic Interrupt Timer |
I2C |
Inter-integrated Circuit Bus |
RTC |
Real-Time Clock |
IMUX |
Internal Multiplexer |
SIUL |
System Integration Unit Lite |
INTC |
Interrupt Controller |
SRAM |
Static Random-Access Memory |
JTAG |
JTAG controller |
SSCM |
System Status Configuration Module |
LINFlex |
Serial Communication Interface (LIN support) |
STM |
System Timer Module |
ECSM |
Error Correction Status Module |
SWT |
Software Watchdog Timer |
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WKPU |
Wakeup Unit |
Doc ID 14619 Rev 9 |
11/117 |
Block diagram |
SPC560B40x/50x, SPC560C40x/50x |
|
|
Table 3 summarizes the functions of all blocks present in the SPC560B40x/50x and |
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SPC560C40x/50x series of microcontrollers. Please note that the presence and number of |
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blocks vary by device and package. |
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Table 3. |
SPC560B40x/50x and SPC560C40x/50x series block summary |
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Block |
Function |
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Analog-to-digital converter (ADC) |
Multi-channel, 10-bit analog-to-digital converter |
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Boot assist module (BAM) |
A block of read-only memory containing VLE code which is executed according |
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to the boot mode of the device |
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Clock monitor unit (CMU) |
Monitors clock source (internal and external) integrity |
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Cross triggering unit (CTU) |
Enables synchronization of ADC conversions with a timer event from the eMIOS |
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or from the PIT |
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Deserial serial peripheral |
Provides a synchronous serial interface for communication with external |
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interface (DSPI) |
devices |
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Provides a myriad of miscellaneous control functions for the device including |
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Error Correction Status Module |
program-visible information about configuration and revision levels, a reset |
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(ECSM) |
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status register, wakeup control for exiting sleep modes, and optional features |
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such as information on memory errors reported by error-correcting codes |
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Enhanced Direct Memory Access |
Performs complex data transfers with minimal intervention from a host |
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(eDMA) |
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processor via “n” programmable channels. |
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Enhanced modular input output |
Provides the functionality to generate or measure events |
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system (eMIOS) |
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Flash memory |
Provides non-volatile storage for program code, constants and variables |
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FlexCAN (controller area |
Supports the standard CAN communications protocol |
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network) |
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Frequency-modulated phase- |
Generates high-speed system clocks and supports programmable frequency |
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locked loop (FMPLL) |
modulation |
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Internal multiplexer (IMUX) SIU |
Allows flexible mapping of peripheral interface on the different pins of the device |
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subblock |
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Inter-integrated circuit (I2C™) bus |
A two wire bidirectional serial bus that provides a simple and efficient method of |
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data exchange between devices |
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Interrupt controller (INTC) |
Provides priority-based preemptive scheduling of interrupt requests |
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JTAG controller |
Provides the means to test chip functionality and connectivity while remaining |
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transparent to system logic when not in test mode |
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LINFlex controller |
Manages a high number of LIN (Local Interconnect Network protocol) |
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messages efficiently with a minimum of CPU load |
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Clock generation module |
Provides logic and control required for the generation of system and peripheral |
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(MC_CGM) |
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clocks |
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Provides a mechanism for controlling the device operational mode and mode |
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Mode entry module (MC_ME) |
transition sequences in all functional states; also manages the power control |
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unit, reset generation module and clock generation module, and holds the |
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configuration, control and status registers accessible for applications |
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12/117 |
Doc ID 14619 Rev 9 |
SPC560B40x/50x, SPC560C40x/50x |
Block diagram |
|||
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||
Table 3. |
SPC560B40x/50x and SPC560C40x/50x series block summary (continued) |
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Block |
Function |
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Reduces the overall power consumption by disconnecting parts of the device |
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Power control unit (MC_PCU) |
from the power supply via a power switching device; device components are |
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grouped into sections called “power domains” which are controlled by the PCU |
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Reset generation module |
Centralizes reset sources and manages the device reset sequence of the |
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(MC_RGM) |
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device |
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Memory protection unit (MPU) |
Provides hardware access control for all memory references generated in a |
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device |
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Nexus development interface |
Provides real-time development support capabilities in compliance with the |
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(NDI) |
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IEEE-ISTO 5001-2003 standard |
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Periodic interrupt timer (PIT) |
Produces periodic interrupts and triggers |
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A free running counter used for time keeping applications, the RTC can be |
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Real-time counter (RTC) |
configured to generate an interrupt at a predefined interval independent of the |
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mode of operation (run mode or low-power mode) |
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Provides control over all the electrical pad controls and up 32 ports with 16 bits |
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System integration unit (SIU) |
of bidirectional, general-purpose input and output signals and supports up to 32 |
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external interrupts with trigger event configuration |
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Static random-access memory |
Provides storage for program code, constants, and variables |
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(SRAM) |
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System status configuration |
Provides system configuration and status data (such as memory size and |
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status, device mode and security status), device identification data, debug |
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module (SSCM) |
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status port enable and selection, and bus and peripheral abort enable/disable |
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System timer module (STM) |
Provides a set of output compare events to support AUTOSAR and operating |
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system tasks |
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System watchdog timer (SWT) |
Provides protection from runaway code |
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The wakeup unit supports up to 18 external sources that can generate |
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Wakeup unit (WKPU) |
interrupts or wakeup events, of which 1 can cause non-maskable interrupt |
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requests or wakeup events. |
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Supports simultaneous connections between two master ports and three slave |
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Crossbar (XBAR) switch |
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus |
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width. |
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Doc ID 14619 Rev 9 |
13/117 |
Package pinouts and signal descriptions |
SPC560B40x/50x, SPC560C40x/50x |
|
|
The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual (RM0017).
|
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PB[2] |
PC[8] |
PC[4] PC[5] PH[9] PC[0] VSS LV VDD LV VDD HV VSS HV PC[1] PH[10] PA[6] PA[5] PC[2] |
PC[3] |
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 |
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PB[3] |
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1 |
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48 |
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PA[11] |
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PC[9] |
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2 |
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47 |
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PA[10] |
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PA[2] |
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3 |
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46 |
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PA[9] |
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PA[1] |
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4 |
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45 |
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PA[8] |
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PA[0] |
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44 |
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PA[7] |
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VSS_HV |
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6 |
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43 |
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PA[3] |
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VDD_HV |
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7 |
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42 |
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PB[15] |
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VSS_HV |
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8 |
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LQFP64 Top view |
41 |
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PB[14] |
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RESET |
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9 |
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40 |
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PB[13] |
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VSS_LV |
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10 |
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39 |
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PB[12] |
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VDD_LV |
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11 |
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38 |
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PB[11] |
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VDD_BV |
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12 |
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37 |
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PB[7] |
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PC[10] |
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13 |
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36 |
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PB[6] |
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PB[0] |
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14 |
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35 |
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PB[5] |
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PB[1] |
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34 |
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VDD_HV_ADC |
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PC[6] |
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16 |
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33 |
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VSS_HV_ADC |
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17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
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PC[7] |
PA[15] |
PA[14] PA[4] PA[13] PA[12] VDD LV VSS LV XTAL VSS HV EXTAL VDD HV PB[9] PB[8] PB[10] |
PB[4] |
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a. All LQFP64 information is indicative and must be confirmed during silicon validation.
14/117 |
Doc ID 14619 Rev 9 |
SPC560B40x/50x, SPC560C40x/50x |
Package pinouts and signal descriptions |
|
|
|
|
|
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|
|
PB[2] |
PC[8] |
PC[13] |
PC[12] |
PE[7] |
PE[6] |
PE[5] |
PE[4] |
PC[4] |
PC[5] |
PE[3] |
PE[2] |
PH[9] |
PC[0] |
VSS LV |
VDD LV |
VDD HV |
VSS HV |
PC[1] |
PH[10] |
PA[6] |
PA[5] |
PC[2] |
PC[3] |
PE[12] |
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100 |
99 |
98 |
97 |
96 |
95 |
94 |
93 |
92 |
91 |
90 |
89 |
88 |
87 |
86 |
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85 |
84 |
83 |
82 |
81 |
80 |
79 |
78 |
77 |
76 |
|
|
|
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
PB[3] |
|
|
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
75 |
|
|
PA[11] |
|||||
|
PC[9] |
|
|
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
74 |
|
|
PA[10] |
|||||
|
PC[14] |
|
|
3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
73 |
|
|
PA[9] |
|||||
|
PC[15] |
|
|
4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
72 |
|
|
PA[8] |
|||||
|
PA[2] |
|
|
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
71 |
|
|
PA[7] |
|||||
|
PE[0] |
|
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
70 |
|
|
VDD_HV |
||||||
|
PA[1] |
|
|
7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
69 |
|
|
VSS_HV |
|||||
|
PE[1] |
|
|
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
68 |
|
|
PA[3] |
|||||
|
PE[8] |
|
|
9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
67 |
|
|
PB[15] |
|||||
|
PE[9] |
|
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
66 |
|
|
PD[15] |
|||||
|
PE[10] |
|
|
11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
65 |
|
|
PB[14] |
|||||
|
PA[0] |
|
|
12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LQFP100 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
64 |
|
|
PD[14] |
|||||||||||||||||||||||||||||||||||||
|
PE[11] |
|
|
13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
63 |
|
|
PB[13] |
||||||||||||||||||||||||||||||||||||||
VSS_HV |
|
|
14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
62 |
|
|
PD[13] |
|||||||||||||||||||||||||||||||||||||||
VDD_HV |
|
|
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Top view |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
61 |
|
|
PB[12] |
|||||||||||||||||||||||||||||||||||
VSS_HV |
|
|
16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
60 |
|
|
PD[12] |
||||||||||||||||||||||||||||||||||||
|
RESET |
|
|
|
17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
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|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
59 |
|
|
PB[11] |
||||
VSS_LV |
|
|
18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
58 |
|
|
PD[11] |
||||||
VDD_LV |
|
19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
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|
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|
|
|
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|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
57 |
|
|
PD[10] |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
VDD_BV |
|
|
20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
56 |
|
|
PD[9] |
||||||
|
PC[11] |
|
|
21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
55 |
|
|
PB[7] |
|||||
|
PC[10] |
|
|
22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
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|
|
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|
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|
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|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
54 |
|
|
PB[6] |
|||||
|
PB[0] |
|
|
23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
53 |
|
|
PB[5] |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
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|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
|
PB[1] |
|
|
24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
52 |
|
|
VDD_HV_ADC |
|||||
|
PC[6] |
|
|
25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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51 |
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VSS_HV_ADC |
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26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
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40 |
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41 |
42 |
43 |
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45 |
46 |
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48 |
49 |
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PC[7] |
PA[15] |
PA[14] |
PA[4] |
PA[13] |
PA[12] |
VDD LV |
VSS LV |
XTAL |
VSS HV |
EXTAL |
VDD HV |
PB[9] |
PB[8] |
PB[10] |
PD[0] |
PD[1] |
PD[2] |
PD[3] |
PD[4] |
PD[5] |
PD[6] |
PD[7] |
PD[8] |
PB[4] |
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Note:
Availability of port pin alternate functions depends on product selection.
Doc ID 14619 Rev 9 |
15/117 |
Package pinouts and signal descriptions |
SPC560B40x/50x, SPC560C40x/50x |
|
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PB[3] 1
PC[9] 2
PC[14] 3 PC[15] 4 PG[5] 5 PG[4] 6 PG[3] 7 PG[2] 8 PA[2] 9
PE[0] 10 PA[1] 11 PE[1] 12 PE[8] 13 PE[9] 14
PE[10] 15 PA[0] 16 PE[11] 17 VSS_HV 18 VDD_HV 19 VSS_HV 20 RESET 21 VSS_LV 22 VDD_LV 23 VDD_BV 24 PG[9] 25 PG[8] 26 PC[11] 27 PC[10] 28 PG[7] 29 PG[6] 30 PB[0] 31 PB[1] 32 PF[9] 33 PF[8] 34 PF[12] 35 PC[6] 36
PB[2] |
PC[8] |
PC[13] |
PC[12] |
PE[7] |
PE[6] |
PH[8] |
PH[7] |
PH[6] |
PH[5] |
PH[4] |
PE[5] |
PE[4] |
PC[4] |
PC[5] |
PE[3] |
PE[2] |
PH[9] |
PC[0] |
VSS LV |
VDD LV |
VDD HV |
VSS HV |
PC[1] |
PH[10] |
PA[6] |
PA[5] |
PC[2] |
PC[3] |
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144 |
143 |
142 |
141 |
140 |
139 |
138 |
137 |
136 |
135 |
134 |
133 |
132 |
131 |
130 |
129 |
128 |
127 |
126 |
125 |
124 |
123 |
122 |
121 |
120 |
119 |
118 |
117 |
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116 |
LQFP144
Top view
37 |
38 |
39 |
40 |
41 |
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42 |
43 |
44 |
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45 |
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46 |
47 |
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48 |
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49 |
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50 |
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51 |
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52 |
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53 |
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54 |
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55 |
56 |
57 |
58 |
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59 |
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60 |
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61 |
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62 |
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63 |
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64 |
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65 |
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PC[7] |
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PF[10] |
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PF[11] |
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PA[15] |
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PF[13] |
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PA[14] |
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PA[4] |
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PA[13] |
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PA[12] |
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VDD LV |
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VSS LV |
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XTAL |
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VSS HV |
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EXTAL |
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VDD HV |
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PB[9] |
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PB[8] |
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PB[10] |
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PF[0] |
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PF[1] |
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PF[2] |
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PF[3] |
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PF[4] |
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PF[5] |
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PF[6] |
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PF[7] |
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PD[0] |
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PD[1] |
PD[2] |
PG[11] |
PG[10] |
PE[15] |
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115 |
114 |
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113 |
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66 |
67 |
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68 |
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PD[3] |
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PD[4] |
PD[5] |
PE[14] |
PG[15] |
PG[14] |
PE[12] |
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112 |
111 |
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110 |
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109 |
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69 |
70 |
71 |
72 |
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PD[6] |
PD[7] |
PD[8] |
PB[4] |
108 PA[11]
107 PA[10]
106 PA[9]
105 PA[8]
104 PA[7]
103 PE[13]
102 PF[14]
101 PF[15]
100 VDD_HV
99 VSS_HV
98 PG[0]
97 PG[1]
96 PH[3]
95 PH[2]
94 PH[1]
93 PH[0]
92 PG[12]
91 PG[13]
90 PA[3]
89 PB[15]
88 PD[15]
87 PB[14]
86 PD[14]
85 PB[13]
84 PD[13]
83 PB[12]
82 PD[12]
81 PB[11]
80 PD[11]
79 PD[10]
78 PD[9]
77 PB[7]
76 PB[6]
75 PB[5]
74 VDD_HV_ADC
73 VSS_HV_ADC
Note:
Availability of port pin alternate functions depends on product selection.
16/117 |
Doc ID 14619 Rev 9 |
SPC560B40x/50x, SPC560C40x/50x |
|
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|
Package pinouts and signal descriptions |
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Figure 5. |
LBGA208 confguration |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
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A |
PC[8] |
PC[13] |
NC |
NC |
PH[8] |
PH[4] |
PC[5] |
PC[0] |
NC |
NC |
PC[2] |
NC |
PE[15] |
NC |
NC |
NC |
A |
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B |
PC[9] |
PB[2] |
NC |
PC[12] |
PE[6] |
PH[5] |
PC[4] |
PH[9] |
PH[10] |
NC |
PC[3] |
PG[11] |
PG[15] |
PG[14] |
PA[11] |
PA[10] |
B |
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C |
PC[14] |
VDD_H |
PB[3] |
PE[7] |
PH[7] |
PE[5] |
PE[3] |
VSS_L |
PC[1] |
NC |
PA[5] |
NC |
PE[14] |
PE[12] |
PA[9] |
PA[8] |
C |
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V |
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V |
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D |
NC |
NC |
PC[15] |
NC |
PH[6] |
PE[4] |
PE[2] |
VDD_L |
VDD_H |
NC |
PA[6] |
NC |
PG[10] |
PF[14] |
PE[13] |
PA[7] |
D |
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V |
V |
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E |
PG[4] |
PG[5] |
PG[3] |
PG[2] |
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PG[1] |
PG[0] |
PF[15] |
VDD_H |
E |
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V |
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F |
PE[0] |
PA[2] |
PA[1] |
PE[1] |
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PH[0] |
PH[1] |
PH[3] |
PH[2] |
F |
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G |
PE[9] |
PE[8] |
PE[10] |
PA[0] |
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VSS_H |
VSS_H |
VSS_H |
VSS_H |
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VDD_H |
NC |
NC |
MSEO |
G |
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V |
V |
V |
V |
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V |
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H |
VSS_H |
PE[11] |
VDD_H |
NC |
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VSS_H |
VSS_H |
VSS_H |
VSS_H |
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MDO3 |
MDO2 |
MDO0 |
MDO1 |
H |
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V |
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V |
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V |
V |
V |
V |
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J |
RESET |
VSS_L |
NC |
NC |
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VSS_H |
VSS_H |
VSS_H |
VSS_H |
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NC |
NC |
NC |
NC |
J |
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V |
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V |
V |
V |
V |
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K |
EVTI |
NC |
VDD_B |
VDD_L |
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VSS_H |
VSS_H |
VSS_H |
VSS_H |
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NC |
PG[12] |
PA[3] |
PG[13] |
K |
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V |
V |
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V |
V |
V |
V |
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L |
PG[9] |
PG[8] |
NC |
EVTO |
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PB[15] |
PD[15] |
PD[14] |
PB[14] |
L |
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M |
PG[7] |
PG[6] |
PC[10] |
PC[11] |
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PB[13] |
PD[13] |
PD[12] |
PB[12] |
M |
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N |
PB[1] |
PF[9] |
PB[0] |
NC |
NC |
PA[4] |
VSS_L |
EXTAL |
VDD_H |
PF[0] |
PF[4] |
NC |
PB[11] |
PD[10] |
PD[9] |
PD[11] |
N |
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V |
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V |
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P |
PF[8] |
NC |
PC[7] |
NC |
NC |
PA[14] |
VDD_L |
XTAL |
PB[10] |
PF[1] |
PF[5] |
PD[0] |
PD[3] |
VDD_H |
PB[6] |
PB[7] |
P |
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V |
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V_ADC |
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VDD_H |
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OSC32 |
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VSS_H |
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R |
PF[12] |
PC[6] |
PF[10] |
PF[11] |
PA[15] |
PA[13] |
NC |
K_XTA |
PF[3] |
PF[7] |
PD[2] |
PD[4] |
PD[7] |
PB[5] |
R |
|||
V |
V_ADC |
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L |
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OSC32 |
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T |
NC |
NC |
NC |
MCKO |
NC |
PF[13] |
PA[12] |
NC |
K_EXT |
PF[2] |
PF[6] |
PD[1] |
PD[5] |
PD[6] |
PD[8] |
PB[4] |
T |
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AL |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
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= Not connected |
|||
Note: LBGA208 available only as development package for Nexus 2+. |
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NC |
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All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
Doc ID 14619 Rev 9 |
17/117 |
Package pinouts and signal descriptions |
SPC560B40x/50x, SPC560C40x/50x |
|
|
After power-up phase, all pads are forced to tristate with the following exceptions:
●PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.
●PA[8] (ABS[0]) is pull-up.
●RESET pad is driven low. This is pull-up only after PHASE2 reset completion.
●JTAG pads (TCK, TMS and TDI) are pull-up whilst TDO remains tristate.
●Precise ADC pads (PB[7:4] and PD[11:0]) are left tristate (no output buffer available).
●Main oscillator pads (EXTAL, XTAL) are tristate.
●Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
Voltage supply pins are used to provide power to the device. Three dedicated
VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.
Table 4. |
Voltage supply pin descriptions |
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Port pin |
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Function |
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Pin number |
|
||
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|||
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LQFP64 |
LQFP100 |
LQFP144 |
LBGA208(1) |
|||
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|||||
VDD_HV |
|
Digital supply voltage |
7, 28, 56 |
15, 37, 70, |
19, 51, 100, |
C2, D9, E16, |
|
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84 |
123 |
G13, H3, |
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N9, R5 |
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G7, G8, G9, |
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G10, H1, |
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VSS_HV |
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Digital ground |
6, 8, 26, 55 |
14, 16, 35, |
18, 20, 49, |
H7, H8, H9, |
|
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69, 83 |
99, 122 |
H10, J7, J8, |
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J9, J10, K7, |
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K8, K9, K10 |
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1.2V decoupling pins. Decoupling |
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VDD_LV |
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capacitor must be connected between |
11, 23, 57 |
19, 32, 85 |
23, 46, 124 |
D8, K4, P7 |
|
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these pins and the nearest VSS_LV |
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pin.(2) |
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1.2V decoupling pins. Decoupling |
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VSS_LV |
|
capacitor must be connected between |
10, 24, 58 |
18, 33, 86 |
22, 47, 125 |
C8, J2, N7 |
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these pins and the nearest VDD_LV |
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pin.(2) |
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VDD_BV |
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Internal regulator supply voltage |
12 |
20 |
24 |
K3 |
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VSS_HV_ADC |
Reference ground and analog ground |
33 |
51 |
73 |
R15 |
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for the ADC |
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VDD_HV_ADC |
Reference voltage and analog supply |
34 |
52 |
74 |
P14 |
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for the ADC |
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1.LBGA208 available only as development package for Nexus2+.
2.A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see the recommended operating conditions in the device datasheet for details).
18/117 |
Doc ID 14619 Rev 9 |
SPC560B40x/50x, SPC560C40x/50x |
Package pinouts and signal descriptions |
|
|
In the device the following types of pads are available for system pins and functional port pins:
S = Slow(b)
M = Medium (b)(c) F = Fast (b)(c)
I = Input only with analog feature(b)
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator
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The system pins are listed in Table 5. |
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Table 5. |
System pin descriptions |
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Systempin |
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directionI/O |
Padtype |
configurationRESET |
LQFP64 |
|
LQFP100 |
LQFP144 |
LBGA208 |
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Pin number |
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Function |
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(1) |
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Bidirectional reset with Schmitt-Trigger characteristics |
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Input, weak |
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RESET |
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I/O |
M |
pull-up only |
9 |
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17 |
21 |
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J1 |
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and noise filter. |
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after PHASE2 |
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Analog output of the oscillator amplifier circuit, when the |
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EXTAL |
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oscillator is not in bypass mode. |
I/O |
X |
Tristate |
27 |
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36 |
50 |
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N8 |
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Analog input for the clock generator when the oscillator |
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is in bypass mode.(2) |
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XTAL |
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Analog input of the oscillator amplifier circuit. Needs to |
I |
X |
Tristate |
25 |
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34 |
48 |
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P8 |
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be grounded if oscillator is used in bypass mode.(2) |
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1.LBGA208 available only as development package for Nexus2+.
2.See the relevant section of the datasheet .
b.See the I/O pad electrical characteristics in the device datasheet for details.
c.All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium (see PCR.SRC in section Pad Configuration Registers (PCR0–PCR122) in the device reference manual).
Doc ID 14619 Rev 9 |
19/117 |
20/117
9 Rev 14619 ID Doc
The functional port pins are listed in Table 6.
Table 6. |
Functional port pin descriptions |
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(1) |
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Peripheral |
(2) |
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RESET configuration |
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Pin number |
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I/Odirection |
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(3) |
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Portpin |
PCR |
Alternate function |
Function |
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
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PA[0] |
PCR[0] |
AF0 |
GPIO[0] |
SIUL |
I/O |
M |
Tristate |
5 |
12 |
16 |
G4 |
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AF1 |
E0UC[0] |
eMIOS_0 |
I/O |
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AF2 |
CLKOUT |
CGL |
O |
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AF3 |
— |
— |
— |
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— |
WKPU[19](4) |
WKPU |
I |
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PA[1] |
PCR[1] |
AF0 |
GPIO[1] |
SIUL |
I/O |
S |
Tristate |
4 |
7 |
11 |
F3 |
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AF1 |
E0UC[1] |
eMIOS_0 |
I/O |
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AF2 |
— |
— |
— |
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AF3 |
— |
— |
— |
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— |
NMI(5) |
WKPU |
I |
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— |
WKPU[2](4) |
WKPU |
I |
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PA[2] |
PCR[2] |
AF0 |
GPIO[2] |
SIUL |
I/O |
S |
Tristate |
3 |
5 |
9 |
F2 |
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AF1 |
E0UC[2] |
eMIOS_0 |
I/O |
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AF2 |
— |
— |
— |
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AF3 |
— |
— |
— |
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— |
WKPU[3](4) |
WKPU |
I |
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PA[3] |
PCR[3] |
AF0 |
GPIO[3] |
SIUL |
I/O |
S |
Tristate |
43 |
68 |
90 |
K15 |
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AF1 |
E0UC[3] |
eMIOS_0 |
I/O |
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AF2 |
— |
— |
— |
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AF3 |
— |
— |
— |
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— |
EIRQ[0] |
SIUL |
I |
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PA[4] |
PCR[4] |
AF0 |
GPIO[4] |
SIUL |
I/O |
S |
Tristate |
20 |
29 |
43 |
N6 |
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AF1 |
E0UC[4] |
eMIOS_0 |
I/O |
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AF2 |
— |
— |
— |
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AF3 |
— |
— |
— |
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— |
WKPU[9](4) |
WKPU |
I |
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descriptions signal and pinouts Package
SPC560C40x/50x SPC560B40x/50x,
|
Table 6. |
Functional port pin descriptions (continued) |
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(1) |
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Peripheral |
(2) |
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RESET configuration |
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Pin number |
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I/Odirection |
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(3) |
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Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
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PA[5] |
PCR[5] |
AF0 |
GPIO[5] |
|
SIUL |
I/O |
M |
Tristate |
51 |
79 |
118 |
C11 |
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AF1 |
E0UC[5] |
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eMIOS_0 |
I/O |
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AF2 |
— |
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— |
— |
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AF3 |
— |
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— |
— |
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PA[6] |
PCR[6] |
AF0 |
GPIO[6] |
|
SIUL |
I/O |
S |
Tristate |
52 |
80 |
119 |
D11 |
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AF1 |
E0UC[6] |
|
eMIOS_0 |
I/O |
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AF2 |
— |
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— |
— |
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AF3 |
— |
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— |
— |
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Doc |
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— |
EIRQ[1] |
|
SIUL |
I |
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PA[7] |
PCR[7] |
AF0 |
GPIO[7] |
|
SIUL |
I/O |
S |
Tristate |
44 |
71 |
104 |
D16 |
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ID |
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AF1 |
E0UC[7] |
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eMIOS_0 |
I/O |
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14619 |
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AF2 |
LIN3TX |
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LINFlex_3 |
O |
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AF3 |
— |
|
— |
— |
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Rev |
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— |
EIRQ[2] |
|
SIUL |
I |
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PA[8] |
PCR[8] |
AF0 |
GPIO[8] |
|
SIUL |
I/O |
S |
Input, weak |
45 |
72 |
105 |
C16 |
|
9 |
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AF1 |
E0UC[8] |
|
eMIOS_0 |
I/O |
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pull-up |
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AF2 |
— |
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— |
— |
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AF3 |
— |
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— |
— |
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— |
EIRQ[3] |
|
SIUL |
I |
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N/A(6) |
ABS[0] |
|
BAM |
I |
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— |
LIN3RX |
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LINFlex_3 |
I |
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PA[9] |
PCR[9] |
AF0 |
GPIO[9] |
|
SIUL |
I/O |
S |
Pull-down |
46 |
73 |
106 |
C15 |
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AF1 |
E0UC[9] |
|
eMIOS_0 |
I/O |
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AF2 |
— |
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— |
— |
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AF3 |
— |
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— |
— |
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N/A(6) |
FAB |
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BAM |
I |
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PA[10] |
PCR[10] |
AF0 |
GPIO[10] |
|
SIUL |
I/O |
S |
Tristate |
47 |
74 |
107 |
B16 |
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AF1 |
E0UC[10] |
|
eMIOS_0 |
I/O |
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21/117 |
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AF2 |
SDA |
|
I2C_0 |
I/O |
|
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AF3 |
— |
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— |
— |
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SPC560C40x/50x SPC560B40x/50x,
descriptions signal and pinouts Package
22/117
9 Rev 14619 ID Doc
Table 6. |
Functional port pin descriptions (continued) |
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|||
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|
(1) |
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Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
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||||
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I/Odirection |
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(3) |
|||
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
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PA[11] |
PCR[11] |
AF0 |
GPIO[11] |
|
SIUL |
I/O |
S |
Tristate |
48 |
75 |
108 |
B15 |
|
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AF1 |
E0UC[11] |
|
eMIOS_0 |
I/O |
|
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AF2 |
SCL |
|
I2C_0 |
I/O |
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AF3 |
— |
|
— |
— |
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PA[12] |
PCR[12] |
AF0 |
GPIO[12] |
|
SIUL |
I/O |
S |
Tristate |
22 |
31 |
45 |
T7 |
|
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AF1 |
— |
|
— |
— |
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AF2 |
— |
|
— |
— |
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AF3 |
— |
|
— |
— |
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— |
SIN_0 |
|
DSPI0 |
I |
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PA[13] |
PCR[13] |
AF0 |
GPIO[13] |
|
SIUL |
I/O |
M |
Tristate |
21 |
30 |
44 |
R7 |
|
|
AF1 |
SOUT_0 |
|
DSPI_0 |
O |
|
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AF2 |
— |
|
— |
— |
|
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AF3 |
— |
|
— |
— |
|
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PA[14] |
PCR[14] |
AF0 |
GPIO[14] |
|
SIUL |
I/O |
M |
Tristate |
19 |
28 |
42 |
P6 |
|
|
AF1 |
SCK_0 |
|
DSPI_0 |
I/O |
|
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|
AF2 |
CS0_0 |
|
DSPI_0 |
I/O |
|
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AF3 |
— |
|
— |
— |
|
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|
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|
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|
|
— |
EIRQ[4] |
|
SIUL |
I |
|
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|
|
PA[15] |
PCR[15] |
AF0 |
GPIO[15] |
|
SIUL |
I/O |
M |
Tristate |
18 |
27 |
40 |
R6 |
|
|
AF1 |
CS0_0 |
|
DSPI_0 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
SCK_0 |
|
DSPI_0 |
I/O |
|
|
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|
|
AF3 |
— |
|
— |
— |
|
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|
|
|
|
|
|
— |
WKPU[10](4) |
|
WKPU |
I |
|
|
|
|
|
|
PB[0] |
PCR[16] |
AF0 |
GPIO[16] |
|
SIUL |
I/O |
M |
Tristate |
14 |
23 |
31 |
N3 |
|
|
AF1 |
CAN0TX |
|
FlexCAN_0 |
O |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
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|
AF3 |
— |
|
— |
— |
|
|
|
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|
|
|
|
|
|
|
|
|
|
descriptions signal and pinouts Package
SPC560C40x/50x SPC560B40x/50x,
|
Table 6. |
Functional port pin descriptions (continued) |
|
|
|
|
|
|
|
|
|||
|
|
|
(1) |
|
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
|||
|
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[1] |
PCR[17] |
AF0 |
GPIO[17] |
|
SIUL |
I/O |
S |
Tristate |
15 |
24 |
32 |
N1 |
|
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
— |
WKPU[4](4) |
|
WKPU |
I |
|
|
|
|
|
|
|
|
|
— |
CAN0RX |
|
FlexCAN_0 |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[2] |
PCR[18] |
AF0 |
GPIO[18] |
|
SIUL |
I/O |
M |
Tristate |
64 |
100 |
144 |
B2 |
|
|
|
AF1 |
LIN0TX |
|
LINFlex_0 |
O |
|
|
|
|
|
|
ID Doc |
|
|
AF2 |
SDA |
|
I2C_0 |
I/O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[3] |
PCR[19] |
AF0 |
GPIO[19] |
|
SIUL |
I/O |
S |
Tristate |
1 |
1 |
1 |
C3 |
|
14619 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
AF2 |
SCL |
|
I2C_0 |
I/O |
|
|
|
|
|
|
Rev |
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
WKPU[11](4) |
|
WKPU |
I |
|
|
|
|
|
|
|
9 |
|
|
— |
LIN0RX |
|
LINFlex_0 |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[4] |
PCR[20] |
AF0 |
GPIO[20] |
|
SIUL |
I |
I |
Tristate |
32 |
50 |
72 |
T16 |
|
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
— |
GPI[0] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[5] |
PCR[21] |
AF0 |
GPIO[21] |
|
SIUL |
I |
I |
Tristate |
35 |
53 |
75 |
R16 |
|
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
— |
GPI[1] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[6] |
PCR[22] |
AF0 |
GPIO[22] |
|
SIUL |
I |
I |
Tristate |
36 |
54 |
76 |
P15 |
|
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
23/117 |
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
— |
GPI[2] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPC560C40x/50x SPC560B40x/50x,
descriptions signal and pinouts Package
24/117
9 Rev 14619 ID Doc
Table 6. |
Functional port pin descriptions (continued) |
|
|
|
|
|
|
|
|
|||
|
|
(1) |
|
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
|||
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[7] |
PCR[23] |
AF0 |
GPIO[23] |
|
SIUL |
I |
I |
Tristate |
37 |
55 |
77 |
P16 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
GPI[3] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[8] |
PCR[24] |
AF0 |
GPIO[24] |
|
SIUL |
I |
I |
Tristate |
30 |
39 |
53 |
R9 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
ANS[0] |
|
ADC |
I |
|
|
|
|
|
|
|
|
— |
OSC32K_XTAL(7) |
|
SXOSC |
I/O |
|
|
|
|
|
|
PB[9] |
PCR[25] |
AF0 |
GPIO[25] |
|
SIUL |
I |
I |
Tristate |
29 |
38 |
52 |
T9 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
ANS[1] |
|
ADC |
I |
|
|
|
|
|
|
|
|
— |
OSC32K_EXTAL(7) |
|
SXOSC |
I/O |
|
|
|
|
|
|
PB[10] |
PCR[26] |
AF0 |
GPIO[26] |
|
SIUL |
I/O |
J |
Tristate |
31 |
40 |
54 |
P9 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
ANS[2] |
|
ADC |
I |
|
|
|
|
|
|
|
|
— |
WKPU[8](4) |
|
WKPU |
I |
|
|
|
|
|
|
PB[11](8) |
PCR[27] |
AF0 |
GPIO[27] |
|
SIUL |
I/O |
J |
Tristate |
38 |
59 |
81 |
N13 |
|
|
AF1 |
E0UC[3] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
CS0_0 |
|
DSPI_0 |
I/O |
|
|
|
|
|
|
|
|
— |
ANS[3] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
descriptions signal and pinouts Package
SPC560C40x/50x SPC560B40x/50x,
|
Table 6. |
Functional port pin descriptions (continued) |
|
|
|
|
|
|
|
|
|||
|
|
|
(1) |
|
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
|||
|
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[12] |
PCR[28] |
AF0 |
GPIO[28] |
|
SIUL |
I/O |
J |
Tristate |
39 |
61 |
83 |
M16 |
|
|
|
AF1 |
E0UC[4] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF3 |
CS1_0 |
|
DSPI_0 |
O |
|
|
|
|
|
|
|
|
|
— |
ANX[0] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[13] |
PCR[29] |
AF0 |
GPIO[29] |
|
SIUL |
I/O |
J |
Tristate |
40 |
63 |
85 |
M13 |
|
|
|
AF1 |
E0UC[5] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
ID Doc |
|
|
AF3 |
CS2_0 |
|
DSPI_0 |
O |
|
|
|
|
|
|
|
|
— |
ANX[1] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[14] |
PCR[30] |
AF0 |
GPIO[30] |
|
SIUL |
I/O |
J |
Tristate |
41 |
65 |
87 |
L16 |
|
14619 |
|
|
AF1 |
E0UC[6] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
Rev |
|
|
AF3 |
CS3_0 |
|
DSPI_0 |
O |
|
|
|
|
|
|
|
|
— |
ANX[2] |
|
ADC |
I |
|
|
|
|
|
|
|
9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PB[15] |
PCR[31] |
AF0 |
GPIO[31] |
|
SIUL |
I/O |
J |
Tristate |
42 |
67 |
89 |
L13 |
|
|
|
||||||||||||
|
|
|
AF1 |
E0UC[7] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF3 |
CS4_0 |
|
DSPI_0 |
O |
|
|
|
|
|
|
|
|
|
— |
ANX[3] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[0](9) |
PCR[32] |
AF0 |
GPIO[32] |
|
SIUL |
I/O |
M |
Input, weak |
59 |
87 |
126 |
A8 |
|
|
|
AF1 |
— |
|
— |
— |
|
pull-up |
|
|
|
|
|
|
|
AF2 |
TDI |
|
JTAGC |
I |
|
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[1](9) |
PCR[33] |
AF0 |
GPIO[33] |
|
SIUL |
I/O |
M |
Tristate |
54 |
82 |
121 |
C9 |
|
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF2 |
TDO(10) |
|
JTAGC |
O |
|
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
25/117 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPC560C40x/50x SPC560B40x/50x,
descriptions signal and pinouts Package
26/117
9 Rev 14619 ID Doc
Table 6. |
Functional port pin descriptions (continued) |
|
|
|
|
|
|
|
|
|||
|
|
(1) |
|
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
|||
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[2] |
PCR[34] |
AF0 |
GPIO[34] |
|
SIUL |
I/O |
M |
Tristate |
50 |
78 |
117 |
A11 |
|
|
AF1 |
SCK_1 |
|
DSPI_1 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
CAN4TX(11) |
|
FlexCAN_4 |
O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
EIRQ[5] |
|
SIUL |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[3] |
PCR[35] |
AF0 |
GPIO[35] |
|
SIUL |
I/O |
S |
Tristate |
49 |
77 |
116 |
B11 |
|
|
AF1 |
CS0_1 |
|
DSPI_1 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
MA[0] |
|
ADC |
O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
CAN1RX |
|
FlexCAN_1 |
I |
|
|
|
|
|
|
|
|
— |
CAN4RX(11) |
|
FlexCAN_4 |
I |
|
|
|
|
|
|
|
|
— |
EIRQ[6] |
|
SIUL |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[4] |
PCR[36] |
AF0 |
GPIO[36] |
|
SIUL |
I/O |
M |
Tristate |
62 |
92 |
131 |
B7 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
SIN_1 |
|
DSPI_1 |
I |
|
|
|
|
|
|
|
|
— |
CAN3RX(11) |
|
FlexCAN_3 |
I |
|
|
|
|
|
|
PC[5] |
PCR[37] |
AF0 |
GPIO[37] |
|
SIUL |
I/O |
M |
Tristate |
61 |
91 |
130 |
A7 |
|
|
AF1 |
SOUT_1 |
|
DSPI1 |
O |
|
|
|
|
|
|
|
|
AF2 |
CAN3TX(11) |
|
FlexCAN_3 |
O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
EIRQ[7] |
|
SIUL |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[6] |
PCR[38] |
AF0 |
GPIO[38] |
|
SIUL |
I/O |
S |
Tristate |
16 |
25 |
36 |
R2 |
|
|
AF1 |
LIN1TX |
|
LINFlex_1 |
O |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
descriptions signal and pinouts Package
SPC560C40x/50x SPC560B40x/50x,
|
Table 6. |
Functional port pin descriptions (continued) |
|
|
|
|
|
|
|
|
|||
|
|
|
(1) |
|
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
|||
|
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[7] |
PCR[39] |
AF0 |
GPIO[39] |
|
SIUL |
I/O |
S |
Tristate |
17 |
26 |
37 |
P3 |
|
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
— |
LIN1RX |
|
LINFlex_1 |
I |
|
|
|
|
|
|
|
|
|
— |
WKPU[12](4) |
|
WKPU |
I |
|
|
|
|
|
|
|
PC[8] |
PCR[40] |
AF0 |
GPIO[40] |
|
SIUL |
I/O |
S |
Tristate |
63 |
99 |
143 |
A1 |
|
|
|
AF1 |
LIN2TX |
|
LINFlex_2 |
O |
|
|
|
|
|
|
ID Doc |
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[9] |
PCR[41] |
AF0 |
GPIO[41] |
|
SIUL |
I/O |
S |
Tristate |
2 |
2 |
2 |
B1 |
|
14619 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
Rev |
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
LIN2RX |
|
LINFlex_2 |
I |
|
|
|
|
|
|
|
9 |
|
|
— |
WKPU[13](4) |
|
WKPU |
I |
|
|
|
|
|
|
|
PC[10] |
PCR[42] |
AF0 |
GPIO[42] |
|
SIUL |
I/O |
M |
Tristate |
13 |
22 |
28 |
M3 |
|
|
|
AF1 |
CAN1TX |
|
FlexCAN_1 |
O |
|
|
|
|
|
|
|
|
|
AF2 |
CAN4TX(11) |
|
FlexCAN_4 |
O |
|
|
|
|
|
|
|
|
|
AF3 |
MA[1] |
|
ADC |
O |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[11] |
PCR[43] |
AF0 |
GPIO[43] |
|
SIUL |
I/O |
S |
Tristate |
— |
21 |
27 |
M4 |
|
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
— |
CAN1RX |
|
FlexCAN_1 |
I |
|
|
|
|
|
|
|
|
|
— |
CAN4RX(11) |
|
FlexCAN_4 |
I |
|
|
|
|
|
|
|
|
|
— |
WKPU[5](4) |
|
WKPU |
I |
|
|
|
|
|
|
27/117 |
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|
SPC560C40x/50x SPC560B40x/50x,
descriptions signal and pinouts Package
28/117
9 Rev 14619 ID Doc
Table 6. |
Functional port pin descriptions (continued) |
|
|
|
|
|
|
|
|
|||
|
|
(1) |
|
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
|||
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[12] |
PCR[44] |
AF0 |
GPIO[44] |
|
SIUL |
I/O |
M |
Tristate |
— |
97 |
141 |
B4 |
|
|
AF1 |
E0UC[12] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
SIN_2 |
|
DSPI_2 |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[13] |
PCR[45] |
AF0 |
GPIO[45] |
|
SIUL |
I/O |
S |
Tristate |
— |
98 |
142 |
A2 |
|
|
AF1 |
E0UC[13] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
SOUT_2 |
|
DSPI_2 |
O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[14] |
PCR[46] |
AF0 |
GPIO[46] |
|
SIUL |
I/O |
S |
Tristate |
— |
3 |
3 |
C1 |
|
|
AF1 |
E0UC[14] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
SCK_2 |
|
DSPI_2 |
I/O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
EIRQ[8] |
|
SIUL |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PC[15] |
PCR[47] |
AF0 |
GPIO[47] |
|
SIUL |
I/O |
M |
Tristate |
— |
4 |
4 |
D3 |
|
|
AF1 |
E0UC[15] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
CS0_2 |
|
DSPI_2 |
I/O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[0] |
PCR[48] |
AF0 |
GPIO[48] |
|
SIUL |
I |
I |
Tristate |
— |
41 |
63 |
P12 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
GPI[4] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[1] |
PCR[49] |
AF0 |
GPIO[49] |
|
SIUL |
I |
I |
Tristate |
— |
42 |
64 |
T12 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
GPI[5] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
descriptions signal and pinouts Package
SPC560C40x/50x SPC560B40x/50x,
Table 6. Functional port pin descriptions (continued)
|
|
|
(1) |
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
||
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
||||
|
Portpin |
PCR |
Alternate function |
Function |
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[2] |
PCR[50] |
AF0 |
GPIO[50] |
SIUL |
I |
I |
Tristate |
— |
43 |
65 |
R12 |
|
|
|
|
AF1 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF2 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF3 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
— |
GPI[6] |
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[3] |
PCR[51] |
AF0 |
GPIO[51] |
SIUL |
I |
I |
Tristate |
— |
44 |
66 |
P13 |
|
|
|
|
AF1 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF2 |
— |
— |
— |
|
|
|
|
|
|
|
ID Doc |
|
|
AF3 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
— |
GPI[7] |
ADC |
I |
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
||
PD[4] |
PCR[52] |
AF0 |
GPIO[52] |
SIUL |
I |
I |
Tristate |
— |
45 |
67 |
R13 |
||
14619 |
|
|
AF1 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
AF2 |
— |
— |
— |
|
|
|
|
|
|
|
Rev |
|
|
AF3 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
— |
GPI[8] |
ADC |
I |
|
|
|
|
|
|
||
9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[5] |
PCR[53] |
AF0 |
GPIO[53] |
SIUL |
I |
I |
Tristate |
— |
46 |
68 |
T13 |
||
|
|||||||||||||
|
|
|
AF1 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF2 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF3 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
— |
GPI[9] |
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[6] |
PCR[54] |
AF0 |
GPIO[54] |
SIUL |
I |
I |
Tristate |
— |
47 |
69 |
T14 |
|
|
|
|
AF1 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF2 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF3 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
— |
GPI[10] |
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[7] |
PCR[55] |
AF0 |
GPIO[55] |
SIUL |
I |
I |
Tristate |
— |
48 |
70 |
R14 |
|
|
|
|
AF1 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
|
AF2 |
— |
— |
— |
|
|
|
|
|
|
|
29/117 |
|
|
AF3 |
— |
— |
— |
|
|
|
|
|
|
|
|
|
— |
GPI[11] |
ADC |
I |
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
SPC560C40x/50x SPC560B40x/50x,
descriptions signal and pinouts Package
30/117
9 Rev 14619 ID Doc
Table 6. |
Functional port pin descriptions (continued) |
|
|
|
|
|
|
|
|
|||
|
|
(1) |
|
|
Peripheral |
(2) |
|
RESET configuration |
|
Pin number |
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
I/Odirection |
|
|
|
|
(3) |
|||
Portpin |
PCR |
Alternate function |
Function |
|
Padtype |
LQFP64 |
LQFP100 |
LQFP144 |
LBGA208 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[8] |
PCR[56] |
AF0 |
GPIO[56] |
|
SIUL |
I |
I |
Tristate |
— |
49 |
71 |
T15 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
GPI[12] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[9] |
PCR[57] |
AF0 |
GPIO[57] |
|
SIUL |
I |
I |
Tristate |
— |
56 |
78 |
N15 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
GPI[13] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[10] |
PCR[58] |
AF0 |
GPIO[58] |
|
SIUL |
I |
I |
Tristate |
— |
57 |
79 |
N14 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
GPI[14] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[11] |
PCR[59] |
AF0 |
GPIO[59] |
|
SIUL |
I |
I |
Tristate |
— |
58 |
80 |
N16 |
|
|
AF1 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF2 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
GPI[15] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[12](8) |
PCR[60] |
AF0 |
GPIO[60] |
|
SIUL |
I/O |
J |
Tristate |
— |
60 |
82 |
M15 |
|
|
AF1 |
CS5_0 |
|
DSPI_0 |
O |
|
|
|
|
|
|
|
|
AF2 |
E0UC[24] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
ANS[4] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PD[13] |
PCR[61] |
AF0 |
GPIO[61] |
|
SIUL |
I/O |
J |
Tristate |
— |
62 |
84 |
M14 |
|
|
AF1 |
CS0_1 |
|
DSPI_1 |
I/O |
|
|
|
|
|
|
|
|
AF2 |
E0UC[25] |
|
eMIOS_0 |
I/O |
|
|
|
|
|
|
|
|
AF3 |
— |
|
— |
— |
|
|
|
|
|
|
|
|
— |
ANS[5] |
|
ADC |
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
descriptions signal and pinouts Package
SPC560C40x/50x SPC560B40x/50x,