Sony SEG-1 Service manual

SPECIAL-EFFECTS

GENERATOR

SEG-1

2V990769-1

373-Printing

-NEG-

SONY CORPORATION OF AMERICA

4747 Van Dam Stnet, Long Island City, New York 11101

PRINTED IN

USA

TABLE OF CONTENTS

General Description

Circuit Description

Transistor Voltage Chart.

Illustrations

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Test Points and Waveforms, Signal Processing Board.

Test Points and Waveforms, Sync Generator Board

Schematic Diagram, Signal Processing Board

Printed Circuit, Signal Processing Board

Schematic Diagram, Sync Generator Board

Printed Circuit, Sync Generator Board

Parts List

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Supplement

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GENERAL DESCRIPTION

INTRODUCTION

SONY Model SEG-1 is a special-effects generator with facilities for switching, fading, superimposing,

and wiping two video signals. Inputs accept up to four SONY video cameras and provisions are included to monitor the output of each camera.

may be inverted, if desired, to yield a negative picture. In addition, an internal sync generator supplies

2:l

interlace sync, or sync may be supplied from an

external source.

The SEG-1 may be used with any SONY video camera, monitor, and/or Videocorder. Refer to the Owner’s Instruction Manual for the complete operating procedure.

One channel

External sync:

Power requirements:

Power consumption: Dimensions:

Weight:

Accepts vertical and hor-

izontal sync from Series Videocorders or vertical sync (-4V p-p) from an external

sync generator. See pin

connections below.

117V, 60Hz 3-wire parallel

ground plug

watts

1/4" H

x 15 1/2" W x 10” D

lb.

CV-

2:l EIA

TECHNICAL SPECIFICATIONS

Camera video inputs:

Number of camera inputs:

Monitor video outputs:

Number of monitor outputs: 4, SO-239 UHF receptacle Number of line outputs: 2, 1-Hirschmann 6 Pin

Internal sync:

1.0

-1.4V

5 n impedance. must be supplied with composite video. 4, Hirschmann 6 Pin receptacle

1.0 upon input), sync negative,

75 Cl

2:l SELECT switch is set to INT.

p-p, sync neg.

1.4V p-p, (dependent

impedance

receptacle 1 -SO -239UHF receptacle

interlace when SYNC

Input 1

CIRCUIT DESCRIPTION

VIDEO INPUT

Figure 1 shows the block diagram of the SEG-1.

Up to four cameras, either 4 CV-Series or 4 DXC-Series

#4.

To de-

must al-

Each cam-

source-

B-

can be driven through Hirschmann connectors. velop the sync pulse in the SEG-1, Camera

ways be connected with composite video signals, while

either composite -- or non-composite -- video signal is acceptable through Camera #2, era output can be monitored through four (4) terminated SO-239 UHF receptacles.

Any combination of input selector switches is

accepted.

Video signals are balanced between A- and

channel by potentiometer

A-&+ ““r”-

VRl..

and

If the output video

Fig. 1. Block Diagram of SEG-1

levels of A- and B-channel cameras are very different, the camera lens f-stop should be readjusted.

VIDEO

one-stage amplifier, Q2, is employed in channel B.

Gain and level adjustments are accomplished by VR2 and VR3 respectively. positive picture can be obtained on channel B by means of SW-3.

DISSOLVE

INVERTER

To produce a negative picture, an inverting

Either a negative or a

by the two wipe one-shots are manipulated by resistor-transistor-logic gate IC-2 and switches SW-6 to arrange the vertical, horizontal and corner wipes.

CLAMPING

The video signal selected by mode switch SW-5 is clamped to ground during blanking time by Q5. The horizontal blanking pulse includes front and back porch, while the vertical blanking pulse has only a back porch.

(RTL)

inverters IC-1, RTL NOR

The two selected signals are independently attenuated by dissolve potentiometers VR4 and VR5, mixed by R24 and the FADE position, presented to the video amplifier.

WIPES

When mode switch

analog gates Q3 and Q4 switch rapidly between the two selected channels in accordance with the logic signals on their bases. The switched video signals are mixed by are arranged so that whenever one transistor is

turned on (turning off its video signal), the other

is turned off. This guarantees that one channel or the other feeds the monitor at all times.

WIPE LOGIC

The logic signals that control these transistors

are derived from the horizontal and vertical sync pulses. multivibrator

mined by the setting of the horizontal wipe pot VR6. At one extreme, a transition between channels is produced at the left side of the screen.

other pot extreme, a long

duced that delays the transition until the right

side of the screen.

slower (O-16 ms.

produces variable width pulses, triggered by the vertical pulse, for horizontal direction wipes. using in combination independently adjustable pots

VR6 (horizontal wipe) and VR7 (vertical wipe) and wipe selector switch, SW-6, it is possible to obtain

four corner wipes, as well as vertical and horizontal wipes.

Each horizontal pulse triggers a one-shot

(Q21/Q22)

Vertical wipe pot

The variable-duration pulses produced

R25

and, with

SW5-a

is set to WIPE,

R27

and R28. Logic signals

whose 0” time is deter-

(60~µs)

VR7

does a similar job at a

)

rate: Vertical one-shot

SW5-a

At the

pulse is pro-

Q23/Q24,

The horizontal blanking pulse is developed from

Camera #l and is a composite video signal. separator Q8 produces mixed sync, which is a positive going 6 volt pulse. multivibrator (Q 9 about 2 µs in front of the sync pulse to form the front porch.

The sync pulses are delayed by Cl6 to form the horizontal back porch. mixed sync, horizontal back porch and the vertical blanking pulse are added with diodes Dl mixed blanking. transistor, Q5.

VIDEO AMPLIFIER

A two-stage feedback amplifier employed as the final stage. impedance to drive two from Camera video amplifier.

CAMERA DRIVE

Two modes of camera drive, external and internal, are available. one interlace sync generator is installed which is phase locked to either incoming vertical pulses

(through a Hirschmann male receptacle) or to

internal 60 Hz line frequency.

After the sync generator, both the horizontal

and the vertical pulses are shaped by and

Ql7

-Q20 respectively. These pulse-shaping amplifiers can drive a 19 (75 + 4) ohm load with a 4-volt negative-going pulse.

Due to the phase difference of horizontal

driving pulses, a combination of DXC-Series and

CVC-Series cameras is not recommended.

This signal is sent to clamping

is inserted at the output of the

By means of a one-shot

/Q10),

60-µs

delayed pulse occurs

The horizontal front porch,

(Q6/Q7)

This gives low output

75-ohm

lines.

In the SEG-1, a two-to-

Mixed sync

Q13 -Q16

-D3

Sync

give

TRANSISTOR VOLTAGE CHART

SIGNAL PROCESSING BOARD

TRANSISTOR

Q1 Q2 Q3 Q4

Q5 Q6 Q7 Q8 Q9 QlO Q11 Q12 Q13 Q14 Q15 Q16 Q17 Ql8 Q19 Q20 Q21 Q22 Q23 Q24 Q25

All voltages above measured with a 20,000 ohms-per-volt VOM.

2. 80

6. 90 0 0

0. 16

2.10

7.20

6. 20

0. 08

0. 01

5. 50

0. 65

6. 60

6. 80

0. 32

0.10

0. 63

0. 08

6. 40

0. 08

7.10

0. 06

7. 0

8. 0

7. 60

0. 28

0. 05

0. 75

7. 0

1.20

0. 45

5. 0

0. 73

5. 50

6. 10

0. 45

6. 80

0. 82

6. 40

6. 10

0. 28

6. 40

6. 80

2.40

4. 20

2. 05

3. 50

11. 0

2. 30

7. 60 0

0 0

1. 65

8. 0

6. 0

4. 8

7.1

0 0 0 0

5. 90

7. 50

7. 60

LOCATION *

c-4 E-3 F-2 F-2 H-2 J-2 J-2 c-5 c-5 E-5 F-4 G-4 C-6 C-6 D-6 E-6 C-8 C-8 D-7 E-7 G-6 G-5 G-8 G-8 L-4

SYNC GENERATOR BOARD

TRANSISTOR

Q1 Q2

Q3 Q4

(FET)

(UJT)

-0.66

30°

3od

All voltages above measured with a VTVM.

SEG-1 CONTROL SETTINGS:

Channel A Level Control = Maximum (upper position) Channel B Level Control = Maximum (lower position)

LEVEL Control FADE -WIPE Selector SYNC SELECT Switch

*Refers to Schematic Diagram Coordinates

= Center = Fade = INT

55 58

0..

58”

80e

-1

FET

Gate

(

N-Type)

0 0

0. 55

75c oaf

LOCA

B-2 c-2 D-2 D-2 E-2

TION*

NOTES:

UJT

Drain

Emitter

Source

Base 2

Base 1

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