SONY KDE 55XBR950 Service Manual

KDE55XBR950

UC Model

PANEL MODULE SERVICE MANUAL

PDP Module Name

FPF55C17196UA

FLAT PANEL COLOR TV

Before doing the service operation please be sure to read this service analysis manual. This module has a lot of devices to secure the safety against the fire, electric shock, injury and harmful radiation. To maintain the safety control, please follow the instructions and remarks described in this service analysis manual.

)

1 OUTLINE

The module is a plasma display module which can be designed in there is no fan in addition to a general feature of the plasma display such as a flat type, lightness, and high-viewing-angle and terrestrial magnetism.

1.1 PANEL DIMENSION

1340(Glass

1229.4

691.2

750(Glass)

Pixel pitch(horizontal)

Pixelpitch(Vertical)

0.90mm

RGB

0.90 mm

RGB

1.2 FEATURE

1. For high definition television and monitor by Progressive method

2. For FAN Less design(Low consumption electric power)

3. Flat type・Lightness

4. Customizing of module equipped with communication function

-1-

Sub- pixel pitch(horizontal)

0.30mm

RGB

1.3 SPECIFICATION

1.3.1 Functional specification

Item NO

Specification

UA-5*

Externals

Display panel

Color Grayscale(standard)

BrightNess

Chromaticity Coordinates

Contrast Contrast in Darkroom(60Hz)

Data signal

Module size

Weight

Display size

Resolution

Pixel pitch

Sub pixel pitch

White(display load Ratio 1%,standard)

(x,y)､white 10%

Video signal (RGB each color)

1 1340 × 760 × 66mm

2 30kg

3 1229.4 × 691.2mm

(55inch: 16:9)

4 1366 × 768 pixel

5 0.90(H) × 0.90(V)mm

6 0.30(H) × 0.90(V)mm

9 RGB each color 256 Grayscale

11 1000cd/ m2

14 (0.290,0.290)

15 900:1

16 LVDS(10bit)X1 or LVDS(10bit)X2

Dot clock(max)

Sync Signal

Powersupply

Noise Shade noise at 18dB(A) or less

Guarantee environment

Horizontal Sync Signal(max)

Vertical Sync Signal

Input voltage/current

Standby electric power(max)

Temperature(operation)

Temperature(storage)

Humidity(operation)

Humidity(storage)

17 85MHz

18 50KHz(LVDS)

19 50Hz ± 1.9 / 60 ± 1.7Hz (LVDS)

20 +3.3/+5/+75-90/+50-65V

21 1W

22 25dB(A) or less

23

24

25 20 ~ 85 %RH (no condensation)

26 20 ~ 80 %RH (no condensation)

0 ~ 45 °C

*It is made to give priority when there is a delivery specification according to the customer.

DC, 0.05/7.5/7.5/6A

-2-

1.3.2 Display quality specification

Specification

Item NO

UC-5*

Non-lighting cell defect

Non-extinguishing cell defect

Flickering cell defect

High intensity cell defect

Brightness variation

Color variation White block of 10% load [9 point]

Total number (subpixel)

Density (subpixel/cm2)

Size (H x V) (subpixel)

Total number (subpixel)

Density (subpixel/ cm

Flickering lighting cell defect (sub pixel/cm

Flickering non-extinguishing cell defect

Twice or more bright point

White block of 10% load [9 point] (%)

In area adjacent 20mm [White] (%)

2

)

2

)

1 15 or less

2 2 or less

（However,1 continuousness or less）

3 1x2 or less, Or 2x1 or less

4

5 Each color 2 cells max

6 5 or less

7 Number on inside of

8 0

9 20 or less

10 10 or less

11 X: Average ± 0.020

6 or less（each color 2 or less）

（However,1 continuousness or less）

Non-extinguishing cell defect

y: Average ± 0.020

*It is made to give priority when there is a delivery specification according to the customer.

-3-

A

1.3.3 I/O Interface Specification

(1) LVDS Signal Definition and Function

A video signal (display data signal and control signal) is converted from parallel data to serial data with the LVDS transmitter and further converted into four sets of differential signals before input to this product. These signals are transmitted seven times faster than dot clock signals. The dot clock signal is converted into one set of differential signals by the transmitter before input to this product. The LVDS signal definition and function are summarized below:

No. Item Signal Name

Number

of

signals

I/O Form Content of definition

1

Video Signal Timing Signal (ODD)

2

Video Signal Timing Signal (EVEN)

Display signal

3

4

5

6 SDA 1 I/O

Clock (ODD)

Clock (EVEN)

Power down Signal

Communication

7

RA0RA0+ RA1RA1+ RA2RA2+ RA3RA3+ RA4R

4+

RB0RB0+ RB1RB1+ RB2RB2+ RB3RB3+ RB4RB4+

RACLKINRACLKIN+

PDWN 1 Input LVTTL

SCL 1 I/O

1 1 1 1 1 1 1 1 1 1

1 1

Input

LVDS

Differential

LVDS

Differential

LVDS

Differential

LVDS

Differential

LVTTL

2

(I

C)

Differential serial data signal. Input video and timing signals after differential serial conversion using a dedicated transceiver. The serial data signal is transmitted seven times faster than the base signal．

Input the clock signal after differential conversion using a dedicated transceiver. The clock signal is transmitted at the same speed as the base signal.

Low :LVDS receiver outputs are all “L”. High: Output signals are active.

2

I

C bus serial data communication signal. Communication with the control MPU of this product is enabled.

“High”: Low power consumption

8

9

10

Control

MPU Communication / Control

CPUGO 1 Input LVTTL

PDPGO 1 Input LVTTL

IRQ 1

Outpu

t

LVTTL

mode of the control MPU of this product is released.

“High”: This product is started. (CPUGO=“High” Effective)

It changes into "Low" → "High" when this product enters the undermentioned state.

1. Vcc/Va/Vs output decrease

2. Circuit abnormality detection

-4-

A

B

(2) Video Signal Definition and Function

The table below summarizes the definitions and functions of input video signals before LVDS conversion.

Item Signal name

Original Display signal (before LVDS transmittance)

Video signal

(ODD)

Video signal (EVEN)

Clock

Horizontal sync signal

Vertical sync signal

Blanking signal

DATA-RA DATA-GA DATA-BA

DATA-RB DATA-GB DATA-BB

DCLK DCLK

Hsync

Vsync

BLANKA

BLANKB

Number

of signals

Input/

output

10 10 10

2 Input

1 Input

2 Input

Input

Display data signal RA9/GA9/BA9 is the highest intensity bit. RA0/GA0/BA0 is the lowest intensity bit.

Display data signal RB9/GB9/BB9 is the highest intensity bit. RB0/GB0/BB0 is the lowest intensity bit.

Video signal timing: These signals continuously input are necessary. Data are read when these signals are fallen.

Regulates one horizontal line of data: Begins

control of the next screen when fallen.

Screen starts up control timing signal: Begins

control of the next screen when fallen.

Input the same frequency in both odd-numbered and even-numbered fields.

Display period timing signal.

H indicates the display period and L indicates the non display period.

Note:

Set this timing properly like followings, as is used internally for signal processing.

・Set the blanking period so that the number of

effective display data items in one horizontal period is 1366.

・Set the number of blanking signals in one

vertical period to 384, which is one half the number of effective scan lines.

Signal definition and function

Hsync is

Vsync is

If the

BLANK changes when the Vsync

frequency is switched, the screen display may be disturbed or brightness may change.

The screen display is restored to the normal

state later when the constant again.

BLANK length is

-5-

)

(3) Connector Specification

The connector specification is shown below. Please do not connect anything with the terminal NC.

(3-1) Signal connector [CN1]

Pin No. Signal name Pin No. Signal name

1 RA0- 2 GND(LVDS

3 RA0+ 4 SCL

5 RA1- 6 GND

7 RA1+ 8 SDA

9 RA2- 10 GND(LVDS)

11 RA2+ 12 CPUGO

13 RACLK- 14 PDPGO

15 RACLK+ 16 IRQ

17 RA3- 18 PDWN

19 RA3+ 20 GND(LVDS)

21 RA4- 22 GND

23 RA4+ 24 GND

25 GND 26 GND

27 GND 28 GND

29 GND 30 GND

DF13-30DP-1.25 V (tin-plated) (Maker: HIROSE DENKI)

[Conforming connector] Housing: DF13-30DS-1.25C Contact: DF13-2630SCF

(3-2) Signal connector [CN2]

Pin No. Signal name Pin No. Signal name

1 RA0- 2 GND(LVDS

3 RA0+ 4 SCL

5 RA1- 6 GND

7 RA1+ 8 SDA

9 RA2- 10 GND(LVDS)

11 RA2+ 12 CPUGO

13 RACLK- 14 PDPGO

15 RACLK+ 16 IRQ

17 RA3- 18 PDWN

19 RA3+ 20 GND(LVDS)

21 RA4- 22 GND

23 RA4+ 24 GND

25 GND 26 GND

27 GND 28 GND

29 GND 30 GND

DF13-30DP-1.25 V (tin-plated) (Maker: HIROSE DENKI)

[Conforming connector] Housing: DF13-30DS-1.25C Contact: DF13-2630SCF

-6-

(3-3) Power Source Connectors (PSU only is used on repair working)

(a) Power input / Signal control connector [CN3]

Pin No. Symbol

1 N.C.

2 VSAGO

3 VCEGO

4 Vrs

5 Vra

6 GND

7 GND

8 GND

9 Vpr2

10 Vcc

11 Vcc

B11B-PH-SM3-TB (Maker: JST)

[Conforming connector]

Housing: PHR-11 Contact: SPH-002T-P0.5L

(b) Power supply output connector for system [CN21]

Pin No. Symbol

1 Va

2 Va

3 Vcc

4 Vcc

5 Vcc

6 GND

7 GND

8 GND

9 Vs

10 Vs

11 Vs

B10P-VH (Maker: JST)

[Conforming connector]

Housing: VHR-10N Contact: SVH-21T-P1.1

-7-

2 SAFETY HANDLING of THE PLASMA DISPLAY

2.1 NOTES TO FOLLOW DURING SERVICING

 The work procedures shown with the Note indication are important for ensuring the

safety of the product and the servicing work. Be sure to follow these instructions.

 Before starting the work, secure a sufficient working space.

 At all times other than when adjusting and checking the product, be sure to turn OFF the

main POWER switch and disconnect the power cable from the power source of the display (jig or the display itself) during servicing.

 To prevent electric shock and breakage of PC board, start the servicing work at least 30

seconds after the main power has been turned off. Especially when installing and removing the power supply PC board and the SUS PC board in which high voltages are applied, start servicing at least 4 minutes after the main power has been turned off.

 While the main power is on, do not touch any parts or circuits other than the ones specified.

The high voltage power supply block within the PDP module has a floating ground. If any connection other than the one specified is made between the measuring equipment and the high voltage power supply block, it can result in electric shock or activation of the leakage-detection circuit breaker.

 When installing the PDP module in, and removing it from the packing carton, be sure to

have at least two persons perform the work while being careful to ensure that the flexible printed-circuit cable of the PDP module does not get caught by the packing carton.

 When the surface of the panel comes into contact with the cushioning materials, be sure to

confirm that there is no foreign matter on top of the cushioning materials before the surface of the panel comes into contact with the cushioning materials. Failure to observe this precaution may result in the surface of the panel being scratched by foreign matter.

 When handling the circuit PC board, be sure to remove static electricity from your body

before handling the circuit PC board.

 Be sure to handle the circuit PC board by holding the such large parts as the heat sink or

transformer. Failure to observe this precaution may result in the occurrence of an abnormality in the soldered areas.

 Do not stack the circuit PC boards.

Failure to observe this precaution may result in problems resulting from scratches on the parts, the deformation of parts, and short-circuits due to residual electric charge.

 Routing of the wires and fixing them in position must be done in accordance with the

original routing and fixing configuration when servicing is completed. All the wires are routed far away from the areas that become hot (such as the heat sink). These wires are fixed in position with the wire clamps so that the wires do not move, thereby ensuring that they are not damaged and their materials do not deteriorate over long periods of time. Therefore, route the cables and fix the cables to the original position and states using the wire clamps.

 Perform a safety check when servicing is completed.

Verify that the peripherals of the serviced points have not undergone any deterioration during servicing. Also verify that the screws, parts and cables removed for servicing purposes have all been returned to their proper locations in accordance with the original setup.

-8-

3 NAME and FUNCTION

4

ABUS

e

M

e

4

e

C

A

3.1 CONFIGURATION

DM

-U1

Signal Cable

Serial ID Label

-U2

Product Label

Signal Cable

P.S. Cabl

-U3

ABUS-U

Signal Cable

P.S. Cable

XBB

SD

ABUS-D1

Y- S U S

ABUS-D２

Signal Cabl

ABUS-D3

LOGI

Signal Cabl

X-SUS

ABUS-D

P.S. Cabl

-9-

3.2 Block Diagrams

γ

U

YYYY

S

X

-

S

C

A

L

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

0

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

0

A

3.2.1 Signal Diagrams

----SU

SUS B.

B.

B. B.

SUSSU

Y-SUS

MMMM

SSSS

DDDD

SSSS

DDDD

EVEN SW

Y- S C A N

EVEN SW

ODD SW

Y-SC AN

ODD SW

POS /NEG

RESET SW

ABUS U1

ABUS U1．．．．

ABUS U1ABUS U1

DMU1

DMU2 ADMU

ABUS U2

ABUS U2ABUS U2

DMU

ABUS U3

ABUS U3ABUS U3

DMU

CNU3-8CNU3-7

DMU

ABUS U4

ABUS U4．．．．

ABUS U4ABUS U4

DMU1

DMU11

XXXX BBBB BBBB

X

-SU

SUS B.

B.

-

SUSSU

B. B.

X

X-SUS

EVEN SW

X-SCAN

EVEN SW

X-SUS

ODD SW

X-SCAN

ODD SW

POS

RESET SW

SIGNA

SIGNAL

SIGNALSIGNA INPUT

INPUT

INPUT INPUT

CN1

CN2

Isk Iak Thermistors

CN4

CN31

LVD S

Analog Sw

OSC

10MHz

LVD S

I2C

DML1 ADML2 ADML

ABUS D1

ABUS D1．．．．

ABUS D1ABUS D1

comp.

V-S YN C c ont.

SCI.

Failure DET.

FLASH MEMORY

CND2-6

DML

ABUSD2

ABUSD2ABUSD2

ABUS D3

ABUS D3ABUS D3

CND3-8

CND3-9

SCAN CONTROLLER

DATA PROCESSOR ×2

RGB GAIN

DITHER /ERR DIF.

MP

APC cont.

I/O

DML

CND3-10

TIMMING ROM

SUB FIELD

PRC.

12.75MHz

OSC

12.75MHz

EEPROM

D/A

DML1

DML11

ABUS D4

ABUS D4．．．．

ABUS D4ABUS D4

25.5MHz

MEMORY

CONTROLLER

51MHz

×4

Vrs Vra Vrw Vrx Vq Vu

LOGI

LOGIC B.

LOGICLOGI

B.

B. B.

FRAME

MEMORY

CN21

CN3

CN7

CN8

CN5

CN6

-10-

3.2.2 Power Diagrams

YYYY

S

X

-

S

C

V

0

9

A

w

4

6

3

4

-

5

0

----SU

SUS B.

B.

B. B.

SUSSU

Y-SUS

SSSS

DDDD

MMMM

SSSS

DDDD

MMMM

CN3

CN31

EVEN SW

Y- S C A N

EVEN SW

ODD SW

Y-SC AN

ODD SW

POS/NEG

RESET SW

Vcc 5V Vs 85V Vx 40V Vw 190

CNU

ABUS U1

ABUS U1．．．．

ABUS U1ABUS U1

ADMU1

ADMU2 ADMU3 ADMU4 ADMU5 ADMU6 ADMU7 ADMU8 ADMU9 ADMU10 ADMU11

ABUS U2

ABUS U2ABUS U2

ABUS U3

ABUS U3ABUS U3

ABUS U4

ABUS U4．．．．

ABUS U4ABUS U4

XXXX BBBB BBBB

ADML1 ADML2 ADML3 ADML4 ADML5 ADML6 ADML7 ADML8 ADML9 ADML10 ADML11

ABUS D1

ABUS D1．．．．

ABUS D1ABUS D1

ABUSD2

ABUSD2ABUSD2

ABUS D3

ABUS D3ABUS D3

ABUS D4

ABUS D4．．．．

ABUS D4ABUS D4

CN22

Vcc 5V Va 6 3V

X

-SU

SUS B.

B.

-

SUSSU

CN2

EVEN SW

ODD SW

POS/NEG

RESET SW

Vcc 5V Vs 85V Vx 40V Vw 190V

B. B.

X-SUS

X-SCAN

X-SUS

X-SCAN

X

CN2

DC/DC

CONVERTER

Vu 35V

Vq -40V

YFVE Vy VE 18V 18V 17V

DC/DC

CONVERTER

CN3

Vpr2 3.3V

CPUgo PDPgo

from PSY(+5V/+3.3V)

from EXT.CONT.

D/

MPU

rst

LOGI

LOGIC B.

LOGICLOGI

CN

Vra Vrs Vr Vrx Vu Vq

YSTBY

B.

B. B.

XFVE Vxx VE

18V 20V 17V

DC/DC

CONVERTER

Vcc 5V

CN21

xvxwgo

RST

CN2

from PSY(+5V/+63V/+85V）

Vs 85V

-11-

3.3 FUNCTION

3.3.1 Logic board Function

(1) Data Processor

- γ adjustment(1 / 2.2 / 2.4 / 2.6 / 2.8)

- NTSC/EBU format(Color matrix) Switch

- RGB gain Control(White balance adjustment, Amplitude limitation)

- Error Diffusion Technology(Grayscale adjustment)

- Dither(Grayscale adjustment)

- Burn-in Pattern generation

(2) Data Converter

- Quasi out-line adjustment (luminous pattern control)

(3) Scan Controller

- Address driver control signal generator (ADM)

- scan driver control signal generator (SDM)

- X/Y sustain control signal generator

(4) Waveform ROM

- Waveform Pattern for drive / Timing memory

(5) MPU

- Synchronous detection

- System control

- Driving voltage(Va, Vs, Vr, Vw, Vu, Vq) Minute adjustment

- Abnormal watch (breakdown detection)/abnormal processing

- Is(sustain) current control (sustain pulse control)

- Ia(address) current control (sub-field control)

- External communication control

- Flash memory (firmware)

(6) EEPROM

- Control parameter memory

- The accumulation energizing time (Every hour).

- Abnormal status memory (16 careers)

-12-

3.3.2 Function of X-SUS Board

(1) DC/DC power supply block

Vs (+85V) Æ Vw (+190V) / Vx (+40V) / Vu (+35V) / Vq (-40V)

Vcc (+5V) Æ Vex (+16V) / XFve (+18V, floating)

(2) X switching block

Switching during address period

Switching during sustain period

Switching during reset period

(3) Current detector block

Isx (sustain) current detection

Ia (address) current detection

(4) Voltage detector block

Vs (sustain) voltage detection

Va (address) voltage detection

3.3.3 Function of Y-SUS Board

(1) DC/DC power supply block

Vcc (+5V) Æ Vey (+16V) / YFve (+18V, floating)

(2) Y Switching block

Switching during address period

Switching during sustain period

Switching during reset period

(3) Current detector block

Isy (sustain) current detection

-13-

3.4 PROTECTION FUNCTION

State of protection operation

(√:State change、、、、There is no change at the blank.)

Abnormality part

Reactivation

condition when

abnormal content

is excluded

Vw

Vx

Vs

Va

Vex

Vey

State Vw, Vx Vs Va Vex Vey Vcc Vpr

Overvoltage Stop(no latch)

Overcurrent Delay Latch

Overvoltage Stop(no latch)

Overcurrent Delay Latch

Overvoltage Latch

Low voltage Latch

Overcurrent Delay Latch

Overvoltage Latch

Low voltage Latch

Overcurrent Delay Latch

Overvoltage Stop(no latch)

Voltage

Overcurrent

pendency(no latch)

Va ux

√ √ √ √ √ √ √

AC

Re-turn

ing on

Yes

Vcc

Vpr2

Overvoltage Latch

Overcurrent Delay Latch

√ √ √ √ √ √ √

√ √ √ √ √ √ √ √ √

-14-

Yes

4 PROBLEM ANALYSIS

Y

YNY

YYY

Y

4.1 OUTLINE OF REPAIR FLOW

Client

Product

manufacturer

(Repair center)

Client claim

Repair product

and Claim contents match

Product block/PDP module block

Locating cause of problem

Is PDP module block

Defective ?

Is the Panel defective ?

PDP module sent to factory

Repair product and

claim contents match

Recheck the problem description

N

Product problem analysis/Repair

PC board replacement/Parts

N

replacement

Operation normal ?

Recheck problem

description

Y

Repair center

Product

manufacturer

(Repair center)

Client

Is the panel faulty?

PC board

unacceptable (NG) ?

Processing to prevent

recurrence

Packing/Shipment

Installation in product

N

Product runs normally ?

Return of repaired product

End of repair

Panel replacement/IC

module replacement

N

PC board

replacement/Parts

replacement

N

Heat run

Operation normal ?

N

-15-

4.2 OUTLINE OF PDP MODULE REPAIR FLOW

Receipt of returned product

(Chapter 4.3)

returned product agree with ID

Does ID of

of actual

Yes

Appearance check

Yes

Appearance unacceptable

(NG) ?

Yes

Repair of appearance

requested ?

Yes

Repair defective spots

No

Repair description and returned

product rechecked.

Perform operation test

(Chapter 4.4).

Problem recurred ?

2

Check description of

repair request.

4

No

Yes

Contents match ?

Yes

13 5

No

Problem symptom

nonrecurrence analysis mode

-16-

1

Fault mode classification (Chapter 4.5)

Fault analysis (Chapter 4.6)

Repair of faulty spots (Chapter 5)

Replace LOGIC PC board or

panel chassis ?

No

3

Perform operation test (Chapter 4.4)

Problem repaired?

Yes

Warranty test (Running)

End of repair

Yes

Adjustment (Chapter 6)

No

Shipment

-17-

Problem symptom nonrecurrence

5

analysis mode/Shipment process mode

Implement module tapping

Problem recurs ?

No

Yes

Turn off the main power

2

Perform running test (Burn-in pattern)

No

Problem recurs ?

Yes

3

-18-

4.3 CHECKING THE PRODUCT REQUESTED FOR REPAIR

Check the serial ID number of the product requested for repair before starting the problem analysis and repair. Structure of serial ID number is shown below.

(1) Checking serial ID number of PDP module (14 digits)

The serial ID number of the product that is brought in for service and that of the completed panel chassis has the structure as shown below.

The serial ID number is shown on the bar code label that is attached to the rear of the chassis (aluminum).

N9A 4 01 001A1 01A

Version No.: 01 ~ 99 A ~ Z (excluding I and O)

Lot No.: 001 ~ 999 A ~ Z (excluding I and O) 1 ~ 3

Production week code: 01 ~ 53

Production year (low digit): 0 ~ 9

Product code: N9A- model 55 type

Module product label Serial ID label of panel chassis

* The module serial ID number and the serial ID number of the completed chassis are usually the same

when the product is brought in for repair for the first time.

(2) Checking serial ID number of constituent PC boards (12 digits)

The serial ID number of the module constituent PC boards has the following structure.

The serial ID number is shown on the bar code label that is attached to each PC board.

CP 1 01 00001 1A

Version No.: 1 ~ 9 , a~z A ~ Z (excluding I and O)

Lot No.: 00001 ~ Z9999

Production week code: 01 ~ 53

Production year (low digit): 0 ~ 9

Product code: Different 2 digits for each board

-19-

4.4 OPERATION TEST PROCEDURE

d

f

Five screws

Photp 4.1 Photo 4.2

(1) Prepare the test equipment.

(2) Set the PSU board (PS-jig) by five M3X8 screw on the module o

requestedfor repair. (photo4.1)

(3) Connect the cable connector from PSU board to CN9 on logic boar

and CN21 on XSUS board. (photo4.2)

(4) Set the module of requested repair to a stand.

(5) Connect between the CN1/CN2 on the logic board and the CN5/CN7 on the interface board (I/F-jig) by particular cable. (photo4.3)

(6) Turn on the AC power to the interface board (I/F-jig).

(7) Select the signal used when a problem occurs, or full white pattern.

(8) Turn on the PDP go switch on the interface board (I/F-jig). (Then, the main

power of the module is turned on.)

Check Fault Symptom

CN21

X-SUS

CN9

LOGIC

-20-

F

Photo 4.3

＜ State of initialization＞

CN7 CN5

CN2

CN1

PDPgo switch

ON

OF

Select switch of Display size, Synchronous, and Clock signal

-21-

4.5 FAULT SYMPTOM

NO Fault

contents

Entire screen

1 After momentarily going on, the

does not light.

2

3 Single vertical line (of different

Vertical line

4 Single vertical line (of different

screen becomes black immediately or after a few seconds. (Main power is turned off.)

Screen lights dimly even on the back screen.

color) start point at center of screen

color) start point exclude at center of screen

Fault status Suspected

5

Single full vertical line (of different color)

Analysis

fault location

X-SUS,Y-SUS PSU, Panel chassis, Logic ABUSL or R

Logic Replace

procedure

and

measure

Refer to Chapter

4.6.1

Logic board

Panel chassis Logic, ABUS, ADM

Refer to Chapter

4.6.2

Panel chassis Replace

Panel

chassis

Logic Replace

Logic

board

6

Vertical bar Bar width of 1/33 of horizontal

7 Abnormal display at bar width of

8 Abnormal display at bar width of

9 Abnormal display at bar width of

10 Abnormal display at bar width of

11 Abnormal display at upper side

size or abnormal display in multiples of 1/33.

1/11 of horizontal size or multiples of 1/11 .

1/11 of horizontal size (Vertical bar of different color)

2/11 of horizontal size (Vertical bar of different color)

or lower side of horizontal size (Vertical bar of different color)

Panel chassis

(ADM)

Panel chassis

ABUS

Connection of

above boards.

Connection of

ADM,

ABUS

Connection of

ABUS

Connection of

ABUS

Connection of

ABUS and

Logic or

X-SUS and

ABUS

Refer to Chapter

4.6.2

Refer to Chapter

4.6.2

-22-

SONY KDE 55XBR950 Service Manual

CONTENTS

1 OUTLINE

1.1 PANEL DIMENSION

1.2 FEATURE

1.3 SPECIFICATION

1.3.1 Functional specification

1.3.2 Display quality specification

1.3.3 I/O Interface Specification

2 SAFETY HANDLING of THE PLASMA DISPLAY

2.1 NOTES TO FOLLOW DURING SERVICING

3 NAME and FUNCTION

3.1 CONFIGURATION

3.2 Block Diagrams

3.2.1 Signal Diagrams

3.2.2 Power Diagrams

3.3 FUNCTION

3.3.1 Logic board Function

3.3.2 Function of X-SUS Board

3.3.3 Function of Y-SUS Board

3.4 PROTECTION FUNCTION

4 PROBLEM ANALYSIS

4.1 OUTLINE OF REPAIR FLOW

4.2 OUTLINE OF PDP MODULE REPAIR FLOW

4.3 CHECKING THE PRODUCT REQUESTED FOR REPAIR

4.4 OPERATION TEST PROCEDURE

4.5 FAULT SYMPTOM